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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Hopefully someone can help me understand. I assume I should be able to access MMIO pointed to by a PCI devices Prefet= chable Memory BAR. I would think I would use EFI_PCI_IO_PROTOCOL.Mem.Read = or Write. This in turn will send the request up to EFI_PCI_ROOT_BRIDGE_IO_= PROTOCOL.Mem.Read or Write. =20 MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c: RootBridgeIoMemRea= d (Write) calls RootBridgeIoCheckParameter() to verify that the request fal= ls within the confines of the PCI root bridge. The below code verifies the= address against non-prefetchable MMIO regions and skips the prefetchable m= emory regions. Is this correct, and if so what is the method to read/write= prefetchable memory regions? If I force EFI_PCI_HOST_BRIDGE_COMBINE_MEM_P= MEM, then I can access prefetchable memory regions because they are forced = within Mem.* and MemAbove4G.* EFI_STATUS RootBridgeIoCheckParameter ( IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, IN OPERATION_TYPE OperationType, IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, IN UINT64 Address, IN UINTN Count, IN VOID *Buffer ) { ... } else if (OperationType =3D=3D MemOperation) { // // Allow Legacy MMIO access // if ((Address >=3D 0xA0000) && (Address + MultU64x32 (Count, Size)) <=3D= 0xC0000) { if ((RootBridge->Attributes & EFI_PCI_ATTRIBUTE_VGA_MEMORY) !=3D 0) { return EFI_SUCCESS; } } // // By comparing the Address against Limit we know which range to be use= d // for checking // if (Address + MultU64x32 (Count, Size) <=3D RootBridge->Mem.Limit + 1) = { Base =3D RootBridge->Mem.Base; Limit =3D RootBridge->Mem.Limit; } else { Base =3D RootBridge->MemAbove4G.Base; Limit =3D RootBridge->MemAbove4G.Limit; } } else { ... GARRETT KIRKENDALL SMTS Firmware Engineer | CTE 7171 Southwest Parkway, Austin, TX 78735 USA=20 AMD=A0=A0 facebook=A0 |=A0 amd.com