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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable No, Ard, ArmGicDisableInterrupt() does not access these registers (IPRIORITYR) -Quan From: Ard Biesheuvel Date: Friday, November 27, 2020 at 14:17 To: Quan Nguyen OS , Leif Lindholm , devel@edk2.groups.io Cc: Open Source Review , Victor Galla= rdo OS Subject: Re: [PATCH v1 1/1] ArmPkg/ArmGicDxe: fix writes to GICD_IPRIORITYR= when ARE enable On 10/28/20 2:21 AM, Quan Nguyen wrote: > According to ARM doc IHI 0069F, section 11.9.18, "Accessing the > GICD_IPRIORITYR:", "These registers are always used when affinity > routing is not enabled. When affinity routing is enabled for the > Security state of an interrupt: >=A0=A0 * GICR_IPRIORITYR is used instead of GICD_IPRIORITYR where n = =3D 0 > to 7 (that is, for SGIs and PPIs)." >=20 > The current ArmGicV3 code tries to initialize all the IPRIORITYR > registers to a default state via the Distributor (GICD), so skip > writes to the first eight IPRIORITYR registers when Affinity Routing > is Enabled. >=20 > Cc: Leif Lindholm > Cc: Ard Biesheuvel > Signed-off-by: Victor Gallardo > Signed-off-by: Quan Nguyen Isn't this already being taken into account in ArmGicDisableInterrupt()? > --- >=A0=A0 ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c | 11 +++++++++++ >=A0=A0 1 file changed, 11 insertions(+) >=20 > diff --git a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c b/ArmPkg/Drivers/A= rmGic/GicV3/ArmGicV3Dxe.c > index d7da1f198d9e..bc543502481b 100644 > --- a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c > +++ b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c > @@ -378,6 +378,7 @@ GicV3DxeInitialize ( >=A0=A0=A0=A0 UINTN=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 R= egShift; >=A0=A0=A0=A0 UINT64=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 Cpu= Target; >=A0=A0=A0=A0 UINT64=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 MpI= d; > +=A0 BOOLEAN=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 AffinityRout= ingEnabled =3D FALSE; >=A0=A0=20 >=A0=A0=A0=A0 // Make sure the Interrupt Controller Protocol is not already= installed in >=A0=A0=A0=A0 // the system. > @@ -391,11 +392,21 @@ GicV3DxeInitialize ( >=A0=A0=A0=A0 // Routing enabled. So ensure that the ARE bit is set. >=A0=A0=A0=A0 if (!FeaturePcdGet (PcdArmGicV3WithV2Legacy)) { >=A0=A0=A0=A0=A0=A0 MmioOr32 (mGicDistributorBase + ARM_GIC_ICDDCR, ARM_GIC= _ICDDCR_ARE); > +=A0=A0=A0 // If Affinity Routing is Enabled, the first 32 interrupts (SG= I and PPI) > +=A0=A0=A0 // can be programmed only through Redistributor interface (GIC= R). > +=A0=A0=A0 // Initializing the GICD_IPRIORITYR registers for these interr= upts can be > +=A0=A0=A0 // skipped as the Redistributor will be powered up and initial= ized > +=A0=A0=A0 // at the appropriate time (e.g. in EL3 by trusted firmware). > +=A0=A0=A0 AffinityRoutingEnabled =3D TRUE; >=A0=A0=A0=A0 } >=A0=A0=20 >=A0=A0=A0=A0 for (Index =3D 0; Index < mGicNumInterrupts; Index++) { >=A0=A0=A0=A0=A0=A0 GicV3DisableInterruptSource (&gHardwareInterruptV3Proto= col, Index); >=A0=A0=20 > +=A0=A0=A0 if (AffinityRoutingEnabled && Index < 32) { > +=A0=A0=A0=A0=A0 continue; > +=A0=A0=A0 } > + >=A0=A0=A0=A0=A0=A0 // Set Priority >=A0=A0=A0=A0=A0=A0 RegOffset =3D Index / 4; >=A0=A0=A0=A0=A0=A0 RegShift =3D (Index % 4) * 8; >=20