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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable 1) Add CXL 2.0 header file to comply with CXL 2.0 specification=0A= 2) CXL 2.0 header will embed Cxl11.h=0A= 3) Updated Cxl.h to point to 2.0 header file=0A= =0A= Signed-off-by: Chris Li =0A= ---=0A= MdePkg/Include/IndustryStandard/Cxl.h | 2 +-=0A= MdePkg/Include/IndustryStandard/Cxl20.h | 477 ++++++++++++++++++++++++=0A= 2 files changed, 478 insertions(+), 1 deletion(-)=0A= create mode 100644 MdePkg/Include/IndustryStandard/Cxl20.h=0A= =0A= diff --git a/MdePkg/Include/IndustryStandard/Cxl.h b/MdePkg/Include/Industr= yStandard/Cxl.h=0A= index 06c1230e3e..9ad3242e25 100644=0A= --- a/MdePkg/Include/IndustryStandard/Cxl.h=0A= +++ b/MdePkg/Include/IndustryStandard/Cxl.h=0A= @@ -12,7 +12,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent=0A= #ifndef _CXL_MAIN_H_=0A= #define _CXL_MAIN_H_=0A= =0A= -#include =0A= +#include =0A= //=0A= // CXL assigned new Vendor ID=0A= //=0A= diff --git a/MdePkg/Include/IndustryStandard/Cxl20.h b/MdePkg/Include/Indus= tryStandard/Cxl20.h=0A= new file mode 100644=0A= index 0000000000..a08251f4e9=0A= --- /dev/null=0A= +++ b/MdePkg/Include/IndustryStandard/Cxl20.h=0A= @@ -0,0 +1,477 @@=0A= +/** @file=0A= + CXL 2.0 Register definitions=0A= +=0A= + This file contains the register definitions based on the Compute Express= Link=0A= + (CXL) Specification Revision 2.0.=0A= +=0A= + Copyright (c) 2023, Ampere Computing LLC. All rights reserved.
=0A= +=0A= + SPDX-License-Identifier: BSD-2-Clause-Patent=0A= +=0A= +**/=0A= +=0A= +#ifndef CXL20_H_=0A= +#define CXL20_H_=0A= +=0A= +#include =0A= +=0A= +//=0A= +// Ensure proper structure formats=0A= +//=0A= +#pragma pack(1)=0A= +=0A= +=0A= +//=0A= +// CXL DVSEC IDs and Revisions=0A= +// Compute Express Link Specification Revision 2.0 - Chapter 8.1.1=0A= +//=0A= +#define CXL_DVSEC_ID_PCIE_DVSEC_FOR_CXL_DEVICE 0x0=0A= +#define CXL_DVSEC_ID_NON_CXL_FUNCTION_MAP 0x2=0A= +#define CXL_DVSEC_ID_CXL20_EXTENSIONS_DVSEC_FOR_PORTS 0x3=0A= +#define CXL_DVSEC_ID_GPF_DVSEC_FOR_CXL_PORTS 0x4=0A= +#define CXL_DVSEC_ID_GPF_DVSEC_FOR_CXL_DEVICES 0x5=0A= +#define CXL_DVSEC_ID_PCIE_DVSEC_FOR_FLEX_BUS_PORT 0x7=0A= +#define CXL_DVSEC_ID_REGISTER_LOCATOR 0x8=0A= +#define CXL_DVSEC_ID_MLD 0x9=0A= +#define CXL_DVSEC_ID_PCIE_DVSEC_FOR_TEST_CAPABILITY 0xA=0A= +=0A= +#define CXL20_DVSEC_REVISON_REGISTOR_LOCATOR 0x0=0A= +=0A= +//=0A= +// Register Block ID=0A= +// Compute Express Link Specification Revision 2.0 - Chapter 8.1.9.1=0A= +//=0A= +#define CXL_REGISTER_BLOCK_ID_EMPTY 0x0=0A= +#define CXL_REGISTER_BLOCK_ID_COMPONENT 0x01=0A= +#define CXL_REGISTER_BLOCK_ID_BAR_VIRTUALIZATION_ACL 0x02=0A= +#define CXL_REGISTER_BLOCK_ID_DEVICE 0x03=0A= +=0A= +//=0A= +// Component Register Block Register Ranges Offset=0A= +// Compute Express Link Specification Revision 2.0 - Chapter 8.2.4=0A= +//=0A= +#define CXL_COMPONENT_REGISTERS_RANGE_OFFSET_IO 0x0=0A= +#define CXL_COMPONENT_REGISTERS_RANGE_OFFSET_CACHE_MEM 0x1000=0A= +#define CXL_COMPONENT_REGISTERS_RANGE_OFFSET_ARB_MUX 0xE000=0A= +=0A= +//=0A= +// CXL Cache Memory Capability IDs=0A= +// Compute Express Link Specification Revision 2.0 - Chapter 8.2.5=0A= +//=0A= +#define CXL_CACHE_MEM_CAPABILITY_ID_CXL 0x1=0A= +#define CXL_CACHE_MEM_CAPABILITY_ID_RAS 0x2=0A= +#define CXL_CACHE_MEM_CAPABILITY_ID_SECURITY 0x3=0A= +#define CXL_CACHE_MEM_CAPABILITY_ID_LINK 0x4=0A= +#define CXL_CACHE_MEM_CAPABILITY_ID_HDM_DECODER 0x5=0A= +#define CXL_CACHE_MEM_CAPABILITY_ID_EXTENDED_SECURITY 0x6=0A= +#define CXL_CACHE_MEM_CAPABILITY_ID_IDE 0x7=0A= +#define CXL_CACHE_MEM_CAPABILITY_ID_SNOOP_FILTER 0x8=0A= +#define CXL_CACHE_MEM_CAPABILITY_ID_MASK 0xFFFF=0A= +=0A= +//=0A= +// Generic CXL Device Capability IDs 0x0000 ~ 0x3FFF=0A= +// Compute Express Link Specification Revision 2.0 - Chapter 8.2.8.2.1=0A= +//=0A= +#define CXL_DEVICE_CAPABILITY_ID_CAPABILITIES_ARRAY_REGISTER 0x0000= =0A= +#define CXL_DEVICE_CAPABILITY_ID_DEVICE_STATUS 0x0001= =0A= +#define CXL_DEVICE_CAPABILITY_ID_PRIMARY_MAILBOX 0x0002= =0A= +#define CXL_DEVICE_CAPABILITY_ID_SECONDARY_MAILBOX 0x0003= =0A= +=0A= +//=0A= +// Specific CXL Device Capability IDs 0x4000 ~ 0x7FFF=0A= +// Compute Express Link Specification Revision 2.0 - Chapter 8.2.8.2.1=0A= +//=0A= +// (ref: CXL 2.0 spec $8.2.8.5)=0A= +#define CXL_DEVICE_CAPABILITY_ID_MEMORY_DEVICE_STATUS 0x4000= =0A= +#define CXL_DEVICE_CAPABILITY_ID_MASK 0xFFFF= =0A= +=0A= +//=0A= +// Memory Device Status=0A= +// Compute Express Link Specification Revision 2.0 - Chapter 8.2.8.5.1.1= =0A= +//=0A= +#define CXL_MEM_DEVICE_MEDIA_STATUS_NOT_READY 0b00=0A= +#define CXL_MEM_DEVICE_MEDIA_STATUS_READY 0b01=0A= +#define CXL_MEM_DEVICE_MEDIA_STATUS_ERROR 0b10=0A= +#define CXL_MEM_DEVICE_MEDIA_STATUS_DISABLED 0b11=0A= +=0A= +//=0A= +// PCIe DVSEC for CXL Device=0A= +// Compute Express Link Specification Revision 2.0 - Chapter 8.1.3=0A= +//=0A= +typedef union {=0A= + struct {=0A= + UINT16 CacheCapable : 1; // bit 0=0A= + UINT16 IoCapable : 1; // bit 1=0A= + UINT16 MemCapable : 1; // bit 2=0A= + UINT16 MemHwInitMode : 1; // bit 3=0A= + UINT16 HdmCount : 2; // bit 4..5=0A= + UINT16 CacheWriteBackAndInvalidateCapable : 1; // bit 6=0A= + UINT16 CxlResetCapable : 1; // bit 7=0A= + UINT16 CxlResetTimeout : 3; // bit 8..10= =0A= + UINT16 CxlResetMemClrCapable : 1; // bit 11=0A= + UINT16 Reserved : 1; // bit 12=0A= + UINT16 MultipleLogicalDevice : 1; // bit 13=0A= + UINT16 ViralCapable : 1; // bit 14=0A= + UINT16 PmInitCompletionReportingCapable : 1; // bit 15=0A= + } Bits;=0A= + UINT16 Uint16;=0A= +} CXL_DVSEC_CXL_DEVICE_CAPABILITY;=0A= +=0A= +typedef union {=0A= + struct {=0A= + UINT16 CacheEnable : 1; // bit 0=0A= + UINT16 IoEnable : 1; // bit 1=0A= + UINT16 MemEnable : 1; // bit 2=0A= + UINT16 CacheSfCoverage : 5; // bit 3..7=0A= + UINT16 CacheSfGranularity : 3; // bit 8..10=0A= + UINT16 CacheCleanEviction : 1; // bit 11=0A= + UINT16 Reserved1 : 2; // bit 12..13=0A= + UINT16 ViralEnable : 1; // bit 14=0A= + UINT16 Reserved2 : 1; // bit 15=0A= + } Bits;=0A= + UINT16 Uint16;=0A= +} CXL_DVSEC_CXL_DEVICE_CONTROL;=0A= +=0A= +typedef union {=0A= + struct {=0A= + UINT16 Reserved1 : 14; // bit 0..13=0A= + UINT16 ViralStatus : 1; // bit 14=0A= + UINT16 Reserved2 : 1; // bit 15=0A= + } Bits;=0A= + UINT16 Uint16;=0A= +} CXL_DVSEC_CXL_DEVICE_STATUS;=0A= +=0A= +typedef union {=0A= + struct {=0A= + UINT16 DisableCaching : 1; // bit 0=0A= + UINT16 InitiateCacheWriteBackAndInvalidate : 1; // bit 1=0A= + UINT16 InitiateCxlReset : 1; // bit 2=0A= + UINT16 CxlResetMemClrEnable : 1; // bit 3=0A= + UINT16 Reserved : 12; // bit 4..15= =0A= + } Bits;=0A= + UINT16 Uint16;=0A= +} CXL_2_0_DVSEC_CXL_DEVICE_CONTROL2;=0A= +=0A= +typedef union {=0A= + struct {=0A= + UINT16 CacheInvalid : 1; // bit 0= =0A= + UINT16 CxlResetComplete : 1; // bit 1= =0A= + UINT16 Reserved : 13; // bit 2..= 14=0A= + UINT16 PowerManagementInitialzationComplete : 1; // bit 15= =0A= + } Bits;=0A= + UINT16 Uint16;=0A= +} CXL_2_0_DVSEC_CXL_DEVICE_STATUS2;=0A= +=0A= +typedef union {=0A= + struct {=0A= + UINT16 ConfigLock : 1; // bit 0=0A= + UINT16 Reserved : 15; // bit 1..15=0A= + } Bits;=0A= + UINT16 Uint16;=0A= +} CXL_DVSEC_CXL_DEVICE_LOCK;=0A= +=0A= +typedef union {=0A= + struct {=0A= + UINT16 CacheSizeUnit : 4; // bit 0..3=0A= + UINT16 Reserved : 4; // bit 4..7=0A= + UINT16 CacheSize : 8; // bit 8..15=0A= + } Bits;=0A= + UINT16 Uint16;=0A= +} CXL_2_0_DVSEC_CXL_DEVICE_CAPABILITY2;=0A= +=0A= +typedef union {=0A= + struct {=0A= + UINT32 MemorySizeHigh : 32; // bit 0..31=0A= + } Bits;=0A= + UINT32 Uint32;=0A= +} CXL_DVSEC_CXL_DEVICE_RANGE1_SIZE_HIGH;=0A= +=0A= +typedef union {=0A= + struct {=0A= + UINT32 MemoryInfoValid : 1; // bit 0=0A= + UINT32 MemoryActive : 1; // bit 1=0A= + UINT32 MediaType : 3; // bit 2..4=0A= + UINT32 MemoryClass : 3; // bit 5..7=0A= + UINT32 DesiredInterleave : 5; // bit 8..12=0A= + UINT32 MemoryActiveTimeout : 3; // bit 13..15=0A= + UINT32 Reserved : 12; // bit 16..27=0A= + UINT32 MemorySizeLow : 4; // bit 28..31=0A= + } Bits;=0A= + UINT32 Uint32;=0A= +} CXL_DVSEC_CXL_DEVICE_RANGE1_SIZE_LOW;=0A= +=0A= +typedef union {=0A= + struct {=0A= + UINT32 MemoryBaseHigh : 32; // bit 0..31=0A= + } Bits;=0A= + UINT32 Uint32;=0A= +} CXL_DVSEC_CXL_DEVICE_RANGE1_BASE_HIGH;=0A= +=0A= +typedef union {=0A= + struct {=0A= + UINT32 Reserved : 28; // bit 0..27=0A= + UINT32 MemoryBaseLow : 4; // bit 28..31=0A= + } Bits;=0A= + UINT32 Uint32;=0A= +} CXL_DVSEC_CXL_DEVICE_RANGE1_BASE_LOW;=0A= +=0A= +typedef union {=0A= + struct {=0A= + UINT32 MemorySizeHigh : 32; // bit 0..31=0A= + } Bits;=0A= + UINT32 Uint32;=0A= +} CXL_DVSEC_CXL_DEVICE_RANGE2_SIZE_HIGH;=0A= +=0A= +typedef union {=0A= + struct {=0A= + UINT32 MemoryInfoValid : 1; // bit 0=0A= + UINT32 MemoryActive : 1; // bit 1=0A= + UINT32 MediaType : 3; // bit 2..4=0A= + UINT32 MemoryClass : 3; // bit 5..7=0A= + UINT32 DesiredInterleave : 5; // bit 8..12=0A= + UINT32 MemoryActiveTimeout : 3; // bit 13..15=0A= + UINT32 Reserved : 12; // bit 16..27=0A= + UINT32 MemorySizeLow : 4; // bit 28..31=0A= + } Bits;=0A= + UINT32 Uint32;=0A= +} CXL_DVSEC_CXL_DEVICE_RANGE2_SIZE_LOW;=0A= +=0A= +typedef union {=0A= + struct {=0A= + UINT32 MemoryBaseHigh : 32; // bit 0..31=0A= + } Bits;=0A= + UINT32 Uint32;=0A= +} CXL_DVSEC_CXL_DEVICE_RANGE2_BASE_HIGH;=0A= +=0A= +typedef union {=0A= + struct {=0A= + UINT32 Reserved : 28; // bit 0..27=0A= + UINT32 MemoryBaseLow : 4; // bit 28..31=0A= + } Bits;=0A= + UINT32 Uint32;=0A= +} CXL_DVSEC_CXL_DEVICE_RANGE2_BASE_LOW;=0A= +=0A= +typedef struct {=0A= + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; = // offset 0x00=0A= + PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 DesignatedVendorSpeci= ficHeader1; // offset 0x04=0A= + PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 DesignatedVendorSpeci= ficHeader2; // offset 0x08=0A= + CXL_DVSEC_CXL_DEVICE_CAPABILITY DeviceCapability; = // offset 0x0A=0A= + CXL_DVSEC_CXL_DEVICE_CONTROL DeviceControl; = // offset 0x0C=0A= + CXL_DVSEC_CXL_DEVICE_STATUS DeviceStatus; = // offset 0x0E=0A= + CXL_2_0_DVSEC_CXL_DEVICE_CONTROL2 DeviceControl2; = // offset 0x10=0A= + CXL_2_0_DVSEC_CXL_DEVICE_STATUS2 DeviceStatus2; = // offset 0x12=0A= + CXL_DVSEC_CXL_DEVICE_LOCK DeviceLock; = // offset 0x14=0A= + CXL_2_0_DVSEC_CXL_DEVICE_CAPABILITY2 DeviceCapability2; = // offset 0x16=0A= + CXL_DVSEC_CXL_DEVICE_RANGE1_SIZE_HIGH DeviceRange1SizeHigh;= // offset 0x18=0A= + CXL_DVSEC_CXL_DEVICE_RANGE1_SIZE_LOW DeviceRange1SizeLow; = // offset 0x1C=0A= + CXL_DVSEC_CXL_DEVICE_RANGE1_BASE_HIGH DeviceRange1BaseHigh;= // offset 0x20=0A= + CXL_DVSEC_CXL_DEVICE_RANGE1_BASE_LOW DeviceRange1BaseLow; = // offset 0x24=0A= + CXL_DVSEC_CXL_DEVICE_RANGE2_SIZE_HIGH DeviceRange2SizeHigh;= // offset 0x28=0A= + CXL_DVSEC_CXL_DEVICE_RANGE2_SIZE_LOW DeviceRange2SizeLow; = // offset 0x2C=0A= + CXL_DVSEC_CXL_DEVICE_RANGE2_BASE_HIGH DeviceRange2BaseHigh;= // offset 0x30=0A= + CXL_DVSEC_CXL_DEVICE_RANGE2_BASE_LOW DeviceRange2BaseLow; = // offset 0x34=0A= +} CXL_2_0_DVSEC_CXL_DEVICE;=0A= +=0A= +//=0A= +// Register Locator DVSEC=0A= +// Compute Express Link Specification Revision 2.0 - Chapter 8.1.9=0A= +//=0A= +typedef union {=0A= + struct {=0A= + UINT32 RegisterBir : 3; // bit 0..2=0A= + UINT32 Reserved : 5; // bit 3..7=0A= + UINT32 RegisterBlockIdentifier : 8; // bit 8..15=0A= + UINT32 RegisterBlockOffsetLow : 16; // bit 16..31=0A= + } Bits;=0A= + UINT32 Uint32;=0A= +} CXL_REGISTER_LOCATOR_DVSEC_REGISTER_OFFSET_LOW;=0A= +=0A= +typedef union {=0A= + struct {=0A= + UINT32 RegisterBlockOffsetHigh : 32; // bit 0..31=0A= + } Bits;=0A= + UINT32 Uint32;=0A= +} CXL_REGISTER_LOCATOR_DVSEC_REGISTER_OFFSET_HIGH;=0A= +=0A= +typedef struct {=0A= + CXL_REGISTER_LOCATOR_DVSEC_REGISTER_OFFSET_LOW OffsetLow;=0A= + CXL_REGISTER_LOCATOR_DVSEC_REGISTER_OFFSET_HIGH OffsetHigh;=0A= +} CXL_REGISTER_LOCATOR_DVSEC_REGISTER_BLOCK;=0A= +=0A= +=0A= +typedef struct {=0A= + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; = // offset 0x00=0A= + PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 DesignatedVendorSpeci= ficHeader1; // offset 0x04=0A= + PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 DesignatedVendorSpeci= ficHeader2; // offset 0x08=0A= + UINT16 Reserved; = // offset 0x0A=0A= + CXL_REGISTER_LOCATOR_DVSEC_REGISTER_BLOCK RegisterBlock[1]; = // offset 0x0C=0A= +} CXL_REGISTER_LOCATOR_DVSEC;=0A= +=0A= +//=0A= +// CXL HDM Decoder Capability Header Register=0A= +// Compute Express Link Specification Revision 2.0 - Chapter 8.2.5.5=0A= +//=0A= +typedef union {=0A= + struct {=0A= + UINT32 CxlCapabilityId : 16; // bit 0..15=0A= + UINT32 CxlCapabilityVersion : 4; // bit 16..19=0A= + UINT32 CxlHdmDecoderCapabilityPointer : 12; // bit 20..31=0A= + } Bits;=0A= + UINT32 Uint32;=0A= +} CXL_HDM_DECODER_CAPABILITY_HEADER_REGISTER;=0A= +=0A= +//=0A= +// CXL HDM Decoder Capability Register=0A= +// Compute Express Link Specification Revision 2.0 - Chapter 8.2.5.12=0A= +//=0A= +typedef union {=0A= + struct {=0A= + UINT32 DecoderCount : 4; // bit 0..3=0A= + UINT32 TargetCount : 4; // bit 4..7=0A= + UINT32 A11to8InterleaveCapable : 1; // bit 8=0A= + UINT32 A14to12InterleaveCapable : 1; // bit 9=0A= + UINT32 PoisonOnDecodeErrorCapability : 1; // bit 10=0A= + UINT32 Reserved : 21; // bit 11..31=0A= + } Bits;=0A= + UINT32 Uint32;=0A= +} CXL_2_0_HDM_DECODER_CAPABILITY_REGISTER;=0A= +=0A= +typedef union {=0A= + struct {=0A= + UINT32 PoisonOnDecodeErrorEnable : 1; // bit 0=0A= + UINT32 HdmDecoderEnable : 1; // bit 1=0A= + UINT32 Reserved : 30; // bit 2..31=0A= + } Bits;=0A= + UINT32 Uint32;=0A= +} CXL_HDM_DECODER_GLOBAL_CONTROL_REGISTER;=0A= +=0A= +typedef union {=0A= + struct {=0A= + UINT32 Reserved : 28; // bit 0..27=0A= + UINT32 MemoryBaseLow : 4; // bit 28..31=0A= + } Bits;=0A= + UINT32 Uint32;=0A= +} CXL_HDM_DECODER_N_BASE_LOW_REGISTER;=0A= +=0A= +typedef union {=0A= + struct {=0A= + UINT32 MemoryBaseHigh : 32; // bit 0..31=0A= + } Bits;=0A= + UINT32 Uint32;=0A= +} CXL_HDM_DECODER_N_BASE_HIGH_REGISTER;=0A= +=0A= +typedef union {=0A= + struct {=0A= + UINT32 Reserved : 28; // bit 0..27=0A= + UINT32 MemorySizeLow : 4; // bit 28..31=0A= + } Bits;=0A= + UINT32 Uint32;=0A= +} CXL_HDM_DECODER_N_SIZE_LOW_REGISTER;=0A= +=0A= +typedef union {=0A= + struct {=0A= + UINT32 MemorySizeHigh : 32; // bit 0..31=0A= + } Bits;=0A= + UINT32 Uint32;=0A= +} CXL_HDM_DECODER_N_SIZE_HIGH_REGISTER;=0A= +=0A= +typedef union {=0A= + struct {=0A= + UINT32 InterleaveGranularity : 4; // bit 0..3=0A= + UINT32 InterleaveWays : 4; // bit 4..7=0A= + UINT32 LockOnCommit : 1; // bit 8=0A= + UINT32 Commit : 1; // bit 9=0A= + UINT32 Committed : 1; // bit 10=0A= + UINT32 ErrorNotCommitted : 1; // bit 11=0A= + UINT32 TargetDeviceType : 1; // bit 12=0A= + UINT32 Reserved : 19; // bit 13..31=0A= + } Bits;=0A= + UINT32 Uint32;=0A= +} CXL_2_0_HDM_DECODER_N_CONTROL_REGISTER;=0A= +=0A= +typedef union {=0A= + struct {=0A= + UINT32 TargetPortIdentiferWay0 : 8; // bit 0..7=0A= + UINT32 TargetPortIdentiferWay1 : 8; // bit 8..15=0A= + UINT32 TargetPortIdentiferWay2 : 8; // bit 16..23=0A= + UINT32 TargetPortIdentiferWay3 : 8; // bit 24..31=0A= + } Bits;=0A= + UINT32 Uint32;=0A= +} CXL_HDM_DECODER_N_TARGET_LIST_LOW_REGISTER;=0A= +=0A= +typedef union {=0A= + struct {=0A= + UINT32 Reserved : 28; // bit 0..27=0A= + UINT32 DpaSkipLow : 4; // bit 28..31=0A= + } Bits;=0A= + UINT32 Uint32;=0A= +} CXL_HDM_DECODER_N_DPA_SKIP_LOW_REGISTER;=0A= +=0A= +typedef union {=0A= + struct {=0A= + UINT32 TargetPortIdentiferWay4 : 8; // bit 0..7=0A= + UINT32 TargetPortIdentiferWay5 : 8; // bit 8..15=0A= + UINT32 TargetPortIdentiferWay6 : 8; // bit 16..23=0A= + UINT32 TargetPortIdentiferWay7 : 8; // bit 24..31=0A= + } Bits;=0A= + UINT32 Uint32;=0A= +} CXL_HDM_DECODER_N_TARGET_LIST_HIGH_REGISTER;=0A= +=0A= +typedef union {=0A= + struct {=0A= + UINT32 DpaSkipHigh : 32; // bit 0..31=0A= + } Bits;=0A= + UINT32 Uint32;=0A= +} CXL_HDM_DECODER_N_DPA_SKIP_HIGH_REGISTER;=0A= +=0A= +typedef union {=0A= + CXL_HDM_DECODER_N_TARGET_LIST_LOW_REGISTER TargetListLow;=0A= + CXL_HDM_DECODER_N_DPA_SKIP_LOW_REGISTER DpaSkipLow;=0A= +} CXL_HDM_DECODER_N_TARGET_LIST_OR_DPA_SKIP_LOW;=0A= +=0A= +typedef union {=0A= + CXL_HDM_DECODER_N_TARGET_LIST_HIGH_REGISTER TargetListHigh;=0A= + CXL_HDM_DECODER_N_DPA_SKIP_HIGH_REGISTER DpaSkipHigh;=0A= +} CXL_HDM_DECODER_N_TARGET_LIST_OR_DPA_SKIP_HIGH;=0A= +=0A= +typedef struct {=0A= + CXL_HDM_DECODER_N_BASE_LOW_REGISTER DecoderBaseLow; = // 0x10=0A= + CXL_HDM_DECODER_N_BASE_HIGH_REGISTER DecoderBaseHigh; = // 0x14=0A= + CXL_HDM_DECODER_N_SIZE_LOW_REGISTER DecoderSizeLow; = // 0x18=0A= + CXL_HDM_DECODER_N_SIZE_HIGH_REGISTER DecoderSizeHigh; = // 0x1c=0A= + CXL_2_0_HDM_DECODER_N_CONTROL_REGISTER DecoderControl; = // 0x20=0A= + CXL_HDM_DECODER_N_TARGET_LIST_OR_DPA_SKIP_LOW DecoderTargetListDpaSkip= Low; // 0x24=0A= + CXL_HDM_DECODER_N_TARGET_LIST_OR_DPA_SKIP_HIGH DecoderTargetListDpaSkip= High; // 0x28=0A= + UINT32 Reserved; = // 0x2C=0A= +} HDM_DECODER_N_INFO;=0A= +=0A= +typedef union {=0A= + struct {=0A= + UINT64 CxlDeviceCapabilityId : 16; // bit 0..15=0A= + UINT64 CxlDeviceCapabilityVersion : 8; // bit 16..23=0A= + UINT64 Reserved1 : 8; // bit 24..31=0A= + UINT64 CxlDeviceCapabilitiesCount : 16; // bit 32..47=0A= + UINT64 Reserved2 : 16; // bit 48..63=0A= + } Bits;=0A= + UINT64 Uint64;=0A= +} CXL_DEVICE_CAPABILITIES_ARRAY_REGISTER;=0A= +=0A= +//=0A= +// CXL Memory Status Register=0A= +// Compute Express Link Specification Revision 2.0 - Chapter 8.2.8.5=0A= +//=0A= +typedef union {=0A= + struct {=0A= + UINT64 DeviceFatal : 1; // bit 0=0A= + UINT64 FwHalt : 1; // bit 1=0A= + UINT64 MediaStatus : 2; // bit 2..3=0A= + UINT64 MailboxInterfacesReady : 1; // bit 4=0A= + UINT64 ResetNeeded : 3; // bit 5..7=0A= + UINT64 Reserved : 56; // bit 8..63=0A= + } Bits;=0A= + UINT64 Uint64;=0A= +} CXL_MEMORY_DEVICE_STATUS_REGISTER;=0A= +=0A= +#pragma pack()=0A= +=0A= +#endif=0A= --=0A= 2.34.1=