From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 7EC34940F0B for ; Wed, 23 Aug 2023 03:25:25 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=KcKi6yHHlLwsfP5l7P7MUdVTWCPeV0srcgB6bq9/D7E=; c=relaxed/simple; d=groups.io; h=ARC-Seal:ARC-Message-Signature:ARC-Authentication-Results:From:To:CC:Subject:Thread-Topic:Thread-Index:Date:Message-ID:References:In-Reply-To:Accept-Language:msip_labels:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Language:Content-Type:Content-Transfer-Encoding; s=20140610; t=1692761124; v=1; b=Itj1jK3KC6SzOVE0/uBsmzKsXQXTtIbxyV55jtjESoHcJ47wigeCleRwV7Non9WrmY+Vvy9f 4H+wkIjd/Ux940IrCLrPtyAshU6UFb+n66cPDU7Oon/L5Z8Gv/BVMrTyzcXAnjF7W4OMhflo4bO FZqDA6nZu+JBxE6nFaadPDGs= X-Received: by 127.0.0.2 with SMTP id 8fdfYY7687511xLgpFcI0oid; Tue, 22 Aug 2023 20:25:24 -0700 X-Received: from NAM12-DM6-obe.outbound.protection.outlook.com (NAM12-DM6-obe.outbound.protection.outlook.com [40.107.243.124]) by mx.groups.io with SMTP id smtpd.web10.4009.1692761123222237449 for ; Tue, 22 Aug 2023 20:25:23 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=XPlHy5vify1q0yz4t7Me+ybtqe+UQQt0aRJiyOk8JB6KoAvGprfL2QAibUwuGdUZfxrSswxaXzzH2PtgtufEeahxMxskao2PRbSjtXgyIiw7nI0Jf7apjGv9V5zp9fnWGX/8N0SYE333kT9zVTLI4lZmP/ZiBmuOZhhwqo08FZfOnhslVLyplZAfhwCCF/p56dwIZ2RazLeRS9T0x7lZsFfZs0JI3QXgs8AL9jIGjTYPbijDqu6wVLMM4YmP2IVLFqC8+C7V0p3DIgs0uTTx/ejTzQM7y6dLJhA04dvB+sB/BmSwuXjDzbX60fbWbyprWLxc2wx8r3kFgucmruqipw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=RSdYtmsMN/eu5NWpiCYv/Q7Nx1MDwoU8q/xtzRQjuv8=; b=Ud5d6+IO6f+/i2x3G3GH4uzfhtV2T/FY/6w6+O+dE90kyo0EHRk+rVLnf9G+dLP/KM8yXMfdxGoAVV7Mx6Ob0QcJOtwA9wLq40xEQfadGiW4vae3AYxqUZ6g4mKb2HNB9U7K2JE4j+jbLMMBGds17I2LAbWtVpx5WV8lVcQfAo1AtBAUnof+d/A9j+HtEBUUQaEo40/nNdNIZ2iocX4fis0SqYAEidneCv9h/EtBNPy2qaSrIqWDBED2k6Oxf4lxWwITqHaBJ7/x3V91r2r9glEHKjiEFGUkD6qGXEVPLKsCB8keEbDsqIp/GABxqwomUk8Hn4fTIojubqa8Zlflvw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=os.amperecomputing.com; dmarc=pass action=none header.from=os.amperecomputing.com; dkim=pass header.d=os.amperecomputing.com; arc=none X-Received: from SN6PR01MB4656.prod.exchangelabs.com (2603:10b6:805:cf::31) by PH0PR01MB7302.prod.exchangelabs.com (2603:10b6:510:10f::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6699.26; Wed, 23 Aug 2023 03:25:15 +0000 X-Received: from SN6PR01MB4656.prod.exchangelabs.com ([fe80::fafc:48fd:4f97:5aac]) by SN6PR01MB4656.prod.exchangelabs.com ([fe80::fafc:48fd:4f97:5aac%4]) with mapi id 15.20.6699.026; Wed, 23 Aug 2023 03:25:14 +0000 From: "Chris Li OS via groups.io" To: "Kinney, Michael D" , "Nong, Foster" , "devel@edk2.groups.io" , "Gao, Liming" CC: "Yao, Jiewen" , "Ni, Ray" , Open Source Submission Subject: Re: [edk2-devel] [PATCH v3 1/1] MdePkg: Add Cxl20.h into IndustryStandard Thread-Topic: [edk2-devel] [PATCH v3 1/1] MdePkg: Add Cxl20.h into IndustryStandard Thread-Index: AQHZ0bZm3zu5NW01xUKbgBkIrKpupq/wLkWAgAPUnoCAAhIdLoAAiRGAgAChH1I= Date: Wed, 23 Aug 2023 03:25:14 +0000 Message-ID: References: In-Reply-To: Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: msip_labels: MSIP_Label_5b82cb1d-c2e0-4643-920a-bbe7b2d7cc47_Enabled=True;MSIP_Label_5b82cb1d-c2e0-4643-920a-bbe7b2d7cc47_SiteId=3bc2b170-fd94-476d-b0ce-4229bdc904a7;MSIP_Label_5b82cb1d-c2e0-4643-920a-bbe7b2d7cc47_SetDate=2023-08-23T03:25:12.493Z;MSIP_Label_5b82cb1d-c2e0-4643-920a-bbe7b2d7cc47_Name=Confidential;MSIP_Label_5b82cb1d-c2e0-4643-920a-bbe7b2d7cc47_ContentBits=0;MSIP_Label_5b82cb1d-c2e0-4643-920a-bbe7b2d7cc47_Method=Standard; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: SN6PR01MB4656:EE_|PH0PR01MB7302:EE_ x-ms-office365-filtering-correlation-id: 495202d0-a4a8-4fc7-cfa4-08dba38890d7 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam-message-info: 4W7/jxjVfK9WjFG1U6x8MLpPIz1ieForYYcDFZtqEzgcMcTRairH+NMN8m2CPYuCAEP63M4hLreiH0BKuhlxETa7OYCgYn5LzTx2DBOhUmgtZYPcMWhwjCme3LfQ/STuKqic5KcfXr79xIheWGOxlznjAeY5awYJRg/RO/cD7Ol5AkkXqna33aY8uuoQehcZnAwFcJ4AXUU8FxjupOr1Ji+qqKbPX3BKxPon1IUwX/PBW+Mzlfff06Xu2KrnOCcImi4+E+d7LXHz5p3WM8eK2VaM8RXUtx0e+Ptq10mQXnJHz1sZXqy8qFxwGLKcTejJa4JGtZWnAOHrgALhyeYs3traNbvUlZXiFtfs/uHIACJKQG/h1qHvQbfdh+bXi3uk5SW/sq8cR6GXnjsw0RMDyGUoM22NTFjDAD7l9RAewggOGJqBnhJuxk8ECiTX16pXS6HAx90GVzj4VZDgTy1phlhSAx801vcFkAIYWv6kxF6B3PXer8LbS6LMrdbZV/lerKW8rzcaHTAu0eluC/nEFj/RPhXZLee8Vhh6vPoRtEuKgDzz552e79ma9MJ+lWwuBXogE0+d/yuTEUL07ayZCfw743rVYNn8wyZvyFBZ5h0= x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?iso-8859-1?Q?2r2+fn+/GcrxhHp5J+vOZrVXdSYtAwQ4ctdZSPI/6C5uEdJqyVEVBgAs2b?= =?iso-8859-1?Q?1XlFN0Ry8pfOKAh419RWbnsdcE2Wps6dKjupUvHRUWhG+Lwu2Ro1VK9hS/?= =?iso-8859-1?Q?pptq6HzTVGitG+7pNqwbep8wTEBkiaz3Lba+2bFvM8EoOBCNACVwayxOCR?= =?iso-8859-1?Q?o9sKuo0vNVovauSZo+nCqpCzlYuJWaongZ54YjUoIbtrBzQeMWq2K2+MLQ?= =?iso-8859-1?Q?SHuBa4/JpjcpZjJVJLUrTPZeHOCT77QKDxwdmN/eOgAMul5ecCZb7NFLeD?= =?iso-8859-1?Q?PuNicdhERQ83MXHes58sLB3HAKhgWAr2RLqwMwdyNoKAPW948dInXJ4Qzg?= =?iso-8859-1?Q?Qktm31cwQqC8xnFvhaL28xofqilMH9z4521r/MpUZFx5ilg1o45XM0O59u?= =?iso-8859-1?Q?tOnN1MmTH6sfp1z0ZKbkCwDPeso+lu5h/6+FIBdz6dcIxg4if9hxhNy6lW?= =?iso-8859-1?Q?WJ5XBxuNs2QbSGChhIhOagIgI6GBqO8UXOJZBCAQGtD5iOFc+2dMhoyxxK?= =?iso-8859-1?Q?/0iDRTuqieR1PCimMWSJlww6A39dVzX4nCktWIkpQYXAmD2pBc4DNJhqGF?= =?iso-8859-1?Q?34ZGCGZUACgRSSrWiKRJP1Bza+VCem8u0BXg3ReDL7gewo4s5ATUvZYrMR?= =?iso-8859-1?Q?xdtFbgiWv2OGAfdXN/Ilrk3lNhCCK12lleKpTu3uYKw9QSnq4bZVudgDrL?= =?iso-8859-1?Q?mqvCWqh7hQ/SZwxHu2zSIUoMzdsZ/Itbthq+uf7a54PnU/97zbmASmfRbh?= =?iso-8859-1?Q?KTDpahL7RxloOICQO5yaW5ZKvDbzVyXUj3zcuuCq+TUvpG8seOVQKhmQQN?= =?iso-8859-1?Q?Bp1Wm81cDW/9YxpChVqy13nQOQF03QH7+S5/mcDcSRgzX6JDw2YDGvAoP9?= =?iso-8859-1?Q?n7qa5fuVeGbvsG0QWUxmFgj5FsfjvwoFSH0nvyQfwB3Kt0qC6iTKDxRmWe?= =?iso-8859-1?Q?hp6obD7tz05zog38Zb5mh5faCgY4C0klguSTEFPAMOFH8fwXd4KL5l+tt7?= =?iso-8859-1?Q?Gvu0ssCdKu/VZ/NYvTMNVfJzqpu7YRt+iUHviOA5VqhrGewOczUFIwQjdg?= =?iso-8859-1?Q?vAUsbdi2/+RZIq3O8CiRlbajpl0TG/zksnngduKyH4BW6LR7VGamkQnROo?= =?iso-8859-1?Q?gXd2byRU9qED/yfcO02YB1tC/gD+8QnP9+TFszU2wVUlClCu11u4UpNmOR?= =?iso-8859-1?Q?7BH6jdYlJXvOL1ev1SMmHWvyFsbzvS/+wj3lvgGMuEVMOy4xhq30qS8gRJ?= =?iso-8859-1?Q?OqP3AbM2a05l3LyPPE9+l3D1W8f6ILjCw32xEKFUovF9iGNvGbwleJPqhm?= =?iso-8859-1?Q?tg4/vhOXLXDA8DZicbhn6WFAz2nhnxY4sWlUk9gARQo30BYvIupKjUCU36?= =?iso-8859-1?Q?6rzKqQMSJXPLz1JHb9OxKjEaKAT4U53GITgjvod2WuvCHWExPwfk6A9/e0?= =?iso-8859-1?Q?eb3Dp5vutHmbPg2vFRpOgzOAZgEqa8uEzi1+zhj5oOgjaekQZc55BB31ue?= =?iso-8859-1?Q?6zjO65xnsoPb+r0N6HcRZEthDmooMY68emdIiTJu33pI4clkdUbzxi/zuM?= =?iso-8859-1?Q?D4UPGCjvo4PXSAN9GAgGTD4QnY+ymjuuJQFdJ4JsHiFmaIZQ8npV4B5Iaf?= =?iso-8859-1?Q?+sxsC96ihocjlL/L4wxeUliiSjma6asN2g/B6gO6+4Z3z6BuCGGzRe2g?= =?iso-8859-1?Q?=3D=3D?= MIME-Version: 1.0 X-OriginatorOrg: os.amperecomputing.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: SN6PR01MB4656.prod.exchangelabs.com X-MS-Exchange-CrossTenant-Network-Message-Id: 495202d0-a4a8-4fc7-cfa4-08dba38890d7 X-MS-Exchange-CrossTenant-originalarrivaltime: 23 Aug 2023 03:25:14.3465 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3bc2b170-fd94-476d-b0ce-4229bdc904a7 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: GP29GBUy47uIDrcO7DCGouy5VJbxmrZ7L4K1lbjgJ17XFeMTVsY1yUEqzJhqkSdZUOxavivOKlF96Qzfa2X1PFLlYHN2OhJQyoLj6YgJXpHr4ZgK6wuw69WOZJciowJ3 X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR01MB7302 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,chrisli@os.amperecomputing.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: 9OzntHRxl2CM1VFr1sfqx4GLx7686176AA= Content-Language: en-US Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=Itj1jK3K; dmarc=none; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io Thanks and will send v4 soon. ________________________________________ From: Kinney, Michael D Sent: Wednesday, August 23, 2023 1:47 AM To: Chris Li OS; Nong, Foster; devel@edk2.groups.io; Gao, Liming Cc: Yao, Jiewen; Ni, Ray; Open Source Submission; Kinney, Michael D Subject: RE: [edk2-devel] [PATCH v3 1/1] MdePkg: Add Cxl20.h into IndustryS= tandard Yes. Mike > -----Original Message----- > From: Chris Li OS > Sent: Tuesday, August 22, 2023 2:42 AM > To: Nong, Foster ; Kinney, Michael D > ; devel@edk2.groups.io; Gao, Liming > > Cc: Yao, Jiewen ; Ni, Ray ; Open > Source Submission > Subject: Re: [edk2-devel] [PATCH v3 1/1] MdePkg: Add Cxl20.h into > IndustryStandard > > Hi Mike and Foster, > So the preferred definition is as below? > > RegisterBlock[]; // offset 0x0C > > ________________________________________ > From: Nong, Foster > Sent: Monday, August 21, 2023 9:59 AM > To: Kinney, Michael D; Chris Li OS; devel@edk2.groups.io; Gao, Liming > Cc: Yao, Jiewen; Ni, Ray; Open Source Submission > Subject: RE: [edk2-devel] [PATCH v3 1/1] MdePkg: Add Cxl20.h into > IndustryStandard > > Hi Mike, > > Yes. In CXL SPEC chapter 8.1.9, the number of register blocks need > calculate from DVSEC length value of DVSEC header1 register. > > -----Original Message----- > From: Kinney, Michael D > Sent: Friday, August 18, 2023 11:30 PM > To: Chris Li OS ; devel@edk2.groups.io; > Nong, Foster ; Gao, Liming > > Cc: Yao, Jiewen ; Ni, Ray ; Open > Source Submission ; Kinney, Michael D > > Subject: RE: [edk2-devel] [PATCH v3 1/1] MdePkg: Add Cxl20.h into > IndustryStandard > > Is RegisterBlock a flexible array member? > > If so, then [] is the compatible syntax. > > Mike > > > -----Original Message----- > > From: Chris Li OS > > Sent: Friday, August 18, 2023 2:29 AM > > To: devel@edk2.groups.io; Nong, Foster ; Gao, > > Liming > > Cc: Yao, Jiewen ; Ni, Ray ; > > Kinney, Michael D ; Open Source Submission > > > > Subject: [edk2-devel] [PATCH v3 1/1] MdePkg: Add Cxl20.h into > > IndustryStandard > > > > Absorbed Foster's input with minor delta. > > @Nong, Foster @Liming and all kindly help review/vote again. > > > > One change compared with Intel's proposal is the below line, we prefer > > [1] style to be safer to work across all compilers. > > Let us know if you folks have different suggestions here. > > > > > > - CXL_DVSEC_REGISTER_LOCATOR_REGISTER_BLOCK > > RegisterBlock[0]; // offset 0x0C > > + CXL_DVSEC_REGISTER_LOCATOR_REGISTER_BLOCK > > RegisterBlock[1]; // offset 0x0C > > > > > > Thanks all! > > > > ----- > > 1) Add CXL 2.0 header file to comply with CXL 2.0 specification > > 2) CXL 2.0 header will embed Cxl11.h > > 3) Updated Cxl.h to point to 2.0 header file > > > > Signed-off-by: Chris Li > > --- > > MdePkg/Include/IndustryStandard/Cxl.h | 2 +- > > MdePkg/Include/IndustryStandard/Cxl20.h | 465 > > ++++++++++++++++++++++++ > > 2 files changed, 466 insertions(+), 1 deletion(-) create mode 100644 > > MdePkg/Include/IndustryStandard/Cxl20.h > > > > diff --git a/MdePkg/Include/IndustryStandard/Cxl.h > > b/MdePkg/Include/IndustryStandard/Cxl.h > > index 06c1230e3e..9ad3242e25 100644 > > --- a/MdePkg/Include/IndustryStandard/Cxl.h > > +++ b/MdePkg/Include/IndustryStandard/Cxl.h > > @@ -12,7 +12,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > > #ifndef _CXL_MAIN_H_ #define _CXL_MAIN_H_ > > > > -#include > > +#include > > // > > // CXL assigned new Vendor ID > > // > > diff --git a/MdePkg/Include/IndustryStandard/Cxl20.h > > b/MdePkg/Include/IndustryStandard/Cxl20.h > > new file mode 100644 > > index 0000000000..a5fe22b4a2 > > --- /dev/null > > +++ b/MdePkg/Include/IndustryStandard/Cxl20.h > > @@ -0,0 +1,465 @@ > > +/** @file > > + CXL 2.0 Register definitions > > + > > + This file contains the register definitions based on the Compute > > Express Link > > + (CXL) Specification Revision 2.0. > > + > > + Copyright (c) 2023, Ampere Computing LLC. All rights reserved.
> > + > > + SPDX-License-Identifier: BSD-2-Clause-Patent > > + > > +**/ > > +#ifndef CXL20_H_ > > +#define CXL20_H_ > > + > > +#include > > + > > +// > > +// CXL DVSEC IDs > > +// Compute Express Link Specification Revision 2.0 - Chapter 8.1.1 // > > +#define CXL_DVSEC_ID_PCIE_DVSEC_FOR_CXL_DEVICE 0x0 > > +#define CXL_DVSEC_ID_NON_CXL_FUNCTION_MAP 0x2 > > +#define CXL_DVSEC_ID_CXL20_EXTENSIONS_DVSEC_FOR_PORTS 0x3 > > +#define CXL_DVSEC_ID_GPF_DVSEC_FOR_CXL_PORTS 0x4 > > +#define CXL_DVSEC_ID_GPF_DVSEC_FOR_CXL_DEVICES 0x5 > > +#define CXL_DVSEC_ID_PCIE_DVSEC_FOR_FLEX_BUS_PORT 0x7 > > +#define CXL_DVSEC_ID_REGISTER_LOCATOR 0x8 > > +#define CXL_DVSEC_ID_MLD 0x9 > > +#define CXL_DVSEC_ID_PCIE_DVSEC_FOR_TEST_CAPABILITY 0xA > > + > > +// > > +// Register Block ID > > +// Compute Express Link Specification Revision 2.0 - Chapter 8.1.9.1 > > +// > > +#define CXL_REGISTER_BLOCK_ID_EMPTY 0x0 > > +#define CXL_REGISTER_BLOCK_ID_COMPONENT 0x1 > > +#define CXL_REGISTER_BLOCK_ID_BAR_VIRTUALIZATION_ACL 0x2 > > +#define CXL_REGISTER_BLOCK_ID_DEVICE 0x3 > > + > > +// > > +// CXL component register layout > > +// Compute Express Link Specification Revision 2.0 - Chapter 8.2.4 // > > +//|------------------------------------| > > +//|--------- Range & Type -------------| > > +//|------------------------------------| IO Base - 0KB > > +//| (0KB - 4KB)IO Regs | > > +//|------------------------------------| Cache and Mem Base - 4KB > > +//| {4KB - 8KB)Cache & Mem Regs | > > +//|------------------------------------| Implementation Spec Regs > > +Base - > > 8KB > > +//| (8KB - 56KB)Implement Spec Regs| > > +//|------------------------------------| ARB/Mux Regs Base - 56KB > > +//| (56KB - 57KB)ARBMUX Regs | > > +//|------------------------------------| Reserved Base - 57KB > > +//| (57KB - 63KB)Reserved | > > +//|------------------------------------| End 64KB // // Component > > +Register Block Register Ranges Offset // > > +#define CXL_COMPONENT_REGISTER_RANGE_OFFSET_IO 0x0 > > +#define CXL_COMPONENT_REGISTER_RANGE_OFFSET_CACHE_MEM 0x1000 > > +#define CXL_COMPONENT_REGISTER_RANGE_OFFSET_ARB_MUX 0xE000 > > + > > + > > +// > > +// CXL Cache Memory Capability IDs > > +// Compute Express Link Specification Revision 2.0 - Chapter 8.2.5 // > > +#define CXL_CACHE_MEM_CAPABILITY_ID_CXL 0x1 > > +#define CXL_CACHE_MEM_CAPABILITY_ID_RAS 0x2 > > +#define CXL_CACHE_MEM_CAPABILITY_ID_SECURITY 0x3 > > +#define CXL_CACHE_MEM_CAPABILITY_ID_LINK 0x4 > > +#define CXL_CACHE_MEM_CAPABILITY_ID_HDM_DECODER 0x5 > > +#define CXL_CACHE_MEM_CAPABILITY_ID_EXTENDED_SECURITY 0x6 > > +#define CXL_CACHE_MEM_CAPABILITY_ID_IDE 0x7 > > +#define CXL_CACHE_MEM_CAPABILITY_ID_SNOOP_FILTER 0x8 > > +#define CXL_CACHE_MEM_CAPABILITY_ID_MASK 0xFFFF > > + > > +// > > +// Generic CXL Device Capability IDs 0x0000 ~ 0x3FFF // Compute > > +Express Link Specification Revision 2.0 - Chapter 8.2.8.2.1 // > > +#define CXL_DEVICE_CAPABILITY_ID_CAPABILITIES_ARRAY_REGISTER 0x0000 > > +#define CXL_DEVICE_CAPABILITY_ID_DEVICE_STATUS 0x0001 > > +#define CXL_DEVICE_CAPABILITY_ID_PRIMARY_MAILBOX 0x0002 > > +#define CXL_DEVICE_CAPABILITY_ID_SECONDARY_MAILBOX 0x0003 > > + > > +// > > +// Specific CXL Device Capability IDs 0x4000 ~ 0x7FFF // Compute > > +Express Link Specification Revision 2.0 - Chapter 8.2.8.2.1 > > and 8.2.8.5 > > + > > +// > > +#define CXL_DEVICE_CAPABILITY_ID_MEMORY_DEVICE_STATUS 0x4000 > > +#define CXL_DEVICE_CAPABILITY_ID_MASK 0xFFFF > > + > > +// > > +// Memory Device Status > > +// Compute Express Link Specification Revision 2.0 - Chapter > > +8.2.8.5.1.1 // > > +#define CXL_MEM_DEVICE_MEDIA_STATUS_NOT_READY 0x0 > > +#define CXL_MEM_DEVICE_MEDIA_STATUS_READY 0x1 > > +#define CXL_MEM_DEVICE_MEDIA_STATUS_ERROR 0x2 > > +#define CXL_MEM_DEVICE_MEDIA_STATUS_DISABLED 0x3 > > + > > +// > > +// Ensure proper structure formats > > +// > > +#pragma pack(1) > > + > > +// > > +// PCIe DVSEC for CXL Device > > +// Compute Express Link Specification Revision 2.0 - Chapter 8.1.3 // > > +typedef union { > > + struct { > > + UINT16 CacheCapable : 1; // bit 0 > > + UINT16 IoCapable : 1; // bit 1 > > + UINT16 MemCapable : 1; // bit 2 > > + UINT16 MemHwInitMode : 1; // bit 3 > > + UINT16 HdmCount : 2; // bit > 4..5 > > + UINT16 CacheWriteBackAndInvalidateCapable : 1; // bit 6 > > + UINT16 CxlResetCapable : 1; // bit 7 > > + UINT16 CxlResetTimeout : 3; // bit > 8..10 > > + UINT16 CxlResetMemClrCapable : 1; // bit 11 > > + UINT16 Reserved : 1; // bit 12 > > + UINT16 MultipleLogicalDevice : 1; // bit 13 > > + UINT16 ViralCapable : 1; // bit 14 > > + UINT16 PmInitCompletionReportingCapable : 1; // bit 15 > > + } Bits; > > + UINT16 Uint16; > > +} CXL_DVSEC_CXL_DEVICE_CAPABILITY; > > + > > +typedef union { > > + struct { > > + UINT16 CacheEnable : 1; // bit 0 > > + UINT16 IoEnable : 1; // bit 1 > > + UINT16 MemEnable : 1; // bit 2 > > + UINT16 CacheSfCoverage : 5; // bit 3..7 > > + UINT16 CacheSfGranularity : 3; // bit 8..10 > > + UINT16 CacheCleanEviction : 1; // bit 11 > > + UINT16 Reserved1 : 2; // bit 12..13 > > + UINT16 ViralEnable : 1; // bit 14 > > + UINT16 Reserved2 : 1; // bit 15 > > + } Bits; > > + UINT16 Uint16; > > +} CXL_DVSEC_CXL_DEVICE_CONTROL; > > + > > +typedef union { > > + struct { > > + UINT16 Reserved1 : 14; // bit 0..13 > > + UINT16 ViralStatus : 1; // bit 14 > > + UINT16 Reserved2 : 1; // bit 15 > > + } Bits; > > + UINT16 Uint16; > > +} CXL_DVSEC_CXL_DEVICE_STATUS; > > + > > +typedef union { > > + struct { > > + UINT16 DisableCaching : 1; // bit 0 > > + UINT16 InitiateCacheWriteBackAndInvalidate : 1; // bit 1 > > + UINT16 InitiateCxlReset : 1; // bit 2 > > + UINT16 CxlResetMemClrEnable : 1; // bit 3 > > + UINT16 Reserved : 12; // bit > 4..15 > > + } Bits; > > + UINT16 Uint16; > > +} CXL_DVSEC_CXL_DEVICE_CONTROL2; > > + > > +typedef union { > > + struct { > > + UINT16 CacheInvalid : 1; // bit > 0 > > + UINT16 CxlResetComplete : 1; // bit > 1 > > + UINT16 Reserved : 13; // bit > > 2..14 > > + UINT16 PowerManagementInitialzationComplete : 1; // bit > > 15 > > + } Bits; > > + UINT16 Uint16; > > +} CXL_DVSEC_CXL_DEVICE_STATUS2; > > + > > +typedef union { > > + struct { > > + UINT16 ConfigLock : 1; // bit 0 > > + UINT16 Reserved : 15; // bit 1..15 > > + } Bits; > > + UINT16 Uint16; > > +} CXL_DVSEC_CXL_DEVICE_LOCK; > > + > > +typedef union { > > + struct { > > + UINT16 CacheSizeUnit : 4; // bit 0..3 > > + UINT16 Reserved : 4; // bit 4..7 > > + UINT16 CacheSize : 8; // bit 8..15 > > + } Bits; > > + UINT16 Uint16; > > +} CXL_DVSEC_CXL_DEVICE_CAPABILITY2; > > + > > +typedef union { > > + struct { > > + UINT32 MemorySizeHigh : 32; // bit 0..31 > > + } Bits; > > + UINT32 Uint32; > > +} CXL_DVSEC_CXL_DEVICE_RANGE_SIZE_HIGH; > > + > > +typedef union { > > + struct { > > + UINT32 MemoryInfoValid : 1; // bit 0 > > + UINT32 MemoryActive : 1; // bit 1 > > + UINT32 MediaType : 3; // bit 2..4 > > + UINT32 MemoryClass : 3; // bit 5..7 > > + UINT32 DesiredInterleave : 5; // bit 8..12 > > + UINT32 MemoryActiveTimeout : 3; // bit 13..15 > > + UINT32 Reserved : 12; // bit 16..27 > > + UINT32 MemorySizeLow : 4; // bit 28..31 > > + } Bits; > > + UINT32 Uint32; > > +} CXL_DVSEC_CXL_DEVICE_RANGE_SIZE_LOW; > > + > > +typedef union { > > + struct { > > + UINT32 MemoryBaseHigh : 32; // bit 0..31 > > + } Bits; > > + UINT32 Uint32; > > +} CXL_DVSEC_CXL_DEVICE_RANGE_BASE_HIGH; > > + > > +typedef union { > > + struct { > > + UINT32 Reserved : 28; // bit 0..27 > > + UINT32 MemoryBaseLow : 4; // bit 28..31 > > + } Bits; > > + UINT32 Uint32; > > +} CXL_DVSEC_CXL_DEVICE_RANGE_BASE_LOW; > > + > > + > > +typedef struct { > > + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; > > // offset 0x00 > > + PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 DvsecHeader1; > > // offset 0x04 > > + PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 DvsecHeader2; > > // offset 0x08 > > + CXL_DVSEC_CXL_DEVICE_CAPABILITY DeviceCapability; > > // offset 0x0A > > + CXL_DVSEC_CXL_DEVICE_CONTROL DeviceControl; > > // offset 0x0C > > + CXL_DVSEC_CXL_DEVICE_STATUS DeviceStatus; > > // offset 0x0E > > + CXL_DVSEC_CXL_DEVICE_CONTROL2 DeviceControl2; > > // offset 0x10 > > + CXL_DVSEC_CXL_DEVICE_STATUS2 DeviceStatus2; > > // offset 0x12 > > + CXL_DVSEC_CXL_DEVICE_LOCK DeviceLock; > > // offset 0x14 > > + CXL_DVSEC_CXL_DEVICE_CAPABILITY2 > DeviceCapability2; > > // offset 0x16 > > + CXL_DVSEC_CXL_DEVICE_RANGE_SIZE_HIGH > > DeviceRange1SizeHigh; // offset 0x18 > > + CXL_DVSEC_CXL_DEVICE_RANGE_SIZE_LOW > > DeviceRange1SizeLow; // offset 0x1C > > + CXL_DVSEC_CXL_DEVICE_RANGE_BASE_HIGH > > DeviceRange1BaseHigh; // offset 0x20 > > + CXL_DVSEC_CXL_DEVICE_RANGE_BASE_LOW > > DeviceRange1BaseLow; // offset 0x24 > > + CXL_DVSEC_CXL_DEVICE_RANGE_SIZE_HIGH > > DeviceRange2SizeHigh; // offset 0x28 > > + CXL_DVSEC_CXL_DEVICE_RANGE_SIZE_LOW > > DeviceRange2SizeLow; // offset 0x2C > > + CXL_DVSEC_CXL_DEVICE_RANGE_BASE_HIGH > > DeviceRange2BaseHigh; // offset 0x30 > > + CXL_DVSEC_CXL_DEVICE_RANGE_BASE_LOW > > DeviceRange2BaseLow; // offset 0x34 > > +} CXL_DVSEC_CXL_DEVICE; > > + > > +#define CXL_DVSEC_CXL_DEVICE_REVISION_1 0x1 > > + > > +// > > +// Register Locator DVSEC > > +// Compute Express Link Specification Revision 2.0 - Chapter 8.1.9 // > > + > > +typedef union { > > + struct { > > + UINT32 RegisterBir : 3; // bit 0..2 > > + UINT32 Reserved : 5; // bit 3..7 > > + UINT32 RegisterBlockIdentifier : 8; // bit 8..15 > > + UINT32 RegisterBlockOffsetLow : 16; // bit 16..31 > > + } Bits; > > + UINT32 Uint32; > > +} CXL_DVSEC_REGISTER_LOCATOR_REGISTER_OFFSET_LOW; > > + > > +typedef union { > > + struct { > > + UINT32 RegisterBlockOffsetHigh : 32; // bit 0..31 > > + } Bits; > > + UINT32 Uint32; > > +} CXL_DVSEC_REGISTER_LOCATOR_REGISTER_OFFSET_HIGH; > > + > > +typedef struct { > > + CXL_DVSEC_REGISTER_LOCATOR_REGISTER_OFFSET_LOW OffsetLow; > > + CXL_DVSEC_REGISTER_LOCATOR_REGISTER_OFFSET_HIGH OffsetHigh; > > +} CXL_DVSEC_REGISTER_LOCATOR_REGISTER_BLOCK; > > + > > +typedef struct { > > + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; > > // offset 0x00 > > + PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 DvsecHeader1; > > // offset 0x04 > > + PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 DvsecHeader2; > > // offset 0x08 > > + UINT16 Reserved; > > // offset 0x0A > > + CXL_DVSEC_REGISTER_LOCATOR_REGISTER_BLOCK > > RegisterBlock[1]; // offset 0x0C > > + > > +} CXL_DVSEC_REGISTER_LOCATOR; > > + > > +#define CXL_DVSEC_REGISTER_LOCATOR_REVISION_0 0x0 > > + > > +// > > +// CXL HDM Decoder Capability Header Register // Compute Express Link > > +Specification Revision 2.0 - Chapter 8.2.5.5 // typedef union { > > + struct { > > + UINT32 CxlCapabilityId : 16; // bit 0..15 > > + UINT32 CxlCapabilityVersion : 4; // bit 16..19 > > + UINT32 CxlHdmDecoderCapabilityPointer : 12; // bit 20..31 > > + } Bits; > > + UINT32 Uint32; > > +} CXL_HDM_DECODER_CAPABILITY_HEADER_REGISTER; > > + > > +// > > +// CXL HDM Decoder Capability Register // Compute Express Link > > +Specification Revision 2.0 - Chapter 8.2.5.12 // typedef union { > > + struct { > > + UINT32 DecoderCount : 4; // bit 0..3 > > + UINT32 TargetCount : 4; // bit 4..7 > > + UINT32 InterleaveCapableA11to8 : 1; // bit 8 > > + UINT32 InterleaveCapableA14to12 : 1; // bit 9 > > + UINT32 PoisonOnDecodeErrorCapability : 1; // bit 10 > > + UINT32 Reserved : 21; // bit 11..31 > > + } Bits; > > + UINT32 Uint32; > > +} CXL_HDM_DECODER_CAPABILITY_REGISTER; > > + > > +typedef union { > > + struct { > > + UINT32 PoisonOnDecodeErrorEnable : 1; // bit 0 > > + UINT32 HdmDecoderEnable : 1; // bit 1 > > + UINT32 Reserved : 30; // bit 2..31 > > + } Bits; > > + UINT32 Uint32; > > +} CXL_HDM_DECODER_GLOBAL_CONTROL_REGISTER; > > + > > +typedef union { > > + struct { > > + UINT32 Reserved : 28; // bit 0..27 > > + UINT32 MemoryBaseLow : 4; // bit 28..31 > > + } Bits; > > + UINT32 Uint32; > > +} CXL_HDM_DECODER_BASE_LOW_REGISTER; > > + > > +typedef union { > > + struct { > > + UINT32 MemoryBaseHigh : 32; // bit 0..31 > > + } Bits; > > + UINT32 Uint32; > > +} CXL_HDM_DECODER_BASE_HIGH_REGISTER; > > + > > +typedef union { > > + struct { > > + UINT32 Reserved : 28; // bit 0..27 > > + UINT32 MemorySizeLow : 4; // bit 28..31 > > + } Bits; > > + UINT32 Uint32; > > +} CXL_HDM_DECODER_SIZE_LOW_REGISTER; > > + > > +typedef union { > > + struct { > > + UINT32 MemorySizeHigh : 32; // bit 0..31 > > + } Bits; > > + UINT32 Uint32; > > +} CXL_HDM_DECODER_SIZE_HIGH_REGISTER; > > + > > +typedef union { > > + struct { > > + UINT32 InterleaveGranularity : 4; // bit 0..3 > > + UINT32 InterleaveWays : 4; // bit 4..7 > > + UINT32 LockOnCommit : 1; // bit 8 > > + UINT32 Commit : 1; // bit 9 > > + UINT32 Committed : 1; // bit 10 > > + UINT32 ErrorNotCommitted : 1; // bit 11 > > + UINT32 TargetDeviceType : 1; // bit 12 > > + UINT32 Reserved : 19; // bit 13..31 > > + } Bits; > > + UINT32 Uint32; > > +} CXL_HDM_DECODER_CONTROL_REGISTER; > > + > > +typedef union { > > + struct { > > + UINT32 TargetPortIdentiferWay0 : 8; // bit 0..7 > > + UINT32 TargetPortIdentiferWay1 : 8; // bit 8..15 > > + UINT32 TargetPortIdentiferWay2 : 8; // bit 16..23 > > + UINT32 TargetPortIdentiferWay3 : 8; // bit 24..31 > > + } Bits; > > + UINT32 Uint32; > > +} CXL_HDM_DECODER_TARGET_LIST_LOW_REGISTER; > > + > > +typedef union { > > + struct { > > + UINT32 Reserved : 28; // bit 0..27 > > + UINT32 DpaSkipLow : 4; // bit 28..31 > > + } Bits; > > + UINT32 Uint32; > > +} CXL_HDM_DECODER_DPA_SKIP_LOW_REGISTER; > > + > > +typedef union { > > + struct { > > + UINT32 TargetPortIdentiferWay4 : 8; // bit 0..7 > > + UINT32 TargetPortIdentiferWay5 : 8; // bit 8..15 > > + UINT32 TargetPortIdentiferWay6 : 8; // bit 16..23 > > + UINT32 TargetPortIdentiferWay7 : 8; // bit 24..31 > > + } Bits; > > + UINT32 Uint32; > > +} CXL_HDM_DECODER_TARGET_LIST_HIGH_REGISTER; > > + > > +typedef union { > > + struct { > > + UINT32 DpaSkipHigh : 32; // bit 0..31 > > + } Bits; > > + UINT32 Uint32; > > +} CXL_HDM_DECODER_DPA_SKIP_HIGH_REGISTER; > > + > > +typedef union { > > + CXL_HDM_DECODER_TARGET_LIST_LOW_REGISTER TargetListLow; > > + CXL_HDM_DECODER_DPA_SKIP_LOW_REGISTER DpaSkipLow; > > +} CXL_HDM_DECODER_TARGET_LIST_OR_DPA_SKIP_LOW; > > + > > +typedef union { > > + CXL_HDM_DECODER_TARGET_LIST_HIGH_REGISTER TargetListHigh; > > + CXL_HDM_DECODER_DPA_SKIP_HIGH_REGISTER DpaSkipHigh; > > +} CXL_HDM_DECODER_TARGET_LIST_OR_DPA_SKIP_HIGH; > > + > > +typedef struct { > > + CXL_HDM_DECODER_BASE_LOW_REGISTER DecoderBaseLow; > > // 0x10 > > + CXL_HDM_DECODER_BASE_HIGH_REGISTER DecoderBaseHigh; > > // 0x14 > > + CXL_HDM_DECODER_SIZE_LOW_REGISTER DecoderSizeLow; > > // 0x18 > > + CXL_HDM_DECODER_SIZE_HIGH_REGISTER DecoderSizeHigh; > > // 0x1c > > + CXL_HDM_DECODER_CONTROL_REGISTER DecoderControl; > > // 0x20 > > + CXL_HDM_DECODER_TARGET_LIST_OR_DPA_SKIP_LOW > > DecoderTargetListDpaSkipLow; // 0x24 > > + CXL_HDM_DECODER_TARGET_LIST_OR_DPA_SKIP_HIGH > > DecoderTargetListDpaSkipHigh; // 0x28 > > + UINT32 Reserved; > > // 0x2C > > +} CXL_HDM_DECODER; > > + > > +// > > +// CXL Device Capabilities Array Register // Compute Express Link > > +Specification Revision 2.0 - Chapter 8.2.8.1 // > > + > > +typedef union { > > + struct { > > + UINT64 CxlDeviceCapabilityId : 16; // bit 0..15 > > + UINT64 CxlDeviceCapabilityVersion : 8; // bit 16..23 > > + UINT64 Reserved1 : 8; // bit 24..31 > > + UINT64 CxlDeviceCapabilitiesCount : 16; // bit 32..47 > > + UINT64 Reserved2 : 16; // bit 48..63 > > + } Bits; > > + UINT64 Uint64; > > +} CXL_DEVICE_CAPABILITIES_ARRAY_REGISTER; > > + > > +// > > +// CXL Memory Status Register > > +// Compute Express Link Specification Revision 2.0 - Chapter 8.2.8.5 > > +// typedef union { > > + struct { > > + UINT64 DeviceFatal : 1; // bit 0 > > + UINT64 FwHalt : 1; // bit 1 > > + UINT64 MediaStatus : 2; // bit 2..3 > > + UINT64 MailboxInterfacesReady : 1; // bit 4 > > + UINT64 ResetNeeded : 3; // bit 5..7 > > + UINT64 Reserved : 56; // bit 8..63 > > + } Bits; > > + UINT64 Uint64; > > +} CXL_MEMORY_DEVICE_STATUS_REGISTER; > > + > > +#pragma pack() > > + > > +#endif > > -- > > 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#107970): https://edk2.groups.io/g/devel/message/107970 Mute This Topic: https://groups.io/mt/100817312/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-