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boundary="_000_SN6PR11MB2768E38BFE9F4860231C5CDAD9E70SN6PR11MB2768namp_" --_000_SN6PR11MB2768E38BFE9F4860231C5CDAD9E70SN6PR11MB2768namp_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Looks like Addresswidth is BIT wise values. Right now these values are not = used any Suggested-by: Star Zeng star.zeng@intel.com Signed-off-by: lorena.r.de.leon.vazquez@intel.com -- .../Feature/VTd/IntelVTdDxe/TranslationTable.c | 11 ++++------- .../Feature/VTd/IntelVTdDxe/TranslationTableEx.c | 11 ++++------- 2 files changed, 8 insertions(+), 14 deletions(-) diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/Translat= ionTable.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/Translat= ionTable.c index cc970c0..61fbb4a 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTabl= e.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTabl= e.c @@ -128,14 +128,11 @@ CreateContextEntry ( DEBUG ((DEBUG_INFO,"Source: S%04x B%02x D%02x F%02x\n", mVtdUnitInform= ation[VtdIndex].Segment, SourceId.Bits.Bus, SourceId.Bits.Device, SourceId.= Bits.Function)); - switch (mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW) { - case BIT1: - ContextEntry->Bits.AddressWidth =3D 0x1; - break; - case BIT2: - ContextEntry->Bits.AddressWidth =3D 0x2; - break; + if ((mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW & BIT2) =3D=3D 0)= { + DEBUG((DEBUG_ERROR, "!!!! 4-level page-table is not supported on VTD= %d !!!!\n", VtdIndex)); + return error; } + ContextEntry->Bits.AddressWidth =3D 0x2; } FlushPageTableMemory (VtdIndex, (UINTN)mVtdUnitInformation[VtdIndex].Roo= tEntryTable, EFI_PAGES_TO_SIZE(EntryTablePages)); diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/Translat= ionTableEx.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/Transl= ationTableEx.c index 0da1611..6bd31b7 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTabl= eEx.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTabl= eEx.c @@ -78,14 +78,11 @@ CreateExtContextEntry ( DEBUG ((DEBUG_INFO,"DOMAIN: S%04x, B%02x D%02x F%02x\n", mVtdUnitInfor= mation[VtdIndex].Segment, SourceId.Bits.Bus, SourceId.Bits.Device, SourceId= .Bits.Function)); - switch (mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW) { - case BIT1: - ExtContextEntry->Bits.AddressWidth =3D 0x1; - break; - case BIT2: - ExtContextEntry->Bits.AddressWidth =3D 0x2; - break; + if ((mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW & BIT2) =3D=3D 0)= { + DEBUG((DEBUG_ERROR, "!!!! 4-level page-table is not supported on VTD= %d !!!!\n", VtdIndex)); + return error; } + ContextEntry->Bits.AddressWidth =3D 0x2; } FlushPageTableMemory (VtdIndex, (UINTN)mVtdUnitInformation[VtdIndex].Ext= RootEntryTable, EFI_PAGES_TO_SIZE(EntryTablePages)); -- 2.21.0.windows.1 --_000_SN6PR11MB2768E38BFE9F4860231C5CDAD9E70SN6PR11MB2768namp_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Looks like Addresswidth is BIT wise values. Right no= w these values are not used any

 

Suggested-by: Star= Zeng star.zeng@intel.com

Signed-off-by: lorena.r.de.leon.vazq= uez@intel.com

 

--

.../Feature/VTd/IntelVTdDxe/TranslationTable.c =        | 11 ++++-------<= /o:p>

.../Feature/VTd/IntelVTdDxe/TranslationTableEx.c&nbs= p;     | 11 ++++-------

2 files changed, 8 insertions(+), 14 deletions(-= )

 

diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/V= Td/IntelVTdDxe/TranslationTable.c b/Silicon/Intel/IntelSiliconPkg/Feature/V= Td/IntelVTdDxe/TranslationTable.c

index cc970c0..61fbb4a 100644

--- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/Inte= lVTdDxe/TranslationTable.c

+++ b/Silicon/Intel/IntelSiliconPkg/Feat= ure/VTd/IntelVTdDxe/TranslationTable.c

@@ -128,14 +128,11 @@ CreateContextEntry (<= /o:p>

     DEBUG ((DEBUG_INFO,&qu= ot;Source: S%04x B%02x D%02x F%02x\n", mVtdUnitInformation[VtdIndex].S= egment, SourceId.Bits.Bus, SourceId.Bits.Device, SourceId.Bits.Function));<= o:p>

-    switch (mVtdUnitInformation[VtdI= ndex].CapReg.Bits.SAGAW) {

-    case BIT1:

-      ContextEntry->Bit= s.AddressWidth =3D 0x1;

-      break;

-    case BIT2:

-      ContextEntry->Bit= s.AddressWidth =3D 0x2;

-      break;

+    if ((mVtdUnitInformation[Vtd= Index].CapReg.Bits.SAGAW & BIT2) =3D=3D 0) {

+      DEBUG((DEBUG_ERR= OR, "!!!! 4-level page-table is not supported on VTD %d !!!!\n", = VtdIndex));

+      return error;

     }

+    ContextEntry->Bits.Addres= sWidth =3D 0x2;

   }

   FlushPageTableMemory (VtdIndex, (U= INTN)mVtdUnitInformation[VtdIndex].RootEntryTable, EFI_PAGES_TO_SIZE(EntryT= ablePages));

diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/V= Td/IntelVTdDxe/TranslationTableEx.c b/Silicon/Intel/IntelSiliconPkg/Feature= /VTd/IntelVTdDxe/TranslationTableEx.c

index 0da1611..6bd31b7 100644

--- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/Inte= lVTdDxe/TranslationTableEx.c

+++ b/Silicon/Intel/IntelSiliconPkg/Feat= ure/VTd/IntelVTdDxe/TranslationTableEx.c

@@ -78,14 +78,11 @@ CreateExtContextEntry (=

     DEBUG ((DEBUG_INFO,&qu= ot;DOMAIN: S%04x, B%02x D%02x F%02x\n", mVtdUnitInformation[VtdIndex].= Segment, SourceId.Bits.Bus, SourceId.Bits.Device, SourceId.Bits.Function));=

-    switch (mVtdUnitInformation[VtdI= ndex].CapReg.Bits.SAGAW) {

-    case BIT1:

-      ExtContextEntry->= Bits.AddressWidth =3D 0x1;

-      break;

-    case BIT2:

-      ExtContextEntry->= Bits.AddressWidth =3D 0x2;

-      break;

+    if ((mVtdUnitInformation[Vtd= Index].CapReg.Bits.SAGAW & BIT2) =3D=3D 0) {

+      DEBUG((DEBUG_ERR= OR, "!!!! 4-level page-table is not supported on VTD %d !!!!\n", = VtdIndex));

+      return error;

     }

+    ContextEntry->Bits.Addres= sWidth =3D 0x2;

   }

   FlushPageTableMemory (VtdIndex, (U= INTN)mVtdUnitInformation[VtdIndex].ExtRootEntryTable, EFI_PAGES_TO_SIZE(Ent= ryTablePages));

--

2.21.0.windows.1

 

--_000_SN6PR11MB2768E38BFE9F4860231C5CDAD9E70SN6PR11MB2768namp_--