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* [edk2-platforms] [PATCH] IntelSiliconPkg: IOMMU generic bug fix
@ 2020-03-02 23:04 lorena.r.de.leon.vazquez
  2020-03-02 23:45 ` Yao, Jiewen
  0 siblings, 1 reply; 9+ messages in thread
From: lorena.r.de.leon.vazquez @ 2020-03-02 23:04 UTC (permalink / raw)
  To: devel@edk2.groups.io; +Cc: Yao, Jiewen, Kinney, Michael D

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Looks like Addresswidth is BIT wise values. Right now these values are not used any

Suggested-by: Star Zeng star.zeng@intel.com<mailto:star.zeng@intel.com>
Signed-off-by: lorena.r.de.leon.vazquez@intel.com<mailto:lorena.r.de.leon.vazquez@intel.com>

--
.../Feature/VTd/IntelVTdDxe/TranslationTable.c        | 11 ++++-------
.../Feature/VTd/IntelVTdDxe/TranslationTableEx.c      | 11 ++++-------
2 files changed, 8 insertions(+), 14 deletions(-)

diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c
index cc970c0..61fbb4a 100644
--- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c
@@ -128,14 +128,11 @@ CreateContextEntry (
     DEBUG ((DEBUG_INFO,"Source: S%04x B%02x D%02x F%02x\n", mVtdUnitInformation[VtdIndex].Segment, SourceId.Bits.Bus, SourceId.Bits.Device, SourceId.Bits.Function));
-    switch (mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW) {
-    case BIT1:
-      ContextEntry->Bits.AddressWidth = 0x1;
-      break;
-    case BIT2:
-      ContextEntry->Bits.AddressWidth = 0x2;
-      break;
+    if ((mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW & BIT2) == 0) {
+      DEBUG((DEBUG_ERROR, "!!!! 4-level page-table is not supported on VTD %d !!!!\n", VtdIndex));
+      return error;
     }
+    ContextEntry->Bits.AddressWidth = 0x2;
   }
   FlushPageTableMemory (VtdIndex, (UINTN)mVtdUnitInformation[VtdIndex].RootEntryTable, EFI_PAGES_TO_SIZE(EntryTablePages));
diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTableEx.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTableEx.c
index 0da1611..6bd31b7 100644
--- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTableEx.c
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTableEx.c
@@ -78,14 +78,11 @@ CreateExtContextEntry (
     DEBUG ((DEBUG_INFO,"DOMAIN: S%04x, B%02x D%02x F%02x\n", mVtdUnitInformation[VtdIndex].Segment, SourceId.Bits.Bus, SourceId.Bits.Device, SourceId.Bits.Function));
-    switch (mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW) {
-    case BIT1:
-      ExtContextEntry->Bits.AddressWidth = 0x1;
-      break;
-    case BIT2:
-      ExtContextEntry->Bits.AddressWidth = 0x2;
-      break;
+    if ((mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW & BIT2) == 0) {
+      DEBUG((DEBUG_ERROR, "!!!! 4-level page-table is not supported on VTD %d !!!!\n", VtdIndex));
+      return error;
     }
+    ContextEntry->Bits.AddressWidth = 0x2;
   }
   FlushPageTableMemory (VtdIndex, (UINTN)mVtdUnitInformation[VtdIndex].ExtRootEntryTable, EFI_PAGES_TO_SIZE(EntryTablePages));
--
2.21.0.windows.1


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^ permalink raw reply related	[flat|nested] 9+ messages in thread
end of thread, other threads:[~2020-08-04 15:16 UTC | newest]

Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2020-03-02 23:04 [edk2-platforms] [PATCH] IntelSiliconPkg: IOMMU generic bug fix lorena.r.de.leon.vazquez
2020-03-02 23:45 ` Yao, Jiewen
2020-07-02 13:55   ` [edk2-devel] " Lohr, Paul A
2020-07-03  1:54     ` Liming Gao
2020-07-06 17:24       ` De Leon Vazquez, Lorena R
2020-07-09 12:44         ` Liming Gao
2020-07-29 15:22           ` De Leon Vasquez, Lorena R
2020-07-31  7:29             ` Liming Gao
2020-08-04 15:15               ` De Leon Vasquez, Lorena R

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