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Thread-Topic: [PATCH v3] IntelFsp2Pkg: Support Multi-Phase SiInit and debug handlers. Thread-Index: AQHWJEQlr56wrWyB50mAohBGe2wEhKicyTjw Date: Thu, 7 May 2020 16:07:07 +0000 Message-ID: References: <20200507074935.11104-1-chasel.chiu@intel.com> In-Reply-To: <20200507074935.11104-1-chasel.chiu@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action authentication-results: intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=none action=none header.from=intel.com; x-originating-ip: [104.153.200.60] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 27462642-b6d3-48bc-08c5-08d7f2a0b14e x-ms-traffictypediagnostic: SN6PR11MB2639: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:10000; x-forefront-prvs: 03965EFC76 x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: GIsnL4tQJskFd6KN9sX3ZoBi45eNbTUnkMZTMJNHr7nCN7NOEu4Lz+R79+SRu214cIPEkEatpYY/5dE1d0KifkVTaBrUiVnWvnDPdRolgdOX/SoZvHqvwKoqneMll4ge4mwFDFjoFuJpwDFpQRg8w0IvPv07syAUeUeNxz13K1NJrgvfJTiMnAdZwIqUsiIPjv9X7nCr14d7/s+Evsp3ZDWL9yeLfIAuWZjsrq80XdIEFb3FFqV2DaZzMwfl1mTZm4iS1eOUcqsjbr1NGG6xK8iQQMbqgpgNcFGUZbZ2VQhKl/+uix16h+vaLQEviznloFHMmIuvbxG4Qmqh7SxIfg0aF+tVBDOadIxWUPt8HbA81tKEe/fN5smmGnsKjNXxeczni0qc2AMk+5p6T7H83E884s74XvKi305CsKNIKrITQ94ZV8kHVG2TS9yqCndlofPUcLCV3GIVVM+cvJ63Pyz6/1lMRQ30I/XYkDH/F+ScgGRmyPOMrAewWKbZYSBvctPbhNpbzpDHku04tMPJD5P/DySV2OgSkTCBcbzU6S5dV83iI47z+wYrRBuFUnzteDq5DHTLIZue8997DtenOUnPAvs3vWVuLUB6FUx/9So= x-forefront-antispam-report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:SN6PR11MB2799.namprd11.prod.outlook.com;PTR:;CAT:NONE;SFTY:;SFS:(6029001)(136003)(396003)(366004)(39860400002)(346002)(376002)(33430700001)(33440700001)(316002)(2906002)(26005)(7696005)(8936002)(53546011)(54906003)(52536014)(66556008)(64756008)(478600001)(66946007)(6506007)(8676002)(110136005)(86362001)(966005)(66476007)(66446008)(5660300002)(76116006)(186003)(83280400001)(83310400001)(83290400001)(30864003)(55016002)(19627235002)(107886003)(4326008)(83320400001)(71200400001)(9686003)(33656002)(83300400001)(579004);DIR:OUT;SFP:1102; x-ms-exchange-antispam-messagedata: S2RYp01ErwLJDMBfa9s8ALTtHRQXw90kUzYXnBOP0wEc3Y/t4LzE0jaLK9GJLY9fe9sDgPPVv0GiqhFvTQuxe5rfPPAr77Mm83ZELvoa5FD1aR5ls35Pzv6Lp2W12KBvtTcMsK6xjJg2wJprCh2VBIp1eZYqzk2CTBbsyO2v37hrEsSUlWoA+R6/3XFYOX1ZIjrQSaWfm2+nD4LhQRreA04XLZS0er/M91Ejq18InMIr/bZ12w7Jn/9FmoYUzwKelVTra74Lc5jKzP7+NYrUhYlb1uPjV6D5gNJjZnune97t6C37nJBeSfSQAoSM2uO6fWa6t2YdGAfczTvP+0YhNpRvC6mKzdfLOHi7xobkjE5MZWO2Gv+3npzt7cDaluq9DH6R4JIoaYe0MdwQNyItDbynmtvdNgy9G1WRv42BOW+CAzGU4y3qy1WSIz83bVNw6de2xVTDQRJouYLPBVf9scm9N20+yI8QQ5MV9SakNmxtOis09Hx3MNduJr9jALZltSf5sDxqUWvrrsNAeYgaXYVL0zquZv1rqYScd8PbvLCcOqlYoqZUJR0zEe5hId+Jd8uz7Y1qbg5zVpOnrbhLcHjdd3HOPu+Krv69S3C7SHh6Swel1nUoSW+WwFmf/FdmPl5oLeIPiiEG+7hPpo2yel+5jJInt+on8O2rlZVWB1NoJxssz8QVf+XA+U0KyzzBMwWif3fQBvI/nx1T5ZENA9SbjcylpGh9AaN5mA772YnHON0vEIc45a2t/W4gRQFTdiOvEvZYzHud3AFMztZoGSBMIPYWAqkCnkNUnOCRk2c= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 27462642-b6d3-48bc-08c5-08d7f2a0b14e X-MS-Exchange-CrossTenant-originalarrivaltime: 07 May 2020 16:07:07.8355 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: CYtoMiAawAzC3+2wsDhOW+9RjtV4PxWkRaX8FujSmA4Dx+A1FFeycBG3azLTjtkZXfhgllq6JmN5AwrPfl7ASg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR11MB2639 Return-Path: maurice.ma@intel.com X-OriginatorOrg: intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Looks good to me. Reviewed-by: Maurice Ma Thanks Maurice > -----Original Message----- > From: Chiu, Chasel > Sent: Thursday, May 7, 2020 0:50 > To: devel@edk2.groups.io > Cc: Ma, Maurice ; Desimone, Nathaniel L > ; Zeng, Star > Subject: [PATCH v3] IntelFsp2Pkg: Support Multi-Phase SiInit and debug > handlers. >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2698 >=20 > To enhance FSP silicon initialization flexibility an optional Multi-Phase= API is > introduced and FSP header needs update for new API offset. Also new SecCo= re > module created for FspMultiPhaseSiInit API >=20 > New ARCH_UPD introduced for enhancing FSP debug message flexibility now > bootloader can pass its own debug handler function pointer and FSP will c= all the > function to handle debug message. >=20 > Cc: Maurice Ma > Cc: Nate DeSimone > Cc: Star Zeng > Signed-off-by: Chasel Chiu > --- > IntelFsp2Pkg/FspSecCore/SecFspApiChk.c | 6= +++--- > IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/PlatformSecLibNull.c | 19 > ++++++++++++++++++- > IntelFsp2Pkg/FspSecCore/FspSecCoreSS.inf | 48 > ++++++++++++++++++++++++++++++++++++++++++++++++ > IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryCommon.nasm | 20 > ++++++++++++++++++-- > IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntrySS.nasm | 58 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > IntelFsp2Pkg/Include/FspEas/FspApi.h | 124 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-- > IntelFsp2Pkg/Include/FspGlobalData.h | 3= ++- > IntelFsp2Pkg/Include/Guid/FspHeaderFile.h | 10= ++++++++-- > IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h | 16 > +++++++++++++++- > 9 files changed, 292 insertions(+), 12 deletions(-) >=20 > diff --git a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c > b/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c > index 8e0595fe9a..1334959005 100644 > --- a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c > +++ b/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c > @@ -1,6 +1,6 @@ > /** @file >=20 > - Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
> + Copyright (c) 2016 - 2020, Intel Corporation. All rights > + reserved.
> SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > **/ > @@ -59,7 +59,7 @@ FspApiCallingCheck ( > Status =3D EFI_UNSUPPORTED; > } > } > - } else if (ApiIdx =3D=3D FspSiliconInitApiIndex) { > + } else if ((ApiIdx =3D=3D FspSiliconInitApiIndex) || (ApiIdx =3D=3D > + FspMultiPhaseSiInitApiIndex)) { > // > // FspSiliconInit check > // > @@ -68,7 +68,7 @@ FspApiCallingCheck ( > } else { > if (FspData->Signature !=3D FSP_GLOBAL_DATA_SIGNATURE) { > Status =3D EFI_UNSUPPORTED; > - } else if (EFI_ERROR (FspUpdSignatureCheck (ApiIdx, ApiParam))) { > + } else if (EFI_ERROR (FspUpdSignatureCheck > + (FspSiliconInitApiIndex, ApiParam))) { > Status =3D EFI_INVALID_PARAMETER; > } > } > diff --git a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/PlatformSecLib= Null.c > b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/PlatformSecLibNull.c > index f7945b5240..df8c5d121f 100644 > --- a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/PlatformSecLibNull.c > +++ b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/PlatformSecLibNull.c > @@ -1,7 +1,7 @@ > /** @file > Null instance of Platform Sec Lib. >=20 > - Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.
> + Copyright (c) 2014 - 2020, Intel Corporation. All rights > + reserved.
> SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > **/ > @@ -25,3 +25,20 @@ FspUpdSignatureCheck ( { > return EFI_SUCCESS; > } > + > +/** > + This function handles FspMultiPhaseSiInitApi. > + > + @param[in] ApiIdx Internal index of the FSP API. > + @param[in] ApiParam Parameter of the FSP API. > + > +**/ > +EFI_STATUS > +EFIAPI > +FspMultiPhaseSiInitApiHandler ( > + IN UINT32 ApiIdx, > + IN VOID *ApiParam > + ) > +{ > + return EFI_SUCCESS; > +} > diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreSS.inf > b/IntelFsp2Pkg/FspSecCore/FspSecCoreSS.inf > new file mode 100644 > index 0000000000..184101c7d3 > --- /dev/null > +++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreSS.inf > @@ -0,0 +1,48 @@ > +## @file > +# Sec Core for FSP to support MultiPhase (SeparatePhase) SiInitializati= on. > +# > +# Copyright (c) 2020, Intel Corporation. All rights reserved.
# # > +SPDX-License-Identifier: BSD-2-Clause-Patent # ## > + > +[Defines] > + INF_VERSION =3D 0x00010005 > + BASE_NAME =3D FspSecCoreSS > + FILE_GUID =3D DF0FCD70-264A-40BF-BBD4-06C76DB19CB= 1 > + MODULE_TYPE =3D SEC > + VERSION_STRING =3D 1.0 > + > +# > +# The following information is for reference only and not required by th= e build > tools. > +# > +# VALID_ARCHITECTURES =3D IA32 > +# > + > +[Sources] > + SecFspApiChk.c > + SecFsp.h > + > +[Sources.IA32] > + Ia32/Stack.nasm > + Ia32/FspApiEntrySS.nasm > + Ia32/FspApiEntryCommon.nasm > + Ia32/FspHelper.nasm > + > +[Binaries.Ia32] > + RAW|Vtf0/Bin/ResetVec.ia32.raw |GCC > + > +[Packages] > + MdePkg/MdePkg.dec > + IntelFsp2Pkg/IntelFsp2Pkg.dec > + > +[LibraryClasses] > + BaseMemoryLib > + DebugLib > + BaseLib > + PciCf8Lib > + SerialPortLib > + FspSwitchStackLib > + FspCommonLib > + FspSecPlatformLib > diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryCommon.nasm > b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryCommon.nasm > index bb4451b145..9b398ee2d0 100644 > --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryCommon.nasm > +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryCommon.nasm > @@ -1,7 +1,7 @@ > ;; @file > ; Provide FSP API entry points. > ; > -; Copyright (c) 2016, Intel Corporation. All rights reserved.
> +; Copyright (c) 2016 - 2020, Intel Corporation. All rights > +reserved.
> ; SPDX-License-Identifier: BSD-2-Clause-Patent ;; >=20 > @@ -12,7 +12,7 @@ > ; > extern ASM_PFX(Loader2PeiSwitchStack) > extern ASM_PFX(FspApiCallingCheck) > - > +extern ASM_PFX(FspMultiPhaseSiInitApiHandler) > ; > ; Following functions will be provided in ASM ; @@ -62,6 +62,22 @@ > FspApiCommon2: > cmp eax, 3 ; FspMemoryInit API > jz FspApiCommon3 >=20 > + cmp eax, 6 ; FspMultiPhaseSiInitApiIndex API > + jnz SwitchStack > + > + ; > + ; Handle FspMultiPhaseSiInitApiIndex API ; pushad > + push DWORD [esp + (4 * 8 + 4)] ; push ApiParam > + push eax ; push ApiIdx > + call ASM_PFX(FspMultiPhaseSiInitApiHandler) > + add esp, 8 > + mov dword [esp + (4 * 7)], eax > + popad > + ret > + > +SwitchStack: > call ASM_PFX(AsmGetFspInfoHeader) > jmp ASM_PFX(Loader2PeiSwitchStack) >=20 > diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntrySS.nasm > b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntrySS.nasm > new file mode 100644 > index 0000000000..768f2db06a > --- /dev/null > +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntrySS.nasm > @@ -0,0 +1,58 @@ > +;; @file > +; Provide FSP API entry points. > +; > +; Copyright (c) 2020, Intel Corporation. All rights reserved.
; > +SPDX-License-Identifier: BSD-2-Clause-Patent ;; > + > + SECTION .text > + > +; > +; Following functions will be provided in C ; extern > +ASM_PFX(FspApiCommon) > + > +;---------------------------------------------------------------------- > +------ > +; FspMultiPhaseSiInitApi API > +; > +; This FSP API provides multi-phase silicon initialization, which > +brings greater ; modularity beyond the existing FspSiliconInit() API. > +; Increased modularity is achieved by adding an extra API to FSP-S. > +; This allows the bootloader to add board specific initialization steps > +throughout ; the SiliconInit flow as needed. > +; > +;---------------------------------------------------------------------- > +------ > +global ASM_PFX(FspMultiPhaseSiInitApi) > +ASM_PFX(FspMultiPhaseSiInitApi): > + mov eax, 6 ; FSP_API_INDEX.FspMultiPhaseSiInitApiIndex > + jmp ASM_PFX(FspApiCommon) > + > +;---------------------------------------------------------------------- > +------ > +; FspApiCommonContinue API > +; > +; This is the FSP API common entry point to resume the FSP execution ; > +;---------------------------------------------------------------------- > +------ > +global ASM_PFX(FspApiCommonContinue) > +ASM_PFX(FspApiCommonContinue): > + jmp $ > + ret > + > +;---------------------------------------------------------------------- > +------ > +; TempRamInit API > +; > +; Empty function for WHOLEARCHIVE build option ; > +;---------------------------------------------------------------------- > +------ > +global ASM_PFX(TempRamInitApi) > +ASM_PFX(TempRamInitApi): > + jmp $ > + ret > + > +;---------------------------------------------------------------------- > +------ > +; Module Entrypoint API > +;---------------------------------------------------------------------- > +------ > +global ASM_PFX(_ModuleEntryPoint) > +ASM_PFX(_ModuleEntryPoint): > + jmp $ > + > diff --git a/IntelFsp2Pkg/Include/FspEas/FspApi.h > b/IntelFsp2Pkg/Include/FspEas/FspApi.h > index dcf489dbe6..ca908b0198 100644 > --- a/IntelFsp2Pkg/Include/FspEas/FspApi.h > +++ b/IntelFsp2Pkg/Include/FspEas/FspApi.h > @@ -2,7 +2,7 @@ > Intel FSP API definition from Intel Firmware Support Package External > Architecture Specification v2.0. >=20 > - Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.
> + Copyright (c) 2014 - 2020, Intel Corporation. All rights > + reserved.
> SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > **/ > @@ -10,6 +10,8 @@ > #ifndef _FSP_API_H_ > #define _FSP_API_H_ >=20 > +#include > + > /// > /// FSP Reset Status code > /// These are defined in FSP EAS v2.0 section 11.2.2 - OEM Status Code @= @ - > 24,6 +26,60 @@ > #define FSP_STATUS_RESET_REQUIRED_8 0x40000008 > /// @} >=20 > +/* > + FSP may optionally include the capability of generating events message= s to > aid in the debugging of firmware issues. > + These events fall under three catagories: Error, Progress, and Debug. > +The event reporting mechanism follows the > + status code services described in section 6 and 7 of the PI Specificat= ion v1.7 > Volume 3. > + > + @param[in] Type Indicates the type of event being re= ported. > + See Section 11.10 Appendix A - Data = Structures for the > definition of EFI_STATUS_CODE_TYPE. > + @param[in] Value Describes the current status of a ha= rdware or > software entity. > + This includes information about the = class and subclass > that is used to classify the entity as well as an operation. > + For progress events, the operation i= s the current activity. > For error events, it is the exception. > + For debug events, it is not defined = at this time. > + See Section 11.10 Appendix A - Data = Structures for the > definition of EFI_STATUS_CODE_VALUE. > + @param[in] Instance The enumeration of a hardware or sof= tware > entity within the system. > + A system may contain multiple entiti= es that match a > class/subclass pairing. The instance differentiates between them. > + An instance of 0 indicates that inst= ance information is > unavailable, not meaningful, or not relevant. > + Valid instance numbers start with 1. > + @param[in] *CallerId This parameter can be used to identi= fy the > sub-module within the FSP generating the event. > + This parameter may be NULL. > + @param[in] *Data This optional parameter may be used = to pass > additional data. The contents can have event-specific data. > + For example, the FSP provides a > EFI_STATUS_CODE_STRING_DATA instance to this parameter when sending > debug messages. > + This parameter is NULL when no addit= ional data is > provided. > + > + @retval EFI_SUCCESS The event was handled successfully. > + @retval EFI_INVALID_PARAMETER Input parameters are invalid. > + @retval EFI_DEVICE_ERROR The event handler failed. > +*/ > +typedef > +EFI_STATUS > +(EFIAPI *FSP_EVENT_HANDLER) ( > + IN EFI_STATUS_CODE_TYPE Type, > + IN EFI_STATUS_CODE_VALUE Value, > + IN UINT32 Instance, > + IN OPTIONAL EFI_GUID *CallerId, > + IN OPTIONAL EFI_STATUS_CODE_DATA *Data > + ); > + > +/* > + Handler for FSP-T debug log messages, provided by the bootloader. > + > + @param[in] DebugMessage A pointer to the debug message to be > written to the log. > + @param[in] MessageLength Number of bytes to written to the de= bug > log. > + > + @retval UINT32 The return value will be passed back= through the > EAX register. > + The return value indicates the numbe= r of bytes actually > written to > + the debug log. If the return value i= s less than > MessageLength, > + an error occurred. > +*/ > +typedef > +UINT32 > +(EFIAPI *FSP_DEBUG_HANDLER) ( > + IN CHAR8* DebugMessage, > + IN UINT32 MessageLength > + ); > + > #pragma pack(1) > /// > /// FSP_UPD_HEADER Configuration. > @@ -77,7 +133,13 @@ typedef struct { > /// Current boot mode. > /// > UINT32 BootMode; > - UINT8 Reserved1[8]; > + /// > + /// A function pointer of type FSP_EVENT_HANDLER. > + /// Optional event handler for the bootloader to be informed of events > occurring during FSP execution. > + /// Refer to Section 8.5 for more details. This value is only valid if= Revision > is >=3D 2. > + /// > + FSP_EVENT_HANDLER *FspEventHandler; > + UINT8 Reserved1[4]; > } FSPM_ARCH_UPD; >=20 > /// > @@ -147,6 +209,40 @@ typedef struct { > FSP_INIT_PHASE Phase; > } NOTIFY_PHASE_PARAMS; >=20 > +/// > +/// Action definition for FspMultiPhaseSiInit API /// typedef enum { > + EnumMultiPhaseGetNumberOfPhases =3D 0x0, > + EnumMultiPhaseExecutePhase =3D 0x1 > +} FSP_MULTI_PHASE_ACTION; > + > +/// > +/// Data structure returned by FSP when bootloader calling /// > +FspMultiPhaseSiInit API with action 0 (EnumMultiPhaseGetNumberOfPhases) > +/// typedef struct { > + UINT32 NumberOfPhases; > + UINT32 PhasesExecuted; > +} FSP_MULTI_PHASE_GET_NUMBER_OF_PHASES_PARAMS; > + > +/// > +/// FspMultiPhaseSiInit function parameter. > +/// > +/// For action 0 (EnumMultiPhaseGetNumberOfPhases): > +/// - PhaseIndex must be 0. > +/// - MultiPhaseParamPtr should point to an instance of > FSP_MULTI_PHASE_GET_NUMBER_OF_PHASES_PARAMS. > +/// > +/// For action 1 (EnumMultiPhaseExecutePhase): > +/// - PhaseIndex will be the phase that will be executed by FSP. > +/// - MultiPhaseParamPtr shall be NULL. > +/// > +typedef struct { > + IN FSP_MULTI_PHASE_ACTION MultiPhaseAction; > + IN UINT32 PhaseIndex; > + IN OUT VOID *MultiPhaseParamPtr; > +} FSP_MULTI_PHASE_PARAMS; > + > #pragma pack() >=20 > /** > @@ -279,4 +375,28 @@ EFI_STATUS > IN VOID *FspsUpdDataPtr > ); >=20 > +/** > + This FSP API is expeted to be called after FspSiliconInit but before > FspNotifyPhase. > + This FSP API provides multi-phase silicon initialization; which > +brings greater modularity > + beyond the existing FspSiliconInit() API. Increased modularity is > +achieved by adding an > + extra API to FSP-S. This allows the bootloader to add board specific > +initialization steps > + throughout the SiliconInit flow as needed. > + > + @param[in,out] FSP_MULTI_PHASE_PARAMS For action - > EnumMultiPhaseGetNumberOfPhases: > + FSP_MULTI_PHASE_PARAMS->Mult= iPhaseParamPtr > will contain > + how many phases supported by= FSP. > + For action - EnumMultiPhaseExe= cutePhase: > + FSP_MULTI_PHASE_PARAMS->Mult= iPhaseParamPtr > shall be NULL. > + @retval EFI_SUCCESS FSP execution environment was = initialized > successfully. > + @retval EFI_INVALID_PARAMETER Input parameters are invalid. > + @retval EFI_UNSUPPORTED The FSP calling conditions wer= e not > met. > + @retval EFI_DEVICE_ERROR FSP initialization failed. > + @retval FSP_STATUS_RESET_REQUIREDx A reset is required. These sta= tus > codes will not be returned during S3. > +**/ > +typedef > +EFI_STATUS > +(EFIAPI *FSP_MULTI_PHASE_SI_INIT) ( > + IN FSP_MULTI_PHASE_PARAMS *MultiPhaseSiInitParamPtr > +); > + > #endif > diff --git a/IntelFsp2Pkg/Include/FspGlobalData.h > b/IntelFsp2Pkg/Include/FspGlobalData.h > index 1896b0240a..02df8463ed 100644 > --- a/IntelFsp2Pkg/Include/FspGlobalData.h > +++ b/IntelFsp2Pkg/Include/FspGlobalData.h > @@ -1,6 +1,6 @@ > /** @file >=20 > - Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
> + Copyright (c) 2014 - 2020, Intel Corporation. All rights > + reserved.
> SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > **/ > @@ -22,6 +22,7 @@ typedef enum { > FspMemoryInitApiIndex, > TempRamExitApiIndex, > FspSiliconInitApiIndex, > + FspMultiPhaseSiInitApiIndex, > FspApiIndexMax > } FSP_API_INDEX; >=20 > diff --git a/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h > b/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h > index 16f43a1273..3474bac1de 100644 > --- a/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h > +++ b/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h > @@ -1,8 +1,8 @@ > /** @file > Intel FSP Header File definition from Intel Firmware Support Package E= xternal > - Architecture Specification v2.0. > + Architecture Specification v2.0 and above. >=20 > - Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
> + Copyright (c) 2014 - 2020, Intel Corporation. All rights > + reserved.
> SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > **/ > @@ -110,6 +110,12 @@ typedef struct { > /// Byte 0x44: The offset for the API to initialize the CPU and chipse= t. > /// > UINT32 FspSiliconInitEntryOffset; > + /// > + /// Byte 0x48: Offset for the API for the optional Multi-Phase process= or and > chipset initialization. > + /// This value is only valid if FSP HeaderRevision is >=3D = 5. > + /// If the value is set to 0x00000000, then this API is not= available in > this component. > + /// > + UINT32 FspMultiPhaseSiInitEntryOffset; > } FSP_INFO_HEADER; >=20 > /// > diff --git a/IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h > b/IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h > index 4d01b5f6d9..51a0309aed 100644 > --- a/IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h > +++ b/IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h > @@ -1,6 +1,6 @@ > /** @file >=20 > - Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
> + Copyright (c) 2015 - 2020, Intel Corporation. All rights > + reserved.
> SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > **/ > @@ -79,4 +79,18 @@ FspUpdSignatureCheck ( > IN VOID *ApiParam > ); >=20 > +/** > + This function handles FspMultiPhaseSiInitApi. > + > + @param[in] ApiIdx Internal index of the FSP API. > + @param[in] ApiParam Parameter of the FSP API. > + > +**/ > +EFI_STATUS > +EFIAPI > +FspMultiPhaseSiInitApiHandler ( > + IN UINT32 ApiIdx, > + IN VOID *ApiParam > + ); > + > #endif > -- > 2.13.3.windows.1