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Thread-Topic: [edk2-devel] [edk2-platforms: PATCH v4] IntelFsp2Pkg: Support Multi-Phase SiInit and debug handlers. Thread-Index: AQHWJNgn/uMhY9lf4EqM5q9J8LuDcKig1qZwgAFmdeCAAAM34A== Date: Mon, 11 May 2020 03:34:42 +0000 Message-ID: References: <20200508012900.8216-1-chasel.chiu@intel.com> <160DDB5B92E20645.21511@groups.io> In-Reply-To: <160DDB5B92E20645.21511@groups.io> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.2.0.6 authentication-results: edk2.groups.io; dkim=none (message not signed) header.d=none;edk2.groups.io; dmarc=none action=none header.from=intel.com; x-originating-ip: [134.134.136.211] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: c41d6798-203b-4bac-b452-08d7f55c3e82 x-ms-traffictypediagnostic: SN6PR11MB3261: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:9508; x-forefront-prvs: 04004D94E2 x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: lGO8EbTcuDbPC1UELPbnAIHAoSHZQeKfs8wvqUOFLu0ZFB3QBXeRN5UYnpnANcSqdrit0oQnG/cJEGHm6IQ/7l2Mvy9qAIjuhytVyj4LIDrOTnFO9eCVAnmsRTMaPsLhSrpADNT6VFsr34joV+pkHIKRHqcpWdT5gYnSUlZKem1yJ7TDrc89hSbRlGty4zUJHrGsxFKVNUlQwMUBXzbs17PDw4z+pLDK37x+pFAcob9LxOhJwi0yaXZc+tcolHlEpV4Cg2mMZW4dyZT/8gv8W9KcfJEcnSSr/CwWjvbtu3e5G6t5lnPJN7o+7vFbRwAl/6kNZ5iuzqYOjwwJN8k4B7TUjNa4X5m6VUIQb1CIn3Pfi1njZbO3TgX7i1bOuXM60SrYH/HIVPQJGrYOtlc6zPRl1fiojb0/HIRVUMlH+iEfM7yC/GArZhtRkmI6pVSMFXL4drhioU4joWGd6idFmCv8giOiBC6WfePV3rqp4jADmmKB+/pXG2fQveY3/8PFL5YoBCtv9fMx7PDxIm6FC8GanE+gm69fnhN8/Bjp1ganKmhz6nVVKLsUPUA18xvEkAfxEjcRrfQ++1alaPMeoILO//4RtiyuKuRyTDhyiG8= x-forefront-antispam-report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:SN6PR11MB2814.namprd11.prod.outlook.com;PTR:;CAT:NONE;SFTY:;SFS:(6029001)(136003)(346002)(376002)(366004)(39860400002)(396003)(33430700001)(8936002)(8676002)(316002)(30864003)(2906002)(6506007)(9686003)(110136005)(53546011)(186003)(19627235002)(6636002)(86362001)(55016002)(76116006)(54906003)(26005)(4326008)(52536014)(71200400001)(66446008)(66476007)(66556008)(66946007)(64756008)(966005)(107886003)(478600001)(5660300002)(7696005)(33440700001)(33656002)(559001)(579004);DIR:OUT;SFP:1102; x-ms-exchange-antispam-messagedata: RLo9g+BQSiA7rLMf3phv7jZqqDZILiznzsF26ODSL8NS2Grz5jpY2WBg1ITuT4KfwEqjxrVk6UDx9WlcyS8ArGmPOXtuEl/hPIF7sFRN6cH70L7U+Gg5oe3/E6XyT92Eb0lvQT14ua5gkaj+a1S3kKLw1taBfmCFFSacZGbRc8o1Ta9zFhaxDHixzCQo8lY5Buv8fk0tu23QfnRjpRftD3lzY/tWqmQ4Iu5k54HMBw3klutlCkc3xRWWkvp9fC4B+lu4DaLTPeOmJXK+Pm6TnzEgZin3MalzSK5swlGK/Imqu2fIfqnPxXV7gIkIgvp01AyesY79kalO/rrDrgjm73pu01f8muv9U9D2QVk3JP7Mcm/zo26Hay/wYrZp+VMKRrd5p0pAoN3sNj72Nj1bCg1TBaMJ6DTnMIBp6HmKPU5rQlG1XpFzXKi7XGwMEelbNOSz22L9piMnnQNwKvOpMq1b922Zam48t3i3QQG7Eaf51QeGlQVN91F1hvXG32SH MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: c41d6798-203b-4bac-b452-08d7f55c3e82 X-MS-Exchange-CrossTenant-originalarrivaltime: 11 May 2020 03:34:42.9434 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: S0/s4LH9BFdBV1tYLDulm9kmNrDaTXGb+lI/yC0A0HibqHxw7IjjC+6EhGoEllpMELhzGCG2B/QJg5V55ckJBQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR11MB3261 Return-Path: chasel.chiu@intel.com X-OriginatorOrg: intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi, Found some comment changes missed in V5, please help to review V6. Thanks, Chasel > -----Original Message----- > From: devel@edk2.groups.io On Behalf Of Chiu, > Chasel > Sent: Monday, May 11, 2020 11:24 AM > To: Desimone, Nathaniel L ; > devel@edk2.groups.io > Cc: Ma, Maurice ; Zeng, Star > Subject: Re: [edk2-devel] [edk2-platforms: PATCH v4] IntelFsp2Pkg: Suppo= rt > Multi-Phase SiInit and debug handlers. >=20 >=20 > Thanks Nate, and sorry that I misunderstood something in previous patch. > I have sent V5 to address all your feedbacks, please help to review agai= n. >=20 > Thanks, > Chasel >=20 >=20 > > -----Original Message----- > > From: Desimone, Nathaniel L > > Sent: Sunday, May 10, 2020 2:22 PM > > To: Chiu, Chasel ; devel@edk2.groups.io > > Cc: Ma, Maurice ; Zeng, Star > > > > Subject: RE: [edk2-platforms: PATCH v4] IntelFsp2Pkg: Support > > Multi-Phase SiInit and debug handlers. > > > > Hi Chasel, > > > > A few comments: > > > > #1) FspApi.h > > > > The references to the FSP/PI spec sections in the comments are a bit o= dd. > > None of the existing comments in FspApi.h make references to sections > > in specs. Particularly weird are these ones: > > > > * See Section 11.10 Appendix A - Data Structures for the definition of > > EFI_STATUS_CODE_TYPE. > > * See Section 11.10 Appendix A - Data Structures for the definition of > > EFI_STATUS_CODE_VALUE. > > > > This is code... why not point the reader to PiStatusCode.h directly? > > > > #2) FspApi.h > > > > This seems overly verbose: > > > > @retval UINT32 The return value will be passed > > back through the EAX register. > > The return value indicates the > > number of bytes actually written to > > the debug log. If the return > value > > is less than MessageLength, > > an error occurred. > > > > I think it can be shortened to: > > > > @retval UINT32 The return value indicates the > > number of bytes actually written to > > the debug log. If the return > value > > is less than MessageLength, > > an error occurred. > > > > #3) Please rename FspSecCoreSS.inf to Fsp22SecCoreS.inf and > > FspApiEntrySS.nasm to Fsp22ApiEntryS.nasm > > > > #4) Any reason why the entry points for FspSiliconInit() and > > NotifyPhase() are absent from FspApiEntrySS.nasm/Fsp22ApiEntry.nasm? > > Are we going to need 2 FspSecCoreS drivers now instead of 1? Not sure > > how that would work... only 1 SecCore is allowed per FV. > > > > Thanks, > > Nate > > > > > -----Original Message----- > > > From: Chiu, Chasel > > > Sent: Thursday, May 7, 2020 6:29 PM > > > To: devel@edk2.groups.io > > > Cc: Ma, Maurice ; Desimone, Nathaniel L > > > ; Zeng, Star > > > Subject: [edk2-platforms: PATCH v4] IntelFsp2Pkg: Support > > > Multi-Phase SiInit and debug handlers. > > > > > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2698 > > > > > > To enhance FSP silicon initialization flexibility an optional > > > Multi-Phase API is introduced and FSP header needs update for new > > > API offset. Also new SecCore module created for FspMultiPhaseSiInit > > > API > > > > > > New ARCH_UPD introduced for enhancing FSP debug message flexibility > > > now bootloader can pass its own debug handler function pointer and > > > FSP will call the function to handle debug message. > > > > > > Cc: Maurice Ma > > > Cc: Nate DeSimone > > > Cc: Star Zeng > > > Signed-off-by: Chasel Chiu > > > --- > > > IntelFsp2Pkg/FspSecCore/SecFspApiChk.c > > | 6 +++--- > > > IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/PlatformSecLibNull.c > > > | > > > 19 > > > ++++++++++++++++++- > > > IntelFsp2Pkg/FspSecCore/FspSecCoreSS.inf > > | 48 > > > ++++++++++++++++++++++++++++++++++++++++++++++++ > > > IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryCommon.nasm > > | 5 > > > ++++- > > > IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntrySS.nasm > > | 68 > > > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > > > ++++++++++ > > > IntelFsp2Pkg/Include/FspEas/FspApi.h > > | 124 > > > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > > > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > > > ++++++-- > > > IntelFsp2Pkg/Include/FspGlobalData.h > > | 3 ++- > > > IntelFsp2Pkg/Include/Guid/FspHeaderFile.h > > | 10 ++++++++-- > > > IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h > | > > 16 > > > +++++++++++++++- > > > 9 files changed, 288 insertions(+), 11 deletions(-) > > > > > > diff --git a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c > > > b/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c > > > index 8e0595fe9a..1334959005 100644 > > > --- a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c > > > +++ b/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c > > > @@ -1,6 +1,6 @@ > > > /** @file > > > > > > - Copyright (c) 2016 - 2018, Intel Corporation. All rights > > > reserved.
> > > + Copyright (c) 2016 - 2020, Intel Corporation. All rights > > > + reserved.
> > > SPDX-License-Identifier: BSD-2-Clause-Patent > > > > > > **/ > > > @@ -59,7 +59,7 @@ FspApiCallingCheck ( > > > Status =3D EFI_UNSUPPORTED; > > > } > > > } > > > - } else if (ApiIdx =3D=3D FspSiliconInitApiIndex) { > > > + } else if ((ApiIdx =3D=3D FspSiliconInitApiIndex) || (ApiIdx =3D= =3D > > > + FspMultiPhaseSiInitApiIndex)) { > > > // > > > // FspSiliconInit check > > > // > > > @@ -68,7 +68,7 @@ FspApiCallingCheck ( > > > } else { > > > if (FspData->Signature !=3D FSP_GLOBAL_DATA_SIGNATURE) { > > > Status =3D EFI_UNSUPPORTED; > > > - } else if (EFI_ERROR (FspUpdSignatureCheck (ApiIdx, ApiParam)= )) > { > > > + } else if (EFI_ERROR (FspUpdSignatureCheck > > > + (FspSiliconInitApiIndex, ApiParam))) { > > > Status =3D EFI_INVALID_PARAMETER; > > > } > > > } > > > diff --git > > > a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/PlatformSecLibNull.c > > > b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/PlatformSecLibNull.c > > > index f7945b5240..df8c5d121f 100644 > > > --- > > > a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/PlatformSecLibNull.c > > > +++ b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/PlatformSecLibNu > > > +++ ll > > > +++ .c > > > @@ -1,7 +1,7 @@ > > > /** @file > > > Null instance of Platform Sec Lib. > > > > > > - Copyright (c) 2014 - 2019, Intel Corporation. All rights > > > reserved.
> > > + Copyright (c) 2014 - 2020, Intel Corporation. All rights > > > + reserved.
> > > SPDX-License-Identifier: BSD-2-Clause-Patent > > > > > > **/ > > > @@ -25,3 +25,20 @@ FspUpdSignatureCheck ( { > > > return EFI_SUCCESS; > > > } > > > + > > > +/** > > > + This function handles FspMultiPhaseSiInitApi. > > > + > > > + @param[in] ApiIdx Internal index of the FSP API. > > > + @param[in] ApiParam Parameter of the FSP API. > > > + > > > +**/ > > > +EFI_STATUS > > > +EFIAPI > > > +FspMultiPhaseSiInitApiHandler ( > > > + IN UINT32 ApiIdx, > > > + IN VOID *ApiParam > > > + ) > > > +{ > > > + return EFI_SUCCESS; > > > +} > > > diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreSS.inf > > > b/IntelFsp2Pkg/FspSecCore/FspSecCoreSS.inf > > > new file mode 100644 > > > index 0000000000..184101c7d3 > > > --- /dev/null > > > +++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreSS.inf > > > @@ -0,0 +1,48 @@ > > > +## @file > > > +# Sec Core for FSP to support MultiPhase (SeparatePhase) > > SiInitialization. > > > +# > > > +# Copyright (c) 2020, Intel Corporation. All rights reserved.
> > > +# # > > > +SPDX-License-Identifier: BSD-2-Clause-Patent # ## > > > + > > > +[Defines] > > > + INF_VERSION =3D 0x00010005 > > > + BASE_NAME =3D FspSecCoreSS > > > + FILE_GUID =3D > > DF0FCD70-264A-40BF-BBD4-06C76DB19CB1 > > > + MODULE_TYPE =3D SEC > > > + VERSION_STRING =3D 1.0 > > > + > > > +# > > > +# The following information is for reference only and not required > > > +by the > > > build tools. > > > +# > > > +# VALID_ARCHITECTURES =3D IA32 > > > +# > > > + > > > +[Sources] > > > + SecFspApiChk.c > > > + SecFsp.h > > > + > > > +[Sources.IA32] > > > + Ia32/Stack.nasm > > > + Ia32/FspApiEntrySS.nasm > > > + Ia32/FspApiEntryCommon.nasm > > > + Ia32/FspHelper.nasm > > > + > > > +[Binaries.Ia32] > > > + RAW|Vtf0/Bin/ResetVec.ia32.raw |GCC > > > + > > > +[Packages] > > > + MdePkg/MdePkg.dec > > > + IntelFsp2Pkg/IntelFsp2Pkg.dec > > > + > > > +[LibraryClasses] > > > + BaseMemoryLib > > > + DebugLib > > > + BaseLib > > > + PciCf8Lib > > > + SerialPortLib > > > + FspSwitchStackLib > > > + FspCommonLib > > > + FspSecPlatformLib > > > diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryCommon.nasm > > > b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryCommon.nasm > > > index bb4451b145..26ae7d9fd3 100644 > > > --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryCommon.nasm > > > +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryCommon.nasm > > > @@ -1,7 +1,7 @@ > > > ;; @file > > > ; Provide FSP API entry points. > > > ; > > > -; Copyright (c) 2016, Intel Corporation. All rights reserved.
> > > +; Copyright (c) 2016 - 2020, Intel Corporation. All rights > > > +reserved.
> > > ; SPDX-License-Identifier: BSD-2-Clause-Patent ;; > > > > > > @@ -62,6 +62,9 @@ FspApiCommon2: > > > cmp eax, 3 ; FspMemoryInit API > > > jz FspApiCommon3 > > > > > > + cmp eax, 6 ; FspMultiPhaseSiInitApiIndex API > > > + jz FspApiCommon3 > > > + > > > call ASM_PFX(AsmGetFspInfoHeader) > > > jmp ASM_PFX(Loader2PeiSwitchStack) > > > > > > diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntrySS.nasm > > > b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntrySS.nasm > > > new file mode 100644 > > > index 0000000000..e6956277a9 > > > --- /dev/null > > > +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntrySS.nasm > > > @@ -0,0 +1,68 @@ > > > +;; @file > > > +; Provide FSP API entry points. > > > +; > > > +; Copyright (c) 2020, Intel Corporation. All rights reserved.
; > > > +SPDX-License-Identifier: BSD-2-Clause-Patent ;; > > > + > > > + SECTION .text > > > + > > > +; > > > +; Following functions will be provided in C ; extern > > > +ASM_PFX(FspApiCommon) extern > > > ASM_PFX(FspMultiPhaseSiInitApiHandler) > > > + > > > +;------------------------------------------------------------------ > > > +-- > > > +-- > > > +------ > > > +; FspMultiPhaseSiInitApi API > > > +; > > > +; This FSP API provides multi-phase silicon initialization, which > > > +brings greater ; modularity beyond the existing FspSiliconInit() AP= I. > > > +; Increased modularity is achieved by adding an extra API to FSP-S. > > > +; This allows the bootloader to add board specific initialization > > > +steps throughout ; the SiliconInit flow as needed. > > > +; > > > +;------------------------------------------------------------------ > > > +-- > > > +-- > > > +------ > > > +global ASM_PFX(FspMultiPhaseSiInitApi) > > > +ASM_PFX(FspMultiPhaseSiInitApi): > > > + mov eax, 6 ; FSP_API_INDEX.FspMultiPhaseSiInitApiIndex > > > + jmp ASM_PFX(FspApiCommon) > > > + > > > +;------------------------------------------------------------------ > > > +-- > > > +-- > > > +------ > > > +; FspApiCommonContinue API > > > +; > > > +; This is the FSP API common entry point to resume the FSP > > > +execution ; > > > +;------------------------------------------------------------------ > > > +-- > > > +-- > > > +------ > > > +global ASM_PFX(FspApiCommonContinue) > > > +ASM_PFX(FspApiCommonContinue): > > > + ; > > > + ; Handle FspMultiPhaseSiInitApiIndex API > > > + ; > > > + pushad > > > + push DWORD [esp + (4 * 8 + 4)] ; push ApiParam > > > + push eax ; push ApiIdx > > > + call ASM_PFX(FspMultiPhaseSiInitApiHandler) > > > + add esp, 8 > > > + mov dword [esp + (4 * 7)], eax > > > + popad > > > + ret > > > + > > > +;------------------------------------------------------------------ > > > +-- > > > +-- > > > +------ > > > +; TempRamInit API > > > +; > > > +; Empty function for WHOLEARCHIVE build option ; > > > +;------------------------------------------------------------------ > > > +-- > > > +-- > > > +------ > > > +global ASM_PFX(TempRamInitApi) > > > +ASM_PFX(TempRamInitApi): > > > + jmp $ > > > + ret > > > + > > > +;------------------------------------------------------------------ > > > +-- > > > +-- > > > +------ > > > +; Module Entrypoint API > > > +;------------------------------------------------------------------ > > > +-- > > > +-- > > > +------ > > > +global ASM_PFX(_ModuleEntryPoint) > > > +ASM_PFX(_ModuleEntryPoint): > > > + jmp $ > > > + > > > diff --git a/IntelFsp2Pkg/Include/FspEas/FspApi.h > > > b/IntelFsp2Pkg/Include/FspEas/FspApi.h > > > index dcf489dbe6..ca908b0198 100644 > > > --- a/IntelFsp2Pkg/Include/FspEas/FspApi.h > > > +++ b/IntelFsp2Pkg/Include/FspEas/FspApi.h > > > @@ -2,7 +2,7 @@ > > > Intel FSP API definition from Intel Firmware Support Package Exte= rnal > > > Architecture Specification v2.0. > > > > > > - Copyright (c) 2014 - 2019, Intel Corporation. All rights > > > reserved.
> > > + Copyright (c) 2014 - 2020, Intel Corporation. All rights > > > + reserved.
> > > SPDX-License-Identifier: BSD-2-Clause-Patent > > > > > > **/ > > > @@ -10,6 +10,8 @@ > > > #ifndef _FSP_API_H_ > > > #define _FSP_API_H_ > > > > > > +#include > > > + > > > /// > > > /// FSP Reset Status code > > > /// These are defined in FSP EAS v2.0 section 11.2.2 - OEM Status > > > Code @@ - > > > 24,6 +26,60 @@ > > > #define FSP_STATUS_RESET_REQUIRED_8 0x40000008 > > > /// @} > > > > > > +/* > > > + FSP may optionally include the capability of generating events > > > +messages to > > > aid in the debugging of firmware issues. > > > + These events fall under three catagories: Error, Progress, and De= bug. > > > +The event reporting mechanism follows the > > > + status code services described in section 6 and 7 of the PI > > > +Specification v1.7 > > > Volume 3. > > > + > > > + @param[in] Type Indicates the type of event > > being reported. > > > + See Section 11.10 Appendix > A > > - > > > + Data Structures for the > > > definition of EFI_STATUS_CODE_TYPE. > > > + @param[in] Value Describes the current status > of > > a hardware or > > > software entity. > > > + This includes information > > about > > > + the class and subclass that > > > is used to classify the entity as well as an operation. > > > + For progress events, the > > operation is the current activity. > > > For error events, it is the exception. > > > + For debug events, it is not > > defined at this time. > > > + See Section 11.10 Appendix > A > > - > > > + Data Structures for the > > > definition of EFI_STATUS_CODE_VALUE. > > > + @param[in] Instance The enumeration of a > hardware > > or software > > > entity within the system. > > > + A system may contain > multiple > > > + entities that match a > > > class/subclass pairing. The instance differentiates between them. > > > + An instance of 0 indicates > that > > > + instance information is > > > unavailable, not meaningful, or not relevant. > > > + Valid instance numbers start > > with 1. > > > + @param[in] *CallerId This parameter can be used to > > identify the > > > sub-module within the FSP generating the event. > > > + This parameter may be > NULL. > > > + @param[in] *Data This optional parameter may > > be used to pass > > > additional data. The contents can have event-specific data. > > > + For example, the FSP > provides > > a > > > EFI_STATUS_CODE_STRING_DATA instance to this parameter when > sending > > > debug messages. > > > + This parameter is NULL > when > > no > > > + additional data is > > > provided. > > > + > > > + @retval EFI_SUCCESS The event was handled > > successfully. > > > + @retval EFI_INVALID_PARAMETER Input parameters are invalid. > > > + @retval EFI_DEVICE_ERROR The event handler failed. > > > +*/ > > > +typedef > > > +EFI_STATUS > > > +(EFIAPI *FSP_EVENT_HANDLER) ( > > > + IN EFI_STATUS_CODE_TYPE Type, > > > + IN EFI_STATUS_CODE_VALUE Value, > > > + IN UINT32 Instance, > > > + IN OPTIONAL EFI_GUID *CallerId, > > > + IN OPTIONAL EFI_STATUS_CODE_DATA *Data > > > + ); > > > + > > > +/* > > > + Handler for FSP-T debug log messages, provided by the bootloader. > > > + > > > + @param[in] DebugMessage A pointer to the debug > > message to be > > > written to the log. > > > + @param[in] MessageLength Number of bytes to written to > > the debug > > > log. > > > + > > > + @retval UINT32 The return value will be > passed > > back through the > > > EAX register. > > > + The return value indicates > the > > > + number of bytes actually > > > written to > > > + the debug log. If the return > > > + value is less than > > > MessageLength, > > > + an error occurred. > > > +*/ > > > +typedef > > > +UINT32 > > > +(EFIAPI *FSP_DEBUG_HANDLER) ( > > > + IN CHAR8* DebugMessage, > > > + IN UINT32 MessageLength > > > + ); > > > + > > > #pragma pack(1) > > > /// > > > /// FSP_UPD_HEADER Configuration. > > > @@ -77,7 +133,13 @@ typedef struct { > > > /// Current boot mode. > > > /// > > > UINT32 BootMode; > > > - UINT8 Reserved1[8]; > > > + /// > > > + /// A function pointer of type FSP_EVENT_HANDLER. > > > + /// Optional event handler for the bootloader to be informed of > > > + events > > > occurring during FSP execution. > > > + /// Refer to Section 8.5 for more details. This value is only > > > + valid if Revision is > > > >=3D 2. > > > + /// > > > + FSP_EVENT_HANDLER *FspEventHandler; > > > + UINT8 Reserved1[4]; > > > } FSPM_ARCH_UPD; > > > > > > /// > > > @@ -147,6 +209,40 @@ typedef struct { > > > FSP_INIT_PHASE Phase; > > > } NOTIFY_PHASE_PARAMS; > > > > > > +/// > > > +/// Action definition for FspMultiPhaseSiInit API /// typedef enum > > > +{ > > > + EnumMultiPhaseGetNumberOfPhases =3D 0x0, > > > + EnumMultiPhaseExecutePhase =3D 0x1 > > > +} FSP_MULTI_PHASE_ACTION; > > > + > > > +/// > > > +/// Data structure returned by FSP when bootloader calling /// > > > +FspMultiPhaseSiInit API with action 0 > > > (EnumMultiPhaseGetNumberOfPhases) > > > +/// typedef struct { > > > + UINT32 NumberOfPhases; > > > + UINT32 PhasesExecuted; > > > +} FSP_MULTI_PHASE_GET_NUMBER_OF_PHASES_PARAMS; > > > + > > > +/// > > > +/// FspMultiPhaseSiInit function parameter. > > > +/// > > > +/// For action 0 (EnumMultiPhaseGetNumberOfPhases): > > > +/// - PhaseIndex must be 0. > > > +/// - MultiPhaseParamPtr should point to an instance of > > > FSP_MULTI_PHASE_GET_NUMBER_OF_PHASES_PARAMS. > > > +/// > > > +/// For action 1 (EnumMultiPhaseExecutePhase): > > > +/// - PhaseIndex will be the phase that will be executed by FSP. > > > +/// - MultiPhaseParamPtr shall be NULL. > > > +/// > > > +typedef struct { > > > + IN FSP_MULTI_PHASE_ACTION MultiPhaseAction; > > > + IN UINT32 PhaseIndex; > > > + IN OUT VOID *MultiPhaseParamPtr; > > > +} FSP_MULTI_PHASE_PARAMS; > > > + > > > #pragma pack() > > > > > > /** > > > @@ -279,4 +375,28 @@ EFI_STATUS > > > IN VOID *FspsUpdDataPtr > > > ); > > > > > > +/** > > > + This FSP API is expeted to be called after FspSiliconInit but > > > +before > > > FspNotifyPhase. > > > + This FSP API provides multi-phase silicon initialization; which > > > +brings greater modularity > > > + beyond the existing FspSiliconInit() API. Increased modularity is > > > +achieved by adding an > > > + extra API to FSP-S. This allows the bootloader to add board > > > +specific initialization steps > > > + throughout the SiliconInit flow as needed. > > > + > > > + @param[in,out] FSP_MULTI_PHASE_PARAMS For action - > > > EnumMultiPhaseGetNumberOfPhases: > > > + > > > + FSP_MULTI_PHASE_PARAMS->MultiPhaseParamPtr > > > will contain > > > + how many phases > > supported by FSP. > > > + For action - > > EnumMultiPhaseExecutePhase: > > > + > > > + FSP_MULTI_PHASE_PARAMS->MultiPhaseParamPtr > > > shall be NULL. > > > + @retval EFI_SUCCESS FSP execution > > environment was initialized > > > successfully. > > > + @retval EFI_INVALID_PARAMETER Input parameters are > > invalid. > > > + @retval EFI_UNSUPPORTED The FSP calling > > conditions were not > > > met. > > > + @retval EFI_DEVICE_ERROR FSP initialization > failed. > > > + @retval FSP_STATUS_RESET_REQUIREDx A reset is required. > > These > > > status codes will not be returned during S3. > > > +**/ > > > +typedef > > > +EFI_STATUS > > > +(EFIAPI *FSP_MULTI_PHASE_SI_INIT) ( > > > + IN FSP_MULTI_PHASE_PARAMS *MultiPhaseSiInitParamPtr > > > +); > > > + > > > #endif > > > diff --git a/IntelFsp2Pkg/Include/FspGlobalData.h > > > b/IntelFsp2Pkg/Include/FspGlobalData.h > > > index 1896b0240a..02df8463ed 100644 > > > --- a/IntelFsp2Pkg/Include/FspGlobalData.h > > > +++ b/IntelFsp2Pkg/Include/FspGlobalData.h > > > @@ -1,6 +1,6 @@ > > > /** @file > > > > > > - Copyright (c) 2014 - 2018, Intel Corporation. All rights > > > reserved.
> > > + Copyright (c) 2014 - 2020, Intel Corporation. All rights > > > + reserved.
> > > SPDX-License-Identifier: BSD-2-Clause-Patent > > > > > > **/ > > > @@ -22,6 +22,7 @@ typedef enum { > > > FspMemoryInitApiIndex, > > > TempRamExitApiIndex, > > > FspSiliconInitApiIndex, > > > + FspMultiPhaseSiInitApiIndex, > > > FspApiIndexMax > > > } FSP_API_INDEX; > > > > > > diff --git a/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h > > > b/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h > > > index 16f43a1273..3474bac1de 100644 > > > --- a/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h > > > +++ b/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h > > > @@ -1,8 +1,8 @@ > > > /** @file > > > Intel FSP Header File definition from Intel Firmware Support > > > Package External > > > - Architecture Specification v2.0. > > > + Architecture Specification v2.0 and above. > > > > > > - Copyright (c) 2014 - 2018, Intel Corporation. All rights > > > reserved.
> > > + Copyright (c) 2014 - 2020, Intel Corporation. All rights > > > + reserved.
> > > SPDX-License-Identifier: BSD-2-Clause-Patent > > > > > > **/ > > > @@ -110,6 +110,12 @@ typedef struct { > > > /// Byte 0x44: The offset for the API to initialize the CPU and c= hipset. > > > /// > > > UINT32 FspSiliconInitEntryOffset; > > > + /// > > > + /// Byte 0x48: Offset for the API for the optional Multi-Phase > > > + processor > > > and chipset initialization. > > > + /// This value is only valid if FSP HeaderRevision is = >=3D 5. > > > + /// If the value is set to 0x00000000, then this API i= s > not > > available in > > > this component. > > > + /// > > > + UINT32 FspMultiPhaseSiInitEntryOffset; > > > } FSP_INFO_HEADER; > > > > > > /// > > > diff --git a/IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h > > > b/IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h > > > index 4d01b5f6d9..51a0309aed 100644 > > > --- a/IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h > > > +++ b/IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h > > > @@ -1,6 +1,6 @@ > > > /** @file > > > > > > - Copyright (c) 2015 - 2019, Intel Corporation. All rights > > > reserved.
> > > + Copyright (c) 2015 - 2020, Intel Corporation. All rights > > > + reserved.
> > > SPDX-License-Identifier: BSD-2-Clause-Patent > > > > > > **/ > > > @@ -79,4 +79,18 @@ FspUpdSignatureCheck ( > > > IN VOID *ApiParam > > > ); > > > > > > +/** > > > + This function handles FspMultiPhaseSiInitApi. > > > + > > > + @param[in] ApiIdx Internal index of the FSP API. > > > + @param[in] ApiParam Parameter of the FSP API. > > > + > > > +**/ > > > +EFI_STATUS > > > +EFIAPI > > > +FspMultiPhaseSiInitApiHandler ( > > > + IN UINT32 ApiIdx, > > > + IN VOID *ApiParam > > > + ); > > > + > > > #endif > > > -- > > > 2.13.3.windows.1 >=20 >=20 >=20