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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Chasel Chiu > -----Original Message----- > From: Lou, Yun > Sent: Sunday, April 25, 2021 10:42 PM > To: devel@edk2.groups.io > Cc: Lou, Yun ; Chiu, Chasel ; > Desimone, Nathaniel L ; Zeng, Star > ; Ni, Ray > Subject: [PATCH v1] Intel/WhiskeylakeOpenBoardPkg: Simplify microcode > related PCD usage >=20 > From: Jason Lou >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3334 >=20 > There are following PCDs in IntelFsp2WrapperPkg for microcode location: >=20 > * IntelFsp2WrapperPkg: > PcdCpuMicrocodePatchAddress > PcdCpuMicrocodePatchRegionSize > PcdFlashMicrocodeOffset >=20 > The change simplify the platform code to use following PCDs instead: > * MinPlatformPkg > PcdFlashFvMicrocodeOffset > PcdFlashFvMicrocodeBase =3D $(BIOS_BASE) + PcdFlashFvMicrocodeOffset > PcdFlashFvMicrocodeSize > PcdMicrocodeOffsetInFv >=20 > Signed-off-by: Jason Lou > Cc: Chasel Chiu > Cc: Nate DeSimone > Cc: Star Zeng > Cc: Ray Ni > --- >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecF > spWrapperPlatformSecLib/SecRamInitData.c | 6 +++--- >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecF > spWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf | 8 ++++---- > Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.fdf > | 6 ++---- >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.fd > f | 6 ++---- > 4 files changed, 11 insertions(+), 15 deletions(-) >=20 > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/Se > cFspWrapperPlatformSecLib/SecRamInitData.c > b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/Se > cFspWrapperPlatformSecLib/SecRamInitData.c > index 8442e5fbff..41a37f5da5 100644 > --- > a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/Se > cFspWrapperPlatformSecLib/SecRamInitData.c > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/Se > cFspWrapperPlatformSecLib/SecRamInitData.c > @@ -1,7 +1,7 @@ > /** @file >=20 > Provide TempRamInitParams data. >=20 >=20 >=20 > -Copyright (c) 2020, Intel Corporation. All rights reserved.
>=20 > +Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.
>=20 > SPDX-License-Identifier: BSD-2-Clause-Patent >=20 >=20 >=20 > **/ >=20 > @@ -24,8 +24,8 @@ GLOBAL_REMOVE_IF_UNREFERENCED CONST FSPT_UPD > FsptUpdDataPtr =3D { > }, >=20 > // FSPT_CORE_UPD >=20 > { >=20 > - ((UINT32) FixedPcdGet64 (PcdCpuMicrocodePatchAddress) + FixedPcdGet3= 2 > (PcdFlashMicrocodeOffset)), >=20 > - ((UINT32) FixedPcdGet64 (PcdCpuMicrocodePatchRegionSize) - > FixedPcdGet32 (PcdFlashMicrocodeOffset)), >=20 > + FixedPcdGet32 (PcdFlashFvMicrocodeBase) + FixedPcdGet32 > (PcdMicrocodeOffsetInFv), >=20 > + FixedPcdGet32 (PcdFlashFvMicrocodeSize) - FixedPcdGet32 > (PcdMicrocodeOffsetInFv), >=20 > 0, // Set CodeRegionBase as 0, so that caching will be 4GB- > (CodeRegionSize > LLCSize ? LLCSize : CodeRegionSize) will be used. >=20 > FixedPcdGet32 (PcdFlashCodeCacheSize), >=20 > { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, >=20 > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/Se > cFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf > b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/Se > cFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf > index b17226d43b..e7319cf9e7 100644 > --- > a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/Se > cFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/Se > cFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf > @@ -1,7 +1,7 @@ > ## @file >=20 > # Provide FSP wrapper platform sec related function. >=20 > # >=20 > -# Copyright (c) 2020, Intel Corporation. All rights reserved.
>=20 > +# Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved. >=20 > # >=20 > # SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > # >=20 > @@ -92,9 +92,9 @@ > [FixedPcd] >=20 > gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## > CONSUMES >=20 > gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate ## > CONSUMES >=20 > - gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress ## > CONSUMES >=20 > - gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize ## > CONSUMES >=20 > - gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset ## > CONSUMES >=20 > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase ## > CONSUMES >=20 > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize ## > CONSUMES >=20 > + gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv ## > CONSUMES >=20 > gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress ## > CONSUMES >=20 > gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize ## > CONSUMES >=20 > gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress ## > CONSUMES >=20 > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.fdf > b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.fdf > index 0d99114961..22fbfc99f0 100644 > --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.fdf > +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.fdf > @@ -2,7 +2,7 @@ > # FDF file for the UpXtreme. >=20 > # >=20 > # >=20 > -# Copyright (c) 2020, Intel Corporation. All rights reserved.
>=20 > +# Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved. >=20 > # >=20 > # SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > # >=20 > @@ -47,9 +47,7 @@ SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =3D > $(gSiPkgTokenSpaceGuid.PcdBio > SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D > $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) >=20 > SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D > $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60 >=20 > SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D > $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60 >=20 > -SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D > $(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + > $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset) >=20 > -SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D > $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) >=20 > -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset =3D 0x60 >=20 > +SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv =3D 0x60 >=20 > SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =3D > gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase >=20 > SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =3D > gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize >=20 > SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =3D > gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset >=20 > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg. > fdf > b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg. > fdf > index ad32268a82..1ab8c13792 100644 > --- > a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg. > fdf > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg. > fdf > @@ -2,7 +2,7 @@ > # FDF file of Platform. >=20 > # >=20 > # >=20 > -# Copyright (c) 2019, Intel Corporation. All rights reserved.
>=20 > +# Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved. >=20 > # >=20 > # SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > # >=20 > @@ -47,9 +47,7 @@ SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =3D > $(gSiPkgTokenSpaceGuid.PcdBio > SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D > $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) >=20 > SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D > $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60 >=20 > SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D > $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60 >=20 > -SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D > $(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + > $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset) >=20 > -SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D > $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) >=20 > -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset =3D 0x60 >=20 > +SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv =3D 0x60 >=20 > SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =3D > gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase >=20 > SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =3D > gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize >=20 > SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =3D > gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset >=20 > -- > 2.28.0.windows.1