* [PATCH v1] Intel/CometlakeOpenBoardPkg: Simplify microcode related PCD usage
@ 2021-04-25 14:41 Jason Lou
2021-04-25 14:41 ` [PATCH v1] Intel/KabylakeOpenBoardPkg: " Jason Lou
` (3 more replies)
0 siblings, 4 replies; 9+ messages in thread
From: Jason Lou @ 2021-04-25 14:41 UTC (permalink / raw)
To: devel; +Cc: Jason Lou, Chasel Chiu, Nate DeSimone, Star Zeng, Ray Ni
From: Jason Lou <yun.lou@intel.com>
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3334
There are following PCDs in IntelFsp2WrapperPkg for microcode location:
* IntelFsp2WrapperPkg:
PcdCpuMicrocodePatchAddress
PcdCpuMicrocodePatchRegionSize
PcdFlashMicrocodeOffset
The change simplify the platform code to use following PCDs instead:
* MinPlatformPkg
PcdFlashFvMicrocodeOffset
PcdFlashFvMicrocodeBase = $(BIOS_BASE) + PcdFlashFvMicrocodeOffset
PcdFlashFvMicrocodeSize
PcdMicrocodeOffsetInFv <NEW>
Signed-off-by: Jason Lou <yun.lou@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
---
Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.fdf | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.fdf b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.fdf
index 31f4d22311..795cc0da75 100644
--- a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.fdf
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.fdf
@@ -2,7 +2,7 @@
# FDF file of Platform.
#
#
-# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -47,9 +47,7 @@ SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase = $(gSiPkgTokenSpaceGuid.PcdBio
SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize)
SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60
SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60
-SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress = $(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset)
-SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize)
-SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset = 0x60
+SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv = 0x60
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset
--
2.28.0.windows.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v1] Intel/KabylakeOpenBoardPkg: Simplify microcode related PCD usage
2021-04-25 14:41 [PATCH v1] Intel/CometlakeOpenBoardPkg: Simplify microcode related PCD usage Jason Lou
@ 2021-04-25 14:41 ` Jason Lou
2021-04-26 0:42 ` Chiu, Chasel
2021-04-25 14:41 ` [PATCH v1] Intel/TigerlakeOpenBoardPkg: " Jason Lou
` (2 subsequent siblings)
3 siblings, 1 reply; 9+ messages in thread
From: Jason Lou @ 2021-04-25 14:41 UTC (permalink / raw)
To: devel; +Cc: Jason Lou, Chasel Chiu, Nate DeSimone, Star Zeng, Ray Ni
From: Jason Lou <yun.lou@intel.com>
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3334
There are following PCDs in IntelFsp2WrapperPkg for microcode location:
* IntelFsp2WrapperPkg:
PcdCpuMicrocodePatchAddress
PcdCpuMicrocodePatchRegionSize
PcdFlashMicrocodeOffset
The change simplify the platform code to use following PCDs instead:
* MinPlatformPkg
PcdFlashFvMicrocodeOffset
PcdFlashFvMicrocodeBase = $(BIOS_BASE) + PcdFlashFvMicrocodeOffset
PcdFlashFvMicrocodeSize
PcdMicrocodeOffsetInFv <NEW>
Signed-off-by: Jason Lou <yun.lou@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
---
Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf | 6 ++----
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf | 6 ++----
2 files changed, 4 insertions(+), 8 deletions(-)
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf
index 196f04c68d..bcd1ade72b 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf
+++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf
@@ -1,7 +1,7 @@
## @file
# System 76 GalagoPro3 board flash file.
#
-# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -45,9 +45,7 @@ SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase = $(gSiPkgTokenSpaceGuid.PcdFla
SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize)
SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60
SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60
-SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress = $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset)
-SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize)
-SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset = 0x60
+SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv = 0x60
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf
index f2cfff1c7b..6cdf4e2f9f 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf
@@ -1,7 +1,7 @@
## @file
# FDF file of Platform.
#
-# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -45,9 +45,7 @@ SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase = $(gSiPkgTokenSpaceGuid.PcdFla
SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize)
SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60
SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60
-SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress = $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset)
-SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize)
-SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset = 0x60
+SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv = 0x60
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset
--
2.28.0.windows.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v1] Intel/TigerlakeOpenBoardPkg: Simplify microcode related PCD usage
2021-04-25 14:41 [PATCH v1] Intel/CometlakeOpenBoardPkg: Simplify microcode related PCD usage Jason Lou
2021-04-25 14:41 ` [PATCH v1] Intel/KabylakeOpenBoardPkg: " Jason Lou
@ 2021-04-25 14:41 ` Jason Lou
2021-04-26 0:42 ` Chiu, Chasel
2021-04-25 14:41 ` [PATCH v1] Intel/WhiskeylakeOpenBoardPkg: " Jason Lou
2021-04-26 0:42 ` [PATCH v1] Intel/CometlakeOpenBoardPkg: " Chiu, Chasel
3 siblings, 1 reply; 9+ messages in thread
From: Jason Lou @ 2021-04-25 14:41 UTC (permalink / raw)
To: devel; +Cc: Jason Lou, Chasel Chiu, Nate DeSimone, Star Zeng, Ray Ni
From: Jason Lou <yun.lou@intel.com>
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3334
There are following PCDs in IntelFsp2WrapperPkg for microcode location:
* IntelFsp2WrapperPkg:
PcdCpuMicrocodePatchAddress
PcdCpuMicrocodePatchRegionSize
PcdFlashMicrocodeOffset
The change simplify the platform code to use following PCDs instead:
* MinPlatformPkg
PcdFlashFvMicrocodeOffset
PcdFlashFvMicrocodeBase = $(BIOS_BASE) + PcdFlashFvMicrocodeOffset
PcdFlashFvMicrocodeSize
PcdMicrocodeOffsetInFv <NEW>
Signed-off-by: Jason Lou <yun.lou@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
---
Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.fdf | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.fdf b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.fdf
index 0f645ed63e..c1fd2be6af 100644
--- a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.fdf
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.fdf
@@ -47,14 +47,12 @@ SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase = $(gSiPkgTokenSpaceGuid.PcdBio
SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize)
SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeOffset)
SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) - $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeOffset)
-SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress = $(gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress)
-SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = $(gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize)
-SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeOffset)
SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress = gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress
SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize = gSiPkgTokenSpaceGuid.PcdBiosSize
SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress = $(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset)
SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress = $(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset)
SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress = $(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset)
+SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeOffset
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset
--
2.28.0.windows.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v1] Intel/WhiskeylakeOpenBoardPkg: Simplify microcode related PCD usage
2021-04-25 14:41 [PATCH v1] Intel/CometlakeOpenBoardPkg: Simplify microcode related PCD usage Jason Lou
2021-04-25 14:41 ` [PATCH v1] Intel/KabylakeOpenBoardPkg: " Jason Lou
2021-04-25 14:41 ` [PATCH v1] Intel/TigerlakeOpenBoardPkg: " Jason Lou
@ 2021-04-25 14:41 ` Jason Lou
2021-04-26 0:42 ` Chiu, Chasel
2021-04-26 0:42 ` [PATCH v1] Intel/CometlakeOpenBoardPkg: " Chiu, Chasel
3 siblings, 1 reply; 9+ messages in thread
From: Jason Lou @ 2021-04-25 14:41 UTC (permalink / raw)
To: devel; +Cc: Jason Lou, Chasel Chiu, Nate DeSimone, Star Zeng, Ray Ni
From: Jason Lou <yun.lou@intel.com>
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3334
There are following PCDs in IntelFsp2WrapperPkg for microcode location:
* IntelFsp2WrapperPkg:
PcdCpuMicrocodePatchAddress
PcdCpuMicrocodePatchRegionSize
PcdFlashMicrocodeOffset
The change simplify the platform code to use following PCDs instead:
* MinPlatformPkg
PcdFlashFvMicrocodeOffset
PcdFlashFvMicrocodeBase = $(BIOS_BASE) + PcdFlashFvMicrocodeOffset
PcdFlashFvMicrocodeSize
PcdMicrocodeOffsetInFv <NEW>
Signed-off-by: Jason Lou <yun.lou@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
---
Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecRamInitData.c | 6 +++---
Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf | 8 ++++----
Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.fdf | 6 ++----
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.fdf | 6 ++----
4 files changed, 11 insertions(+), 15 deletions(-)
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecRamInitData.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecRamInitData.c
index 8442e5fbff..41a37f5da5 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecRamInitData.c
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecRamInitData.c
@@ -1,7 +1,7 @@
/** @file
Provide TempRamInitParams data.
-Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -24,8 +24,8 @@ GLOBAL_REMOVE_IF_UNREFERENCED CONST FSPT_UPD FsptUpdDataPtr = {
},
// FSPT_CORE_UPD
{
- ((UINT32) FixedPcdGet64 (PcdCpuMicrocodePatchAddress) + FixedPcdGet32 (PcdFlashMicrocodeOffset)),
- ((UINT32) FixedPcdGet64 (PcdCpuMicrocodePatchRegionSize) - FixedPcdGet32 (PcdFlashMicrocodeOffset)),
+ FixedPcdGet32 (PcdFlashFvMicrocodeBase) + FixedPcdGet32 (PcdMicrocodeOffsetInFv),
+ FixedPcdGet32 (PcdFlashFvMicrocodeSize) - FixedPcdGet32 (PcdMicrocodeOffsetInFv),
0, // Set CodeRegionBase as 0, so that caching will be 4GB-(CodeRegionSize > LLCSize ? LLCSize : CodeRegionSize) will be used.
FixedPcdGet32 (PcdFlashCodeCacheSize),
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
index b17226d43b..e7319cf9e7 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
@@ -1,7 +1,7 @@
## @file
# Provide FSP wrapper platform sec related function.
#
-# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -92,9 +92,9 @@
[FixedPcd]
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate ## CONSUMES
- gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress ## CONSUMES
- gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize ## CONSUMES
- gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv ## CONSUMES
gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress ## CONSUMES
gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize ## CONSUMES
gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress ## CONSUMES
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.fdf b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.fdf
index 0d99114961..22fbfc99f0 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.fdf
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.fdf
@@ -2,7 +2,7 @@
# FDF file for the UpXtreme.
#
#
-# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -47,9 +47,7 @@ SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase = $(gSiPkgTokenSpaceGuid.PcdBio
SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize)
SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60
SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60
-SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress = $(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset)
-SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize)
-SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset = 0x60
+SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv = 0x60
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.fdf b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.fdf
index ad32268a82..1ab8c13792 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.fdf
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.fdf
@@ -2,7 +2,7 @@
# FDF file of Platform.
#
#
-# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -47,9 +47,7 @@ SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase = $(gSiPkgTokenSpaceGuid.PcdBio
SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize)
SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60
SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60
-SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress = $(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset)
-SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize)
-SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset = 0x60
+SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv = 0x60
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset
--
2.28.0.windows.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v1] Intel/CometlakeOpenBoardPkg: Simplify microcode related PCD usage
2021-04-25 14:41 [PATCH v1] Intel/CometlakeOpenBoardPkg: Simplify microcode related PCD usage Jason Lou
` (2 preceding siblings ...)
2021-04-25 14:41 ` [PATCH v1] Intel/WhiskeylakeOpenBoardPkg: " Jason Lou
@ 2021-04-26 0:42 ` Chiu, Chasel
3 siblings, 0 replies; 9+ messages in thread
From: Chiu, Chasel @ 2021-04-26 0:42 UTC (permalink / raw)
To: Lou, Yun, devel@edk2.groups.io; +Cc: Desimone, Nathaniel L, Zeng, Star, Ni, Ray
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
> -----Original Message-----
> From: Lou, Yun <yun.lou@intel.com>
> Sent: Sunday, April 25, 2021 10:42 PM
> To: devel@edk2.groups.io
> Cc: Lou, Yun <yun.lou@intel.com>; Chiu, Chasel <chasel.chiu@intel.com>;
> Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Zeng, Star
> <star.zeng@intel.com>; Ni, Ray <ray.ni@intel.com>
> Subject: [PATCH v1] Intel/CometlakeOpenBoardPkg: Simplify microcode related
> PCD usage
>
> From: Jason Lou <yun.lou@intel.com>
>
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3334
>
> There are following PCDs in IntelFsp2WrapperPkg for microcode location:
>
> * IntelFsp2WrapperPkg:
> PcdCpuMicrocodePatchAddress
> PcdCpuMicrocodePatchRegionSize
> PcdFlashMicrocodeOffset
>
> The change simplify the platform code to use following PCDs instead:
> * MinPlatformPkg
> PcdFlashFvMicrocodeOffset
> PcdFlashFvMicrocodeBase = $(BIOS_BASE) + PcdFlashFvMicrocodeOffset
> PcdFlashFvMicrocodeSize
> PcdMicrocodeOffsetInFv <NEW>
>
> Signed-off-by: Jason Lou <yun.lou@intel.com>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> Cc: Star Zeng <star.zeng@intel.com>
> Cc: Ray Ni <ray.ni@intel.com>
> ---
> Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.fdf |
> 6 ++----
> 1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git
> a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.fdf
> b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.fdf
> index 31f4d22311..795cc0da75 100644
> ---
> a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.fdf
> +++
> b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.fdf
> @@ -2,7 +2,7 @@
> # FDF file of Platform.
>
> #
>
> #
>
> -# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
>
> +# Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.<BR>
>
> #
>
> # SPDX-License-Identifier: BSD-2-Clause-Patent
>
> #
>
> @@ -47,9 +47,7 @@ SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =
> $(gSiPkgTokenSpaceGuid.PcdBio
> SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =
> $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize)
>
> SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =
> $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60
>
> SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =
> $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60
>
> -SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress =
> $(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) +
> $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset)
>
> -SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =
> $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize)
>
> -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset = 0x60
>
> +SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv = 0x60
>
> SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =
> gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase
>
> SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =
> gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
>
> SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =
> gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset
>
> --
> 2.28.0.windows.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v1] Intel/KabylakeOpenBoardPkg: Simplify microcode related PCD usage
2021-04-25 14:41 ` [PATCH v1] Intel/KabylakeOpenBoardPkg: " Jason Lou
@ 2021-04-26 0:42 ` Chiu, Chasel
0 siblings, 0 replies; 9+ messages in thread
From: Chiu, Chasel @ 2021-04-26 0:42 UTC (permalink / raw)
To: Lou, Yun, devel@edk2.groups.io; +Cc: Desimone, Nathaniel L, Zeng, Star, Ni, Ray
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
> -----Original Message-----
> From: Lou, Yun <yun.lou@intel.com>
> Sent: Sunday, April 25, 2021 10:42 PM
> To: devel@edk2.groups.io
> Cc: Lou, Yun <yun.lou@intel.com>; Chiu, Chasel <chasel.chiu@intel.com>;
> Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Zeng, Star
> <star.zeng@intel.com>; Ni, Ray <ray.ni@intel.com>
> Subject: [PATCH v1] Intel/KabylakeOpenBoardPkg: Simplify microcode related
> PCD usage
>
> From: Jason Lou <yun.lou@intel.com>
>
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3334
>
> There are following PCDs in IntelFsp2WrapperPkg for microcode location:
>
> * IntelFsp2WrapperPkg:
> PcdCpuMicrocodePatchAddress
> PcdCpuMicrocodePatchRegionSize
> PcdFlashMicrocodeOffset
>
> The change simplify the platform code to use following PCDs instead:
> * MinPlatformPkg
> PcdFlashFvMicrocodeOffset
> PcdFlashFvMicrocodeBase = $(BIOS_BASE) + PcdFlashFvMicrocodeOffset
> PcdFlashFvMicrocodeSize
> PcdMicrocodeOffsetInFv <NEW>
>
> Signed-off-by: Jason Lou <yun.lou@intel.com>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> Cc: Star Zeng <star.zeng@intel.com>
> Cc: Ray Ni <ray.ni@intel.com>
> ---
> Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf | 6 ++-
> ---
> Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf | 6
> ++----
> 2 files changed, 4 insertions(+), 8 deletions(-)
>
> diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf
> b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf
> index 196f04c68d..bcd1ade72b 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf
> @@ -1,7 +1,7 @@
> ## @file
>
> # System 76 GalagoPro3 board flash file.
>
> #
>
> -# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
>
> +# Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.<BR>
>
> #
>
> # SPDX-License-Identifier: BSD-2-Clause-Patent
>
> #
>
> @@ -45,9 +45,7 @@ SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =
> $(gSiPkgTokenSpaceGuid.PcdFla
> SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =
> $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize)
>
> SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =
> $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60
>
> SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =
> $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60
>
> -SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress =
> $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) +
> $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset)
>
> -SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =
> $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize)
>
> -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset = 0x60
>
> +SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv = 0x60
>
> SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =
> gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase
>
> SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =
> gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
>
> SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =
> gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset
>
> diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf
> b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf
> index f2cfff1c7b..6cdf4e2f9f 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf
> @@ -1,7 +1,7 @@
> ## @file
>
> # FDF file of Platform.
>
> #
>
> -# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
>
> +# Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>
>
> #
>
> # SPDX-License-Identifier: BSD-2-Clause-Patent
>
> #
>
> @@ -45,9 +45,7 @@ SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =
> $(gSiPkgTokenSpaceGuid.PcdFla
> SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =
> $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize)
>
> SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =
> $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60
>
> SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =
> $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60
>
> -SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress =
> $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) +
> $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset)
>
> -SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =
> $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize)
>
> -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset = 0x60
>
> +SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv = 0x60
>
> SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =
> gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase
>
> SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =
> gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
>
> SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =
> gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset
>
> --
> 2.28.0.windows.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v1] Intel/TigerlakeOpenBoardPkg: Simplify microcode related PCD usage
2021-04-25 14:41 ` [PATCH v1] Intel/TigerlakeOpenBoardPkg: " Jason Lou
@ 2021-04-26 0:42 ` Chiu, Chasel
2021-04-30 4:31 ` [edk2-devel] " Chaganty, Rangasai V
0 siblings, 1 reply; 9+ messages in thread
From: Chiu, Chasel @ 2021-04-26 0:42 UTC (permalink / raw)
To: Lou, Yun, devel@edk2.groups.io; +Cc: Desimone, Nathaniel L, Zeng, Star, Ni, Ray
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
> -----Original Message-----
> From: Lou, Yun <yun.lou@intel.com>
> Sent: Sunday, April 25, 2021 10:42 PM
> To: devel@edk2.groups.io
> Cc: Lou, Yun <yun.lou@intel.com>; Chiu, Chasel <chasel.chiu@intel.com>;
> Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Zeng, Star
> <star.zeng@intel.com>; Ni, Ray <ray.ni@intel.com>
> Subject: [PATCH v1] Intel/TigerlakeOpenBoardPkg: Simplify microcode related
> PCD usage
>
> From: Jason Lou <yun.lou@intel.com>
>
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3334
>
> There are following PCDs in IntelFsp2WrapperPkg for microcode location:
>
> * IntelFsp2WrapperPkg:
> PcdCpuMicrocodePatchAddress
> PcdCpuMicrocodePatchRegionSize
> PcdFlashMicrocodeOffset
>
> The change simplify the platform code to use following PCDs instead:
> * MinPlatformPkg
> PcdFlashFvMicrocodeOffset
> PcdFlashFvMicrocodeBase = $(BIOS_BASE) + PcdFlashFvMicrocodeOffset
> PcdFlashFvMicrocodeSize
> PcdMicrocodeOffsetInFv <NEW>
>
> Signed-off-by: Jason Lou <yun.lou@intel.com>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> Cc: Star Zeng <star.zeng@intel.com>
> Cc: Ray Ni <ray.ni@intel.com>
> ---
> Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.fdf | 4
> +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git
> a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.fdf
> b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.fdf
> index 0f645ed63e..c1fd2be6af 100644
> --- a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.fdf
> +++
> b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.fdf
> @@ -47,14 +47,12 @@ SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =
> $(gSiPkgTokenSpaceGuid.PcdBio
> SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =
> $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize)
>
> SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =
> $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) +
> $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeOffset)
>
> SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =
> $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) -
> $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeOffset)
>
> -SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress =
> $(gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress)
>
> -SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =
> $(gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize)
>
> -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset =
> $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeOffset)
>
> SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress =
> gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress
>
> SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize =
> gSiPkgTokenSpaceGuid.PcdBiosSize
>
> SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress =
> $(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) +
> $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset)
>
> SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress =
> $(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) +
> $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset)
>
> SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress =
> $(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) +
> $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset)
>
> +SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv =
> gSiPkgTokenSpaceGuid.PcdFlashMicrocodeOffset
>
> SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =
> gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase
>
> SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =
> gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
>
> SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =
> gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset
>
> --
> 2.28.0.windows.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v1] Intel/WhiskeylakeOpenBoardPkg: Simplify microcode related PCD usage
2021-04-25 14:41 ` [PATCH v1] Intel/WhiskeylakeOpenBoardPkg: " Jason Lou
@ 2021-04-26 0:42 ` Chiu, Chasel
0 siblings, 0 replies; 9+ messages in thread
From: Chiu, Chasel @ 2021-04-26 0:42 UTC (permalink / raw)
To: Lou, Yun, devel@edk2.groups.io; +Cc: Desimone, Nathaniel L, Zeng, Star, Ni, Ray
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
> -----Original Message-----
> From: Lou, Yun <yun.lou@intel.com>
> Sent: Sunday, April 25, 2021 10:42 PM
> To: devel@edk2.groups.io
> Cc: Lou, Yun <yun.lou@intel.com>; Chiu, Chasel <chasel.chiu@intel.com>;
> Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Zeng, Star
> <star.zeng@intel.com>; Ni, Ray <ray.ni@intel.com>
> Subject: [PATCH v1] Intel/WhiskeylakeOpenBoardPkg: Simplify microcode
> related PCD usage
>
> From: Jason Lou <yun.lou@intel.com>
>
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3334
>
> There are following PCDs in IntelFsp2WrapperPkg for microcode location:
>
> * IntelFsp2WrapperPkg:
> PcdCpuMicrocodePatchAddress
> PcdCpuMicrocodePatchRegionSize
> PcdFlashMicrocodeOffset
>
> The change simplify the platform code to use following PCDs instead:
> * MinPlatformPkg
> PcdFlashFvMicrocodeOffset
> PcdFlashFvMicrocodeBase = $(BIOS_BASE) + PcdFlashFvMicrocodeOffset
> PcdFlashFvMicrocodeSize
> PcdMicrocodeOffsetInFv <NEW>
>
> Signed-off-by: Jason Lou <yun.lou@intel.com>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> Cc: Star Zeng <star.zeng@intel.com>
> Cc: Ray Ni <ray.ni@intel.com>
> ---
>
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecF
> spWrapperPlatformSecLib/SecRamInitData.c | 6 +++---
>
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecF
> spWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf | 8 ++++----
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.fdf
> | 6 ++----
>
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.fd
> f | 6 ++----
> 4 files changed, 11 insertions(+), 15 deletions(-)
>
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/Se
> cFspWrapperPlatformSecLib/SecRamInitData.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/Se
> cFspWrapperPlatformSecLib/SecRamInitData.c
> index 8442e5fbff..41a37f5da5 100644
> ---
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/Se
> cFspWrapperPlatformSecLib/SecRamInitData.c
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/Se
> cFspWrapperPlatformSecLib/SecRamInitData.c
> @@ -1,7 +1,7 @@
> /** @file
>
> Provide TempRamInitParams data.
>
>
>
> -Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
>
> +Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.<BR>
>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
>
>
> **/
>
> @@ -24,8 +24,8 @@ GLOBAL_REMOVE_IF_UNREFERENCED CONST FSPT_UPD
> FsptUpdDataPtr = {
> },
>
> // FSPT_CORE_UPD
>
> {
>
> - ((UINT32) FixedPcdGet64 (PcdCpuMicrocodePatchAddress) + FixedPcdGet32
> (PcdFlashMicrocodeOffset)),
>
> - ((UINT32) FixedPcdGet64 (PcdCpuMicrocodePatchRegionSize) -
> FixedPcdGet32 (PcdFlashMicrocodeOffset)),
>
> + FixedPcdGet32 (PcdFlashFvMicrocodeBase) + FixedPcdGet32
> (PcdMicrocodeOffsetInFv),
>
> + FixedPcdGet32 (PcdFlashFvMicrocodeSize) - FixedPcdGet32
> (PcdMicrocodeOffsetInFv),
>
> 0, // Set CodeRegionBase as 0, so that caching will be 4GB-
> (CodeRegionSize > LLCSize ? LLCSize : CodeRegionSize) will be used.
>
> FixedPcdGet32 (PcdFlashCodeCacheSize),
>
> { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
>
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/Se
> cFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/Se
> cFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
> index b17226d43b..e7319cf9e7 100644
> ---
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/Se
> cFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/Se
> cFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
> @@ -1,7 +1,7 @@
> ## @file
>
> # Provide FSP wrapper platform sec related function.
>
> #
>
> -# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
>
> +# Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.<BR>
>
> #
>
> # SPDX-License-Identifier: BSD-2-Clause-Patent
>
> #
>
> @@ -92,9 +92,9 @@
> [FixedPcd]
>
> gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ##
> CONSUMES
>
> gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate ##
> CONSUMES
>
> - gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress ##
> CONSUMES
>
> - gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize ##
> CONSUMES
>
> - gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset ##
> CONSUMES
>
> + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase ##
> CONSUMES
>
> + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize ##
> CONSUMES
>
> + gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv ##
> CONSUMES
>
> gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress ##
> CONSUMES
>
> gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize ##
> CONSUMES
>
> gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress ##
> CONSUMES
>
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.fdf
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.fdf
> index 0d99114961..22fbfc99f0 100644
> --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.fdf
> +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.fdf
> @@ -2,7 +2,7 @@
> # FDF file for the UpXtreme.
>
> #
>
> #
>
> -# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
>
> +# Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.<BR>
>
> #
>
> # SPDX-License-Identifier: BSD-2-Clause-Patent
>
> #
>
> @@ -47,9 +47,7 @@ SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =
> $(gSiPkgTokenSpaceGuid.PcdBio
> SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =
> $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize)
>
> SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =
> $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60
>
> SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =
> $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60
>
> -SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress =
> $(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) +
> $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset)
>
> -SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =
> $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize)
>
> -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset = 0x60
>
> +SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv = 0x60
>
> SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =
> gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase
>
> SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =
> gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
>
> SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =
> gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset
>
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.
> fdf
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.
> fdf
> index ad32268a82..1ab8c13792 100644
> ---
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.
> fdf
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.
> fdf
> @@ -2,7 +2,7 @@
> # FDF file of Platform.
>
> #
>
> #
>
> -# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
>
> +# Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.<BR>
>
> #
>
> # SPDX-License-Identifier: BSD-2-Clause-Patent
>
> #
>
> @@ -47,9 +47,7 @@ SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =
> $(gSiPkgTokenSpaceGuid.PcdBio
> SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =
> $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize)
>
> SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =
> $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60
>
> SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =
> $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60
>
> -SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress =
> $(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) +
> $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset)
>
> -SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =
> $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize)
>
> -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset = 0x60
>
> +SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv = 0x60
>
> SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =
> gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase
>
> SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =
> gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
>
> SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =
> gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset
>
> --
> 2.28.0.windows.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [edk2-devel] [PATCH v1] Intel/TigerlakeOpenBoardPkg: Simplify microcode related PCD usage
2021-04-26 0:42 ` Chiu, Chasel
@ 2021-04-30 4:31 ` Chaganty, Rangasai V
0 siblings, 0 replies; 9+ messages in thread
From: Chaganty, Rangasai V @ 2021-04-30 4:31 UTC (permalink / raw)
To: Chiu, Chasel, devel
[-- Attachment #1: Type: text/plain, Size: 61 bytes --]
Reviewed-by: Sai Chaganty < rangasai.v.chaganty@intel.com >
[-- Attachment #2: Type: text/html, Size: 144 bytes --]
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2021-04-30 4:31 UTC | newest]
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2021-04-25 14:41 [PATCH v1] Intel/CometlakeOpenBoardPkg: Simplify microcode related PCD usage Jason Lou
2021-04-25 14:41 ` [PATCH v1] Intel/KabylakeOpenBoardPkg: " Jason Lou
2021-04-26 0:42 ` Chiu, Chasel
2021-04-25 14:41 ` [PATCH v1] Intel/TigerlakeOpenBoardPkg: " Jason Lou
2021-04-26 0:42 ` Chiu, Chasel
2021-04-30 4:31 ` [edk2-devel] " Chaganty, Rangasai V
2021-04-25 14:41 ` [PATCH v1] Intel/WhiskeylakeOpenBoardPkg: " Jason Lou
2021-04-26 0:42 ` Chiu, Chasel
2021-04-26 0:42 ` [PATCH v1] Intel/CometlakeOpenBoardPkg: " Chiu, Chasel
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