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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Chasel Chiu > -----Original Message----- > From: Lou, Yun > Sent: Sunday, April 25, 2021 10:42 PM > To: devel@edk2.groups.io > Cc: Lou, Yun ; Chiu, Chasel ; > Desimone, Nathaniel L ; Zeng, Star > ; Ni, Ray > Subject: [PATCH v1] Intel/TigerlakeOpenBoardPkg: Simplify microcode relat= ed > PCD usage >=20 > From: Jason Lou >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3334 >=20 > There are following PCDs in IntelFsp2WrapperPkg for microcode location: >=20 > * IntelFsp2WrapperPkg: > PcdCpuMicrocodePatchAddress > PcdCpuMicrocodePatchRegionSize > PcdFlashMicrocodeOffset >=20 > The change simplify the platform code to use following PCDs instead: > * MinPlatformPkg > PcdFlashFvMicrocodeOffset > PcdFlashFvMicrocodeBase =3D $(BIOS_BASE) + PcdFlashFvMicrocodeOffset > PcdFlashFvMicrocodeSize > PcdMicrocodeOffsetInFv >=20 > Signed-off-by: Jason Lou > Cc: Chasel Chiu > Cc: Nate DeSimone > Cc: Star Zeng > Cc: Ray Ni > --- > Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.fdf | 4 > +--- > 1 file changed, 1 insertion(+), 3 deletions(-) >=20 > diff --git > a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.fdf > b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.fdf > index 0f645ed63e..c1fd2be6af 100644 > --- a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.fdf > +++ > b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.fdf > @@ -47,14 +47,12 @@ SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =3D > $(gSiPkgTokenSpaceGuid.PcdBio > SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D > $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) >=20 > SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D > $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + > $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeOffset) >=20 > SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D > $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) - > $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeOffset) >=20 > -SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D > $(gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress) >=20 > -SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D > $(gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize) >=20 > -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset =3D > $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeOffset) >=20 > SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress =3D > gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress >=20 > SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize =3D > gSiPkgTokenSpaceGuid.PcdBiosSize >=20 > SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress =3D > $(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + > $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset) >=20 > SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress =3D > $(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + > $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset) >=20 > SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress =3D > $(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + > $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset) >=20 > +SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv =3D > gSiPkgTokenSpaceGuid.PcdFlashMicrocodeOffset >=20 > SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =3D > gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase >=20 > SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =3D > gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize >=20 > SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =3D > gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset >=20 > -- > 2.28.0.windows.1