Sean, the RISC-V edk2 port patches against to ek2-stating were reviewed. The submodule one attached FYR.

We have three sets of RISC-V edk2 port patches,

1.  Patches for RISC-V EDK2  CI enablement (This is what you are reviewing now).

2.  Patches for edk2 modules other than RISC-V ones, which fix the issues for building  packages respectively on RISC-V arch.

3 . RISC-V edk2 port

Patch of submodule is belong to #3 set.

We will have to make #1 and #2 to get in edk2 master and then submit #3 against to edk2/master, pull request to trigger CI as well.

Thanks

Abner

From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of Sean via Groups.Io
Sent: Sunday, March 8, 2020 6:09 AM
To: Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com>; devel@edk2.groups.io
Subject: Re: [edk2-devel] [edk2/master PATCH RISC-V CI v1 6/6] .pytool: Add RISC-V architecture on RISC-V EDK2 CI.

I never saw a patch in the series that actually added the submodule to the .gitmodules file but maybe i missed that.  If that is approved then the changes to this file look ok.  I have no idea why all the line endings are shown but the substantial changes here look fine to me.