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Thread-Topic: [PATCH 10/15] [platforms/devel-riscv-v2]: U500Pkg/Library: Library instances of U500 platform library. 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The "platform.c" under OpenSbiPlatformLib is cloned from RI= SC-V OpenSBI code tree (in EDK2 RiscVPkg) and built based on EDK2 build env= ironment. PeiCoreInfoHobLib - This is the library to create RISC-V core characteristics for building up= RISC-V related SMBIOS records to support the unified boot loader and OS im= age. - RiscVPlatformTimerLib This is U500 platform timer library which has the platform-specific timer i= mplementation. - SerialPortLib U500 serial port platform library Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Gilbert Chen --- .../OpenSbiPlatformLib/OpenSbiPlatformLib.inf | 53 +++++ .../U500Pkg/Library/OpenSbiPlatformLib/platform.c | 214 ++++++++++++++++++ .../Library/PeiCoreInfoHobLib/CoreInfoHob.c | 201 +++++++++++++++++ .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 64 ++++++ .../RiscVPlatformTimerLib.inf | 46 ++++ .../RiscVPlatformTimerLib/RiscVPlatformTimerLib.s | 54 +++++ .../U500Pkg/Library/SerialIoLib/SerialIoLib.inf | 37 +++ .../U500Pkg/Library/SerialIoLib/SerialPortLib.c | 247 +++++++++++++++++= ++++ .../Library/SerialIoLib/U500SerialPortLib.uni | 22 ++ 9 files changed, 938 insertions(+) create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLi= b/OpenSbiPlatformLib.inf create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLi= b/platform.c create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/PeiCoreInfoHobLib= /CoreInfoHob.c create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/PeiCoreInfoHobLib= /PeiCoreInfoHobLib.inf create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/RiscVPlatformTime= rLib/RiscVPlatformTimerLib.inf create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/RiscVPlatformTime= rLib/RiscVPlatformTimerLib.s create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/Seria= lIoLib.inf create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/Seria= lPortLib.c create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/U500S= erialPortLib.uni diff --git a/Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/OpenS= biPlatformLib.inf b/Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLi= b/OpenSbiPlatformLib.inf new file mode 100644 index 0000000..1823e48 --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/OpenSbiPlatf= ormLib.inf @@ -0,0 +1,53 @@ +## @file +# RISC-V OpenSbi Platform Library +# This is the the required library which provides platform +# level opensbi functions follow RISC-V opensbi implementation. +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may b= e found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D OpenSbiPlatformLib + FILE_GUID =3D 9424ED54-EBDA-4FB5-8FF6-8291B07BB151 + MODULE_TYPE =3D SEC + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D OpenSbiPlatformLib + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D RISCV64 EBC +# + +[Sources] + platform.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + RiscVPkg/RiscVPkg.dec + Platform/RiscV/RiscVPlatformPkg.dec + +[LibraryClasses] + BaseLib + DebugLib + BaseMemoryLib + PcdLib + DebugAgentLib + RiscVCpuLib + PrintLib + +[FixedPcd] + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId diff --git a/Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/platf= orm.c b/Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/platform.c new file mode 100644 index 0000000..887a279 --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/platform.c @@ -0,0 +1,214 @@ +/* + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates. + * + * Authors: + * Atish Patra + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +#define U500_HART_COUNTFixedPcdGet32(PcdHartCount) +#define U500_HART_STACK_SIZEFixedPcdGet32(PcdOpenSbiStackSize) +#define U500_BOOT_HART_ID FixedPcdGet32(PcdBootHartId) + +#define U500_SYS_CLK100000000 + +#define U500_CLINT_ADDR0x2000000 + +#define U500_PLIC_ADDR0xc000000 +#define U500_PLIC_NUM_SOURCES0x35 +#define U500_PLIC_NUM_PRIORITIES7 + +#define U500_UART_ADDR0x54000000 + +#define U500_UART_BAUDRATE115200 + +/** + * The U500 SoC has 8 HARTs but HART ID 0 doesn't have S mode. + * HARTs 1 is selected as boot HART + */ +#ifndef U500_ENABLED_HART_MASK +#define U500_ENABLED_HART_MASK(1 << U500_BOOT_HART_ID) +#endif + +#define U500_HARTID_DISABLED~(U500_ENABLED_HART_MASK) + +/* PRCI clock related macros */ +//TODO: Do we need a separate driver for this ? +#define U500_PRCI_BASE_ADDR0x10000000 +#define U500_PRCI_CLKMUXSTATUSREG0x002C +#define U500_PRCI_CLKMUX_STATUS_TLCLKSEL(0x1 << 1) + +static void U500_modify_dt(void *fdt) +{ +u32 i, size; +int chosen_offset, err; +int cpu_offset; +char cpu_node[32] =3D ""; +const char *mmu_type; + +for (i =3D 0; i < U500_HART_COUNT; i++) { +sbi_sprintf(cpu_node, "/cpus/cpu@%d", i); +cpu_offset =3D fdt_path_offset(fdt, cpu_node); +mmu_type =3D fdt_getprop(fdt, cpu_offset, "mmu-type", NULL); +if (mmu_type && (!strcmp(mmu_type, "riscv,sv39") || + !strcmp(mmu_type,"riscv,sv48"))) +continue; +else +fdt_setprop_string(fdt, cpu_offset, "status", "masked"); +memset(cpu_node, 0, sizeof(cpu_node)); +} +size =3D fdt_totalsize(fdt); +err =3D fdt_open_into(fdt, fdt, size + 256); +if (err < 0) +sbi_printf("Device Tree can't be expanded to accmodate new node"); + +chosen_offset =3D fdt_path_offset(fdt, "/chosen"); +fdt_setprop_string(fdt, chosen_offset, "stdout-path", + "/soc/serial@10010000:115200"); + +plic_fdt_fixup(fdt, "riscv,plic0"); +} + +static int U500_final_init(bool cold_boot) +{ +void *fdt; + +if (!cold_boot) +return 0; + +fdt =3D sbi_scratch_thishart_arg1_ptr(); +U500_modify_dt(fdt); + +return 0; +} + +static u32 U500_pmp_region_count(u32 hartid) +{ +return 1; +} + +static int U500_pmp_region_info(u32 hartid, u32 index, + ulong *prot, ulong *addr, ulong *log2size) +{ +int ret =3D 0; + +switch (index) { +case 0: +*prot =3D PMP_R | PMP_W | PMP_X; +*addr =3D 0; +*log2size =3D __riscv_xlen; +break; +default: +ret =3D -1; +break; +}; + +return ret; +} + +static int U500_console_init(void) +{ +unsigned long peri_in_freq; + +peri_in_freq =3D U500_SYS_CLK/2; +return sifive_uart_init(U500_UART_ADDR, peri_in_freq, U500_UART_BAUDRATE); +} + +static int U500_irqchip_init(bool cold_boot) +{ +int rc; +u32 hartid =3D sbi_current_hartid(); + +if (cold_boot) { +rc =3D plic_cold_irqchip_init(U500_PLIC_ADDR, + U500_PLIC_NUM_SOURCES, + U500_HART_COUNT); +if (rc) +return rc; +} + +return plic_warm_irqchip_init(hartid, +(hartid) ? (2 * hartid - 1) : 0, +(hartid) ? (2 * hartid) : -1); +} + +static int U500_ipi_init(bool cold_boot) +{ +int rc; + +if (cold_boot) { +rc =3D clint_cold_ipi_init(U500_CLINT_ADDR, + U500_HART_COUNT); +if (rc) +return rc; + +} + +return clint_warm_ipi_init(); +} + +static int U500_timer_init(bool cold_boot) +{ +int rc; + +if (cold_boot) { +rc =3D clint_cold_timer_init(U500_CLINT_ADDR, + U500_HART_COUNT); +if (rc) +return rc; +} + +return clint_warm_timer_init(); +} + +static int U500_system_down(u32 type) +{ +/* For now nothing to do. */ +return 0; +} + +const struct sbi_platform_operations platform_ops =3D { +.pmp_region_count =3D U500_pmp_region_count, +.pmp_region_info =3D U500_pmp_region_info, +.final_init =3D U500_final_init, +.console_putc =3D sifive_uart_putc, +.console_getc =3D sifive_uart_getc, +.console_init =3D U500_console_init, +.irqchip_init =3D U500_irqchip_init, +.ipi_send =3D clint_ipi_send, +.ipi_sync =3D clint_ipi_sync, +.ipi_clear =3D clint_ipi_clear, +.ipi_init =3D U500_ipi_init, +.timer_value =3D clint_timer_value, +.timer_event_stop =3D clint_timer_event_stop, +.timer_event_start =3D clint_timer_event_start, +.timer_init =3D U500_timer_init, +.system_reboot =3D U500_system_down, +.system_shutdown =3D U500_system_down +}; + +const struct sbi_platform platform =3D { +.opensbi_version=3D OPENSBI_VERSION,// The OpenSBI version this platform t= able is built bassed on. +.platform_version=3D SBI_PLATFORM_VERSION(0x0001, 0x0000),// SBI Platform = version 1.0 +.name=3D "SiFive Freedom U500", +.features=3D SBI_PLATFORM_DEFAULT_FEATURES, +.hart_count=3D U500_HART_COUNT, +.hart_stack_size=3D U500_HART_STACK_SIZE, +.disabled_hart_mask=3D U500_HARTID_DISABLED, +.platform_ops_addr=3D (unsigned long)&platform_ops +}; diff --git a/Platform/RiscV/SiFive/U500Pkg/Library/PeiCoreInfoHobLib/CoreIn= foHob.c b/Platform/RiscV/SiFive/U500Pkg/Library/PeiCoreInfoHobLib/CoreInfoH= ob.c new file mode 100644 index 0000000..2db4fdc --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c @@ -0,0 +1,201 @@ +/**@file + Build up platform processor information. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +// +// The package level header files this module uses +// +#include + +// +// The Library classes this module consumes +// +#include +#include +#include + +#include +#include +#include +#include +#include + +/** + Build up processor-specific HOB for U5MC Coreplex + + @param UniqueId Unique ID of this U5MC Coreplex processor + + @return EFI_SUCCESS The PEIM initialized successfully. + +**/ +EFI_STATUS +EFIAPI +CreateU5MCCoreplexProcessorSpecificDataHob ( + IN UINTN UniqueId + ) +{ + EFI_STATUS Status; + UINT32 HartIdNumber; + RISC_V_PROCESSOR_SPECIFIC_DATA_HOB *GuidHobData; + EFI_GUID *ParentCoreGuid; + BOOLEAN MCSupport; + + DEBUG ((EFI_D_INFO, "Building U5 Coreplex processor information HOB\n")); + + HartIdNumber =3D 0; + ParentCoreGuid =3D PcdGetPtr(PcdSiFiveU5MCCoreplexGuid); + MCSupport =3D PcdGetBool (PcdE5MCSupported); + if (MCSupport =3D=3D TRUE) { + Status =3D CreateE51CoreProcessorSpecificDataHob (ParentCoreGuid, Uniq= ueId, HartIdNumber, FALSE, &GuidHobData); + if (EFI_ERROR (Status)) { + DEBUG ((EFI_D_ERROR, "Faile to build U5MC processor informatino HOB\= n")); + ASSERT (FALSE); + } + HartIdNumber ++; + DEBUG ((EFI_D_INFO, "Support E5 Monitor core on U500 platform, HOB at = address 0x%x\n", GuidHobData)); + } + for (; HartIdNumber < (FixedPcdGet32 (PcdNumberofU5Cores) + (UINT32)MCSu= pport); HartIdNumber ++) { + Status =3D CreateU54CoreProcessorSpecificDataHob (ParentCoreGuid, Uniq= ueId, HartIdNumber, (HartIdNumber =3D=3D FixedPcdGet32 (PcdBootHartId))? TR= UE: FALSE, &GuidHobData); + if (EFI_ERROR (Status)) { + DEBUG ((EFI_D_ERROR, "Faile to build U5MC processor informatino HOB\= n")); + ASSERT (FALSE); + } + DEBUG ((EFI_D_INFO, "Support U5 application core on U500 platform, HOB= Data at address 0x%x\n", GuidHobData)); + } + DEBUG ((EFI_D_INFO, "Support %d U5 application cores on U500 platform\n"= , HartIdNumber - (UINT32)MCSupport)); + + if (HartIdNumber !=3D FixedPcdGet32 (PcdHartCount)) { + DEBUG ((EFI_D_ERROR, "Improper core settings...\n")); + DEBUG ((EFI_D_ERROR, " PcdHartCount\n")); + DEBUG ((EFI_D_ERROR, " PcdNumberofU5Cores\n")); + DEBUG ((EFI_D_ERROR, " PcdE5MCSupported\n\n")); + ASSERT (FALSE); + } + return Status; +} + +/** + Function to build processor related SMBIOS information. RISC-V SMBIOS DX= E driver collect + this information and build SMBIOS Type4 and Type7 record. + + @param ProcessorUid Unique ID of pysical processor which owns this c= ore. + @param SmbiosHobPtr Pointer to receive RISC_V_PROCESSOR_SMBIOS_DATA_= HOB. The pointers + maintained in this structure is only valid befor= e memory is discovered. + Access to those pointers after memory is install= ed will cause unexpected issues. + + @return EFI_SUCCESS The PEIM initialized successfully. + +**/ +EFI_STATUS +EFIAPI +CreateU5MCProcessorSmbiosDataHob ( + IN UINTN ProcessorUid, + OUT RISC_V_PROCESSOR_SMBIOS_DATA_HOB **SmbiosHobPtr + ) +{ + EFI_GUID *GuidPtr; + RISC_V_PROCESSOR_TYPE4_DATA_HOB ProcessorDataHob; + RISC_V_PROCESSOR_TYPE7_DATA_HOB L2CacheDataHob; + RISC_V_PROCESSOR_SMBIOS_DATA_HOB SmbiosDataHob; + RISC_V_PROCESSOR_TYPE4_DATA_HOB *ProcessorDataHobPtr; + RISC_V_PROCESSOR_TYPE7_DATA_HOB *L2CacheDataHobPtr; + RISC_V_PROCESSOR_SMBIOS_DATA_HOB *SmbiosDataHobPtr; + + DEBUG ((EFI_D_INFO, "%a: Entry\n", __FUNCTION__)); + + if (SmbiosHobPtr =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + // + // Build up SMBIOS type 7 L2 cache record. + // + ZeroMem((VOID *)&L2CacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_DATA_HOB= )); + L2CacheDataHob.PrcessorGuid =3D *((EFI_GUID *)PcdGetPtr (PcdSiFiveU5MCCo= replexGuid)); + L2CacheDataHob.ProcessorUid =3D ProcessorUid; + L2CacheDataHob.SmbiosType7Cache.SocketDesignation =3D TO_BE_FILLED_BY_VE= NDOR; + L2CacheDataHob.SmbiosType7Cache.CacheConfiguration =3D RISC_V_CACHE_CONF= IGURATION_CACHE_LEVEL_2 | \ + RISC_V_CACHE_CONFIGURATION_LOCATION_EXTERNAL | \ + RISC_V_CACHE_CONFIGURATION_ENABLED | \ + RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN; + L2CacheDataHob.SmbiosType7Cache.MaximumCacheSize =3D TO_BE_FILLED_BY_VEN= DOR; + L2CacheDataHob.SmbiosType7Cache.InstalledSize =3D TO_BE_FILLED_BY_VENDOR; + L2CacheDataHob.SmbiosType7Cache.SupportedSRAMType.Unknown =3D 1; + L2CacheDataHob.SmbiosType7Cache.CurrentSRAMType.Unknown =3D 1; + L2CacheDataHob.SmbiosType7Cache.CacheSpeed =3D TO_BE_FILLED_BY_VENDOR; + L2CacheDataHob.SmbiosType7Cache.ErrorCorrectionType =3D TO_BE_FILLED_BY_= VENDOR; + L2CacheDataHob.SmbiosType7Cache.SystemCacheType =3D CacheTypeUnified; + L2CacheDataHob.SmbiosType7Cache.Associativity =3D TO_BE_FILLED_BY_VENDOR; + GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType7GuidHobGuid); + L2CacheDataHobPtr =3D (RISC_V_PROCESSOR_TYPE7_DATA_HOB *)BuildGuidDataHo= b (GuidPtr, (VOID *)&L2CacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_DATA_HO= B)); + if (L2CacheDataHobPtr =3D=3D NULL) { + DEBUG ((EFI_D_ERROR, "Fail to create GUID HOB of SiFive U5 MC Coreplex= L2 cache RISC_V_PROCESSOR_TYPE7_DATA_HOB.\n")); + ASSERT (FALSE); + } + + // + // Build up SMBIOS type 4 record. + // + ZeroMem((VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_DATA_H= OB)); + ProcessorDataHob.PrcessorGuid =3D *((EFI_GUID *)PcdGetPtr (PcdSiFiveU5MC= CoreplexGuid)); + ProcessorDataHob.ProcessorUid =3D ProcessorUid; + ProcessorDataHob.SmbiosType4Processor.Socket =3D TO_BE_FILLED_BY_VENDOR; + ProcessorDataHob.SmbiosType4Processor.ProcessorType =3D CentralProcessor; + ProcessorDataHob.SmbiosType4Processor.ProcessorFamily =3D ProcessorFamil= yIndicatorFamily2; + ProcessorDataHob.SmbiosType4Processor.ProcessorManufacture =3D TO_BE_FIL= LED_BY_VENDOR; + SetMem ((VOID *)&ProcessorDataHob.SmbiosType4Processor.ProcessorId, size= of (PROCESSOR_ID_DATA), TO_BE_FILLED_BY_CODE); + ProcessorDataHob.SmbiosType4Processor.ProcessorVersion =3D TO_BE_FILLED_= BY_VENDOR; + ProcessorDataHob.SmbiosType4Processor.Voltage.ProcessorVoltageCapability= 3_3V =3D 1; + ProcessorDataHob.SmbiosType4Processor.ExternalClock =3D TO_BE_FILLED_BY_= VENDOR; + ProcessorDataHob.SmbiosType4Processor.MaxSpeed =3D TO_BE_FILLED_BY_VENDO= R; + ProcessorDataHob.SmbiosType4Processor.CurrentSpeed =3D TO_BE_FILLED_BY_V= ENDOR; + ProcessorDataHob.SmbiosType4Processor.Status =3D TO_BE_FILLED_BY_CODE; + ProcessorDataHob.SmbiosType4Processor.ProcessorUpgrade =3D TO_BE_FILLED_= BY_VENDOR; + ProcessorDataHob.SmbiosType4Processor.L1CacheHandle =3D TO_BE_FILLED_BY_= RISC_V_SMBIOS_DXE_DRIVER; + ProcessorDataHob.SmbiosType4Processor.L2CacheHandle =3D TO_BE_FILLED_BY_= RISC_V_SMBIOS_DXE_DRIVER; + ProcessorDataHob.SmbiosType4Processor.L3CacheHandle =3D 0xffff; + ProcessorDataHob.SmbiosType4Processor.SerialNumber =3D TO_BE_FILLED_BY_C= ODE; + ProcessorDataHob.SmbiosType4Processor.AssetTag =3D TO_BE_FILLED_BY_VENDO= R; + ProcessorDataHob.SmbiosType4Processor.PartNumber =3D TO_BE_FILLED_BY_VEN= DOR; + ProcessorDataHob.SmbiosType4Processor.CoreCount =3D (UINT8)FixedPcdGet32= (PcdNumberofU5Cores) + (UINT8)PcdGetBool (PcdE5MCSupported); + ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount =3D (UINT8)FixedP= cdGet32 (PcdNumberofU5Cores) + (UINT8)PcdGetBool (PcdE5MCSupported); + ProcessorDataHob.SmbiosType4Processor.ThreadCount =3D (UINT8)FixedPcdGet= 32 (PcdNumberofU5Cores) + (UINT8)PcdGetBool (PcdE5MCSupported); + ProcessorDataHob.SmbiosType4Processor.ProcessorCharacteristics =3D (UINT= 16)(1 << 2); // 64-bit capable + ProcessorDataHob.SmbiosType4Processor.ProcessorFamily2 =3D ProcessorFami= lyRiscVRV64; + ProcessorDataHob.SmbiosType4Processor.CoreCount2 =3D 0; + ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount2 =3D 0; + ProcessorDataHob.SmbiosType4Processor.ThreadCount2 =3D 0; + GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType4GuidHobGuid); + ProcessorDataHobPtr =3D (RISC_V_PROCESSOR_TYPE4_DATA_HOB *)BuildGuidData= Hob (GuidPtr, (VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_DAT= A_HOB)); + if (ProcessorDataHobPtr =3D=3D NULL) { + DEBUG ((EFI_D_ERROR, "Fail to create GUID HOB of SiFive U5MC Coreplex = RISC_V_PROCESSOR_TYPE4_DATA_HOB.\n")); + ASSERT (FALSE); + } + + ZeroMem((VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_DATA_HOB= )); + SmbiosDataHob.Processor =3D ProcessorDataHobPtr; + SmbiosDataHob.L1InstCache =3D NULL; + SmbiosDataHob.L1DataCache =3D NULL; + SmbiosDataHob.L2Cache =3D L2CacheDataHobPtr; + SmbiosDataHob.L3Cache =3D NULL; + GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosGuidHobGuid); + SmbiosDataHobPtr =3D (RISC_V_PROCESSOR_SMBIOS_DATA_HOB *)BuildGuidDataHo= b (GuidPtr, (VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_DATA_HO= B)); + if (SmbiosDataHobPtr =3D=3D NULL) { + DEBUG ((EFI_D_ERROR, "Fail to create GUID HOB of SiFive U5MC Coreplex = RISC_V_PROCESSOR_SMBIOS_DATA_HOB.\n")); + ASSERT (FALSE); + } + *SmbiosHobPtr =3D SmbiosDataHobPtr; + DEBUG ((EFI_D_INFO, "%a: Exit\n", __FUNCTION__)); + return EFI_SUCCESS; +} diff --git a/Platform/RiscV/SiFive/U500Pkg/Library/PeiCoreInfoHobLib/PeiCor= eInfoHobLib.inf b/Platform/RiscV/SiFive/U500Pkg/Library/PeiCoreInfoHobLib/P= eiCoreInfoHobLib.inf new file mode 100644 index 0000000..716d0bb --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/Library/PeiCoreInfoHobLib/PeiCoreInfoHo= bLib.inf @@ -0,0 +1,64 @@ +## @file +# Library instance to create core information HOB +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D SiliconSiFiveU5MCCoreplexInfoLib + FILE_GUID =3D 4E397A71-5164-4E69-9884-70CBE2740AAB + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SiliconSiFiveU5MCCoreplexInfoLib + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D RISCV +# + +[Sources] + CoreInfoHob.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Platform/RiscV/RiscVPlatformPkg.dec + Platform/RiscV/SiFive/U500Pkg/U500.dec + Silicon/SiFive/SiFive.dec + RiscVPkg/RiscVPkg.dec + +[LibraryClasses] + BaseLib + PcdLib + MemoryAllocationLib + PrintLib + SiliconSiFiveE51CoreInfoLib + SiliconSiFiveU54CoreInfoLib + +[Guids] + gUefiRiscVPlatformU500PkgTokenSpaceGuid + +[Ppis] + +[FixedPcd] + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosGuidHobGuid + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType4GuidHobGuid + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType7GuidHobGuid + gEfiSiFiveSiliconSpaceGuid.PcdSiFiveU54CoreGuid + gEfiSiFiveSiliconSpaceGuid.PcdSiFiveE51CoreGuid + gEfiSiFiveSiliconSpaceGuid.PcdSiFiveU5MCCoreplexGuid + gUefiRiscVPlatformU500PkgTokenSpaceGuid.PcdNumberofU5Cores + gUefiRiscVPlatformU500PkgTokenSpaceGuid.PcdE5MCSupported + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId diff --git a/Platform/RiscV/SiFive/U500Pkg/Library/RiscVPlatformTimerLib/Ri= scVPlatformTimerLib.inf b/Platform/RiscV/SiFive/U500Pkg/Library/RiscVPlatfo= rmTimerLib/RiscVPlatformTimerLib.inf new file mode 100644 index 0000000..d1553da --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/Library/RiscVPlatformTimerLib/RiscVPlat= formTimerLib.inf @@ -0,0 +1,46 @@ +## @file +# RISC-V CPU lib to override timer mechanism for U500 platform. +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+# Copyright (c) 2007 - 2010, Intel Corporation. All rights reserved.
+# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BS= D License +# which accompanies this distribution. The full text of the license may b= e found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +# +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D RiscVPlatformTimerLib + FILE_GUID =3D AFA75BBD-DE9D-4E77-BD88-1EA401BE931D + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D RiscVPlatformTimerLib + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D RISCV32 RISCV64 +# + +[Sources] + +[Sources.RISCV32] + RiscVPlatformTimerLib.s + +[Sources.RISCV64] + RiscVPlatformTimerLib.s + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + RiscVPkg/RiscVPkg.dec + Platform/RiscV/SiFive/U500Pkg/U500.dec + + diff --git a/Platform/RiscV/SiFive/U500Pkg/Library/RiscVPlatformTimerLib/Ri= scVPlatformTimerLib.s b/Platform/RiscV/SiFive/U500Pkg/Library/RiscVPlatform= TimerLib/RiscVPlatformTimerLib.s new file mode 100644 index 0000000..fd22466 --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/Library/RiscVPlatformTimerLib/RiscVPlat= formTimerLib.s @@ -0,0 +1,54 @@ +//------------------------------------------------------------------------= ------ +// +// SiFive U500 Timer CSR functions. +// +// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the B= SD License +// which accompanies this distribution. The full text of the license may = be found at +// http://opensource.org/licenses/bsd-license.php. +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +// +//------------------------------------------------------------------------= ------ +#include +#include +#include + +.data + +.text +.align 3 + +.global ASM_PFX(RiscVReadMachineTimer) +.global ASM_PFX(RiscVSetMachineTimerCmp) +.global ASM_PFX(RiscVReadMachineTimerCmp) + +// +// Read machine timer CSR. +// @retval a0 : 64-bit machine timer. +// +ASM_PFX (RiscVReadMachineTimer): + li t1, CLINT_REG_MTIME + ld a0, (t1) + ret + +// +// Set machine timer compare CSR. +// @param a0 : UINT64 +// +ASM_PFX (RiscVSetMachineTimerCmp): + li t1, CLINT_REG_MTIMECMP0 + sd a0, (t1) + ret + +// +// Read machine timer compare CSR. +// @param a0 : UINT64 +// +ASM_PFX (RiscVReadMachineTimerCmp): + li t1, CLINT_REG_MTIMECMP0 + ld a0, (t1) + ret diff --git a/Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/SerialIoLib.= inf b/Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/SerialIoLib.inf new file mode 100644 index 0000000..6245484 --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/SerialIoLib.inf @@ -0,0 +1,37 @@ +## @file +# Library instance for SerialIo library class +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
+# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D U500SerialPortLib + MODULE_UNI_FILE =3D U500SerialPortLib.uni + FILE_GUID =3D FCC4FD2B-2FF6-4FFA-B363-7C1111E5DCE9 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SerialPortLib + +[Packages] + MdePkg/MdePkg.dec + RiscVPkg/RiscVPkg.dec + Platform/RiscV/RiscVPlatformPkg.dec + +[LibraryClasses] + BaseLib + IoLib + RiscVOpensbiLib + +[Sources] + SerialPortLib.c + diff --git a/Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/SerialPortLi= b.c b/Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/SerialPortLib.c new file mode 100644 index 0000000..84475fe --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/SerialPortLib.c @@ -0,0 +1,247 @@ +/** @file + UART Serial Port library functions + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include +#include +#include +#include + +#define REG32(p, i) ((p)[(i) >> 2]) + +//--------------------------------------------- +// UART Register Offsets +//--------------------------------------------- + +#define UART_REG_IP 0x14 + #define UART_IP_RXWM 0x02 + +//--------------------------------------------- +// UART Settings +//--------------------------------------------- + +#define U500_UART_ADDR 0x54000000 +#define U500_UART_BAUDRATE 115200 +#define U500_SYS_CLK 100000000 + +/** + Initialize the serial device hardware. + + If no initialization is required, then return RETURN_SUCCESS. + If the serial device was successfuly initialized, then return RETURN_SUC= CESS. + If the serial device could not be initialized, then return RETURN_DEVICE= _ERROR. + + @retval RETURN_SUCCESS The serial device was initialized. + @retval RETURN_DEVICE_ERROR The serail device could not be initialized. + +**/ +RETURN_STATUS +EFIAPI +SerialPortInitialize ( + VOID + ) +{ + if (sifive_uart_init (U500_UART_ADDR, U500_SYS_CLK/2, U500_UART_BAUDRATE= ) !=3D 0) { + return EFI_DEVICE_ERROR; + } + return RETURN_SUCCESS; +} + +/** + Write data from buffer to serial device. + + Writes NumberOfBytes data bytes from Buffer to the serial device. + The number of bytes actually written to the serial device is returned. + If the return value is less than NumberOfBytes, then the write operation= failed. + + If Buffer is NULL, then ASSERT(). + + If NumberOfBytes is zero, then return 0. + + @param Buffer Pointer to the data buffer to be written. + @param NumberOfBytes Number of bytes to written to the serial device. + + @retval 0 NumberOfBytes is 0. + @retval >0 The number of bytes written to the serial devic= e. + If this value is less than NumberOfBytes, then = the write operation failed. + +**/ +UINTN +EFIAPI +SerialPortWrite ( + IN UINT8 *Buffer, + IN UINTN NumberOfBytes + ) +{ + UINTN i; + + if (Buffer =3D=3D NULL) { + return 0; + } + + for(i=3D0; i < NumberOfBytes; i++) { + sifive_uart_putc (Buffer[i]); + } + + return i; +} + + +/** + Reads data from a serial device into a buffer. + + @param Buffer Pointer to the data buffer to store the data re= ad from the serial device. + @param NumberOfBytes Number of bytes to read from the serial device. + + @retval 0 NumberOfBytes is 0. + @retval >0 The number of bytes read from the serial device. + If this value is less than NumberOfBytes, then = the read operation failed. + +**/ +UINTN +EFIAPI +SerialPortRead ( + OUT UINT8 *Buffer, + IN UINTN NumberOfBytes + ) +{ + UINTN i; + + if (NULL =3D=3D Buffer) { + return 0; + } + + for(i=3D0; i < NumberOfBytes; i++) { + Buffer[i] =3D (UINT8)sifive_uart_getc (); + } + + return i; +} + +/** + Polls a serial device to see if there is any data waiting to be read. + + Polls aserial device to see if there is any data waiting to be read. + If there is data waiting to be read from the serial device, then TRUE is= returned. + If there is no data waiting to be read from the serial device, then FALS= E is returned. + + @retval TRUE Data is waiting to be read from the serial devi= ce. + @retval FALSE There is no data waiting to be read from the se= rial device. + +**/ +BOOLEAN +EFIAPI +SerialPortPoll ( + VOID + ) +{ + static volatile UINT32 * const uart =3D (void *)(U500_UART_ADDR); + UINT32 ip; + + ip =3D REG32(uart, UART_REG_IP); + if(ip & UART_IP_RXWM) { + return TRUE; + } + else { + return FALSE; + } +} + +/** + Sets the control bits on a serial device. + + @param Control Sets the bits of Control that are settable. + + @retval RETURN_SUCCESS The new control bits were set on the seria= l device. + @retval RETURN_UNSUPPORTED The serial device does not support this op= eration. + @retval RETURN_DEVICE_ERROR The serial device is not functioning corre= ctly. + +**/ +RETURN_STATUS +EFIAPI +SerialPortSetControl ( + IN UINT32 Control + ) +{ + + return RETURN_SUCCESS; +} + +/** + Retrieve the status of the control bits on a serial device. + + @param Control A pointer to return the current control si= gnals from the serial device. + + @retval RETURN_SUCCESS The control bits were read from the serial= device. + @retval RETURN_UNSUPPORTED The serial device does not support this op= eration. + @retval RETURN_DEVICE_ERROR The serial device is not functioning corre= ctly. + +**/ +RETURN_STATUS +EFIAPI +SerialPortGetControl ( + OUT UINT32 *Control + ) +{ + *Control =3D 0; + return RETURN_SUCCESS; +} + +/** + Sets the baud rate, receive FIFO depth, transmit/receice time out, parit= y, + data bits, and stop bits on a serial device. + + @param BaudRate The requested baud rate. A BaudRate value of 0= will use the + device's default interface speed. + On output, the value actually set. + @param ReveiveFifoDepth The requested depth of the FIFO on the receive= side of the + serial interface. A ReceiveFifoDepth value of = 0 will use + the device's default FIFO depth. + On output, the value actually set. + @param Timeout The requested time out for a single character = in microseconds. + This timeout applies to both the transmit and = receive side of the + interface. A Timeout value of 0 will use the d= evice's default time + out value. + On output, the value actually set. + @param Parity The type of parity to use on this serial devic= e. A Parity value of + DefaultParity will use the device's default pa= rity value. + On output, the value actually set. + @param DataBits The number of data bits to use on the serial d= evice. A DataBits + vaule of 0 will use the device's default data = bit setting. + On output, the value actually set. + @param StopBits The number of stop bits to use on this serial = device. A StopBits + value of DefaultStopBits will use the device's= default number of + stop bits. + On output, the value actually set. + + @retval RETURN_SUCCESS The new attributes were set on the ser= ial device. + @retval RETURN_UNSUPPORTED The serial device does not support thi= s operation. + @retval RETURN_INVALID_PARAMETER One or more of the attributes has an u= nsupported value. + @retval RETURN_DEVICE_ERROR The serial device is not functioning c= orrectly. + +**/ +RETURN_STATUS +EFIAPI +SerialPortSetAttributes ( + IN OUT UINT64 *BaudRate, + IN OUT UINT32 *ReceiveFifoDepth, + IN OUT UINT32 *Timeout, + IN OUT EFI_PARITY_TYPE *Parity, + IN OUT UINT8 *DataBits, + IN OUT EFI_STOP_BITS_TYPE *StopBits + ) +{ + return RETURN_SUCCESS; +} + diff --git a/Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/U500SerialPo= rtLib.uni b/Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/U500SerialPor= tLib.uni new file mode 100644 index 0000000..a1ad72e --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/U500SerialPortLib.u= ni @@ -0,0 +1,22 @@ +// /** @file +// Library instance for SerialIo library class +// +// Library instance for SerialIO library class. +// +// Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
+// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the B= SD License +// which accompanies this distribution. The full text of the license may = be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +// +// **/ + + +#string STR_MODULE_ABSTRACT #language en-US "Library instance = for SerialIO library class" + +#string STR_MODULE_DESCRIPTION #language en-US "Library instance = for SerialIO library class." + -- 2.7.4