[PATCH 08/15] [platforms/devel-riscv]: U500Pkg/Include: Header files of SiFive U500 platform

[PATCH 08/15] [platforms/devel-riscv]: U500Pkg/Include: Header files of SiFive U500 platform

[Chen, Gilbert]

The initial header file commit for SiFive U5-MC Coreplex and U500 Core Local interrupt definitions.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gilbert Chen <gilbert.chen@hpe.com>
---
 .../SiFive/U500Pkg/Include/SiFiveU5MCCoreplex.h    | 57 ++++++++++++++++++++++
 Platform/RiscV/SiFive/U500Pkg/Include/U500Clint.h  | 24 +++++++++
 2 files changed, 81 insertions(+)
 create mode 100644 Platform/RiscV/SiFive/U500Pkg/Include/SiFiveU5MCCoreplex.h
 create mode 100644 Platform/RiscV/SiFive/U500Pkg/Include/U500Clint.h

diff --git a/Platform/RiscV/SiFive/U500Pkg/Include/SiFiveU5MCCoreplex.h b/Platform/RiscV/SiFive/U500Pkg/Include/SiFiveU5MCCoreplex.h
new file mode 100644
index 0000000..c0323a5
--- /dev/null
+++ b/Platform/RiscV/SiFive/U500Pkg/Include/SiFiveU5MCCoreplex.h
@@ -0,0 +1,57 @@
+/** @file
+  SiFive U54 Coreplex library definitions.
+
+  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+  This program and the accompanying materials are licensed and made available under
+  the terms and conditions of the BSD License that accompanies this distribution.
+  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef __SIFIVE_U5MC_COREPLEX_H__
+#define __SIFIVE_U5MC_COREPLEX_H__
+
+#include <PiPei.h>
+
+#include <SmbiosProcessorSpecificData.h>
+#include <ProcessorSpecificDataHob.h>
+
+#define SIFIVE_U5MC_COREPLEX_MC_HART_ID     0
+
+/**
+  Build up U5MC coreplex processor core-specific information.
+
+  @param  UniqueId      U5MC unique ID.
+
+  @return EFI_STATUS
+
+**/
+EFI_STATUS
+EFIAPI
+CreateU5MCCoreplexProcessorSpecificDataHob (
+  IN UINTN UniqueId
+  );
+
+/**
+  Function to build processor related SMBIOS information. RISC-V SMBIOS DXE driver collect
+  this information and build SMBIOS Type4 and Type7 record.
+
+  @param  ProcessorUid        Unique ID of pysical processor which owns this core.
+  @param  SmbiosDataHobPtr    Pointer to receive RISC_V_PROCESSOR_SMBIOS_DATA_HOB. The pointers
+                              maintained in this structure is only valid before memory is discovered.
+                              Access to those pointers after memory is installed will cause unexpected issues.
+
+  @return EFI_SUCCESS     The PEIM initialized successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+CreateU5MCProcessorSmbiosDataHob (
+  IN UINTN     ProcessorUid,
+  OUT RISC_V_PROCESSOR_SMBIOS_DATA_HOB **SmbiosDataHobPtr
+  );
+#endif
diff --git a/Platform/RiscV/SiFive/U500Pkg/Include/U500Clint.h b/Platform/RiscV/SiFive/U500Pkg/Include/U500Clint.h
new file mode 100644
index 0000000..426bf43
--- /dev/null
+++ b/Platform/RiscV/SiFive/U500Pkg/Include/U500Clint.h
@@ -0,0 +1,24 @@
+/** @file
+  RISC-V Timer Architectural definition for U500 platform.
+
+  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution. The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+#ifndef _U500_H_
+#define _U500_H_
+
+#define CLINT_REG_MTIME     0x0200BFF8
+#define CLINT_REG_MTIMECMP0 0x02004000
+#define CLINT_REG_MTIMECMP1 0x02004008
+#define CLINT_REG_MTIMECMP2 0x02004010
+#define CLINT_REG_MTIMECMP3 0x02004018
+#define CLINT_REG_MTIMECMP4 0x02004020
+
+#endif
\ No newline at end of file
--
2.7.4