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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Initial version of RISC-V platform package which provides the common librar= ies, drivers, PCD and etc. for RISC-V platform development. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Gilbert Chen --- Platform/RiscV/Readme.md | 89 +++++++++++++++++++++++++++= ++++ Platform/RiscV/RiscVPlatformPkg.dec | 79 +++++++++++++++++++++++++++ Platform/RiscV/RiscVPlatformPkg.uni | Bin 0 -> 1754 bytes Platform/RiscV/RiscVPlatformPkgExtra.uni | Bin 0 -> 1392 bytes 4 files changed, 168 insertions(+) create mode 100644 Platform/RiscV/Readme.md create mode 100644 Platform/RiscV/RiscVPlatformPkg.dec create mode 100644 Platform/RiscV/RiscVPlatformPkg.uni create mode 100644 Platform/RiscV/RiscVPlatformPkgExtra.uni diff --git a/Platform/RiscV/Readme.md b/Platform/RiscV/Readme.md new file mode 100644 index 0000000..ee2746c --- /dev/null +++ b/Platform/RiscV/Readme.md @@ -0,0 +1,89 @@ +# Introduction + +## EDK2 RISC-V Platform Package +RISC-V platform package provides the generic and common modules for RISC-V= platforms. RISC-V platform package could include RiscPlatformPkg.dec to us= e the common drivers, libraries, definitions, PCDs and etc. for the platfor= m development. + +## EDK2 RISC-V Platforms +RISC-V platform is created and maintained by RISC-V platform vendors. The = directory of RISC-V platform should be created under Platform/RiscV. Vendor= should create the folder under Platform/RiscV and name it using vendor nam= e, under the vendor folder is the platform folder named by platform model n= ame, code name or etc. (e.g. Platform/RiscV/SiFive/U500Pkg) + +## Build EDK2 RISC-V Platforms +RISC-V platform package should provide EDK2 metafiles under RISC-V platfor= m package folder (Platform/RiscV/{Vendor}/{Platform}). Build RISC-V platfor= m package against edk2 and follow the build guidence mentioned in Readme.md= under below link.
+https://github.com/tianocore/edk2-platforms
+ +### Download the sources ### +``` +git clone https://github.com/tianocore/edk2-staging.git +# Checkout RISC-V-V2 branch +git clone https://github.com/tianocore/edk2-platforms.git +# Checkout devel-riscv-v2 branch +git clone https://github.com/tianocore/edk2-non-osi.git +``` + +### Requirements +Build EDK2 RISC-V platform requires GCC RISC-V toolchain. Refer to https:/= /github.com/riscv/riscv-gnu-toolchain for the details. +The commit ID 64879b24 is verified to build RISC-V EDK2 platform and boot = to EFI SHELL successfully. + +### EDK2 project +Currently, the EDK2 RISC-V platform can only build with edk2 project in **= edk2-staging/RISC-V-V2** branch. The build architecture whcih is supported = and verified so far is "RISCV64". The verified RISC-V toolchain is https://= github.com/riscv/riscv-gnu-toolchain @64879b24, toolchain tag is "GCCRISCV"= declared in tools_def.txt
+ +### Linux Build Instructions +You can build the RISC-V platform using below script,
+`build -a RISCV64 -p Platform/{Vendor}/{Platform}/{Platform}.dsc -t GCCRIS= CV` + +Or modify target.txt to set up your build parameters. + +## RISC-V Platform PCD settings +### EDK2 Firmware Volume Settings +EDK2 Firmware volume related PCDs which declared in platform FDF file. + +| **PCD name** |**Usage**| +|----------------|----------| +|PcdRiscVSecFvBase| The base address of SEC Firmware Volume| +|PcdRiscVSecFvSize| The size of SEC Firmware Volume| +|PcdRiscVPeiFvBase| The base address of SEC Firmware Volume| +|PcdRiscVPeiFvSize| The size of SEC Firmware Volume| +|PcdRiscVDxeFvBase| The base address of SEC Firmware Volume| +|PcdRiscVDxeFvSize| The size of SEC Firmware Volume| + +### EDK2 EFI Variable Region Settings +The PCD settings regard to EFI Variable + +| **PCD name** |**Usage**| +|----------------|----------| +|PcdVariableFdBaseAddress| The EFI variable firmware device base address| +|PcdVariableFdSize| The EFI variable firmware device size| +|PcdVariableFdBlockSize| The block size of EFI variable firmware device| +|PcdPlatformFlashNvStorageVariableBase| EFI variable base address within f= irmware device| +|PcdPlatformFlashNvStorageFtwWorkingBase| The base address of EFI variable= fault tolerance worksapce (FTW) within firmware device| +|PcdPlatformFlashNvStorageFtwSpareBase| The base address of EFI variable s= pare FTW within firmware device| + +### RISC-V Physical Memory Protection (PMP) Region Settings +Below PCDs could be set in platform FDF file. + +| **PCD name** |**Usage**| +|----------------|----------| +|PcdFwStartAddress| The starting address of firmware region to protected b= y PMP| +|PcdFwEndAddress| The ending address of firmware region to protected by PM= P| + +### RISC-V Processor HART Settings + +| **PCD name** |**Usage**| +|----------------|----------| +|PcdHartCount| Number of RISC-V HARTs, the value is processor-implementati= on specific| +|PcdBootHartId| The ID of RISC-V HART to execute main fimrware code and bo= ot system to OS| + +### RISC-V OpenSBI Settings + +| **PCD name** |**Usage**| +|----------------|----------| +|PcdScratchRamBase| The base address of OpenSBI scratch buffer for all RIS= C-V HARTs| +|PcdScratchRamSize| The total size of OpenSBI scratch buffer for all RISC-= V HARTs| +|PcdOpenSbiStackSize| The size of initial stack of each RISC-V HART for bo= oting system use OpenSBI| +|PcdTemporaryRamBase| The base address of temporary memory for PEI phase| +|PcdTemporaryRamSize| The temporary memory size for PEI phase| + +## Supported Operating Systems +Only support to boot to EFI Shell so far + +## Known Issues and Limitations +Only RISC-V RV64 is verified diff --git a/Platform/RiscV/RiscVPlatformPkg.dec b/Platform/RiscV/RiscVPlat= formPkg.dec new file mode 100644 index 0000000..7fb7044 --- /dev/null +++ b/Platform/RiscV/RiscVPlatformPkg.dec @@ -0,0 +1,79 @@ +## @file RiscVPlatformPkg.dec +# This Package provides UEFI RISC-V platform modules and libraries. +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+# +# This program and the accompanying materials are licensed and made availa= ble under +# the terms and conditions of the BSD License which accompanies this distr= ibution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +# +## + +[Defines] + DEC_SPECIFICATION =3D 0x00010005 + PACKAGE_NAME =3D RiscPlatformPkg + PACKAGE_UNI_FILE =3D RiscPlatformPkg.uni + PACKAGE_GUID =3D 6A67AF99-4592-40F8-B6BE-62BCA10DA1EC + PACKAGE_VERSION =3D 1.0 + +[Includes] + Include + +[LibraryClasses] + +[LibraryClasses.RISCV32, LibraryClasses.RISCV64] + +[Guids] + gUefiRiscVPlatformPkgTokenSpaceGuid =3D {0x6A67AF99, 0x4592, 0x40F8, { = 0xB6, 0xBE, 0x62, 0xBC, 0xA1, 0x0D, 0xA1, 0xEC}} + +[PcdsFixedAtBuild] + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVSecFvBase|0x0|UINT32|0x00001= 000 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVSecFvSize|0x0|UINT32|0x00001= 001 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVPeiFvBase|0x0|UINT32|0x00001= 002 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVPeiFvSize|0x0|UINT32|0x00001= 003 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvBase|0x0|UINT32|0x00001= 004 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvSize|0x0|UINT32|0x00001= 005 + + +# +# Definition of EFI Variable region +# + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBaseAddress|0|UINT32|0x= 00001010 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdSize|0|UINT32|0x00001011 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBlockSize|0|UINT32|0x00= 001012 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageVariableBas= e|0|UINT32|0x00001013 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwWorkingB= ase|0|UINT32|0x00001014 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwSpareBas= e|0|UINT32|0x00001015 +# +# Firmware region which is protected by PMP. +# + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwBlockSize|0|UINT32|0x00001020 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwStartAddress|0|UINT32|0x00001021 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwEndAddress|0|UINT32|0x00001022 +# +# Definition of RISC-V Hart +# + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount|0|UINT32|0x00001023 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId|0|UINT32|0x00001024 +# +# Definitions for OpenSbi +# + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamBase|0|UINT32|0x00001025 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamSize|0|UINT32|0x00001026 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize|0|UINT32|0x00001= 027 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamBase|0|UINT32|0x00001= 028 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamSize|0|UINT32|0x00001= 029 + +[PcdsPatchableInModule] + +[PcdsFeatureFlag] + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootlogoOnlyEnable|FALSE|BOOLEAN|= 0x00001006 + +[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx] + +[UserExtensions.TianoCore."ExtraFiles"] + RiscVPlatformPkgExtra.uni diff --git a/Platform/RiscV/RiscVPlatformPkg.uni b/Platform/RiscV/RiscVPlat= formPkg.uni new file mode 100644 index 0000000000000000000000000000000000000000..eec4f33da2c96f54580e86ce2d6= 39237194fb708 GIT binary patch literal 1754 zcmc(g+iwy<6vof9iT}fdzNl$IebX2tlx-!gg>bR@)GW}_jZm6pi{c-z{=3DS*LK-)y$ z4B5GyIhSv~bI$PlSHl|S_+IdH_Q9?!vAJE^Q+t9`XMO9~zz*%eKC|mtY!my&I77?X zsV&*Z*d+E7$rRbZGE3RtptE8hvy%J}-5bs>{a7z!RI#LSYa4GpvukvnJ;VQV=3DGXSp zUfCPlXZ;Z$-#yOE>r|*xA1TV?q<9mOmB-p^Tw&@fsKu z3db(NO1OncoECm%HO)P*Su2aNjTvQkhlNhl60;*lK%#u4MBUDmkjWxJEAeZcE~$>n zu0@{P>`!+vIr1V7CX5ennGj2!6g%*w7%TR=3D?HHUzysA2!iB;X=3Dit~^mVg7;ceN4Oj z1THsdjdS~D&V-OW##kKO2Xyj=3D5D z)m^QIRB!~Y9(B~UW5%X^Vy{kfu&R0JJFjIUR*`3VWM|9~a&ZzoR9WcIUlAGu@43rL z6|J$xEWh$vV{ZAqcKciC&N-LYu8-*K9Id`bc80uzSNZ7r=3DzVs=3DE}3Eu(Up#(2CXA> z75yvo2`56X&W-XY;TDm7Dg9L5J8;pXt`xIPzZJX{v-7W2!^bdB`-Iw&%N64sZRhHg}1*@sA@!+rMZPnEnotQ6lP_4ZCzusGQqgPxQdS$L2-u>_Q ZRyT&;tzO;mU!b@4e=3D$-gBSkG}{sRMH5f=3Dae literal 0 HcmV?d00001 diff --git a/Platform/RiscV/RiscVPlatformPkgExtra.uni b/Platform/RiscV/Risc= VPlatformPkgExtra.uni new file mode 100644 index 0000000000000000000000000000000000000000..35bf5b300d57cbeb82bb1c0d28e= fa0bbff795b76 GIT binary patch literal 1392 zcmZvc+iy}q5XR@(#Q$M~FKSv)-!#Su<=3DB$eLV$XCYPgj4L@3SSv=3D#q&_4m!5OR0vi zvokxFZ@-y6e}1>DWr6=3Doe!)K4!ctq>g*~+=3DSamkEo{j9l_U#MWz$P}cAFP*n1v{}d z`h=3DL&eqoto8(D4{`ZYcq^a(rJ5AeO_?84V(RimyYj~m;1^rcBk zZIAsCIqn^2?mjiD%qt~Dos4WkvT>|k);s=3D7ud-q%G`hpUn#eXMOQa%Vb)nDjQ+(#J zb3ET$2Ub4(2mct%susNNnk*T&U!j*AUQv3RNB%=3DzH}cny|~Jnq$1=3DqpH#C6TXW4jy&c> z$n|cMqDs6)V&AGfb@m=3Dy445j_?DE=3D5-bxw#Th(&AY|pCs(f3AQA8~hHusa~ju)2Y) zZJ0V{J>=3DvZWa3`kh`ID?l;;*1zi^s_eOM7f`83F