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charset="us-ascii" Content-Transfer-Encoding: quoted-printable This is the platform-implementation specific library which is executed in e= arly PEI phase for platform initialization. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Gilbert Chen --- .../SiFive/U500Pkg/Universal/Pei/PlatformPei/Fv.c | 55 ++++ .../U500Pkg/Universal/Pei/PlatformPei/MemDetect.c | 80 ++++++ .../U500Pkg/Universal/Pei/PlatformPei/Platform.c | 319 +++++++++++++++++= ++++ .../U500Pkg/Universal/Pei/PlatformPei/Platform.h | 97 +++++++ .../Universal/Pei/PlatformPei/PlatformPei.inf | 82 ++++++ 5 files changed, 633 insertions(+) create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei= /Fv.c create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei= /MemDetect.c create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei= /Platform.c create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei= /Platform.h create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei= /PlatformPei.inf diff --git a/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Fv.c b= /Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Fv.c new file mode 100644 index 0000000..04ac7ac --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Fv.c @@ -0,0 +1,55 @@ +/** @file + Build FV related hobs for platform. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include "PiPei.h" +#include "Platform.h" +#include +#include +#include +#include + +/** + Publish PEI & DXE (Decompressed) Memory based FVs to let PEI + and DXE know about them. + + @retval EFI_SUCCESS Platform PEI FVs were initialized successfully. + +**/ +EFI_STATUS +PeiFvInitialization ( + VOID + ) +{ + DEBUG ((EFI_D_INFO, "Platform PEI Firmware Volume Initialization\n")); + // + // Let DXE know about the DXE FV + // + BuildFvHob (PcdGet32 (PcdRiscVDxeFvBase), PcdGet32 (PcdRiscVDxeFvSize)); + DEBUG ((EFI_D_INFO, "Platform builds DXE FV at %x, size %x.\n", PcdGet32= (PcdRiscVDxeFvBase), PcdGet32 (PcdRiscVDxeFvSize))); + + // + // Let PEI know about the DXE FV so it can find the DXE Core + // + PeiServicesInstallFvInfoPpi ( + NULL, + (VOID *)(UINTN) PcdGet32 (PcdRiscVDxeFvBase), + PcdGet32 (PcdRiscVDxeFvSize), + NULL, + NULL + ); + + return EFI_SUCCESS; +} diff --git a/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/MemDet= ect.c b/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/MemDetect.c new file mode 100644 index 0000000..3c047f1 --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/MemDetect.c @@ -0,0 +1,80 @@ +/**@file + Memory Detection for Virtual Machines. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +Module Name: + + MemDetect.c + +**/ + +// +// The package level header files this module uses +// +#include + +// +// The Library classes this module consumes +// +#include +#include +#include +#include +#include +#include +#include + +#include "Platform.h" + + +/** + Publish PEI core memory + + @return EFI_SUCCESS The PEIM initialized successfully. + +**/ +EFI_STATUS +PublishPeiMemory ( + VOID + ) +{ + EFI_STATUS Status; + EFI_PHYSICAL_ADDRESS MemoryBase; + UINT64 MemorySize; + + MemoryBase =3D 0x80000000UL + 0x1000000UL; + MemorySize =3D 0x40000000UL - 0x1000000UL; //1GB - 16MB + + DEBUG((EFI_D_INFO, "%a: MemoryBase:0x%x MemorySize:%d\n", __FUNCTION__, = MemoryBase, MemorySize)); + + // + // Publish this memory to the PEI Core + // + Status =3D PublishSystemMemory(MemoryBase, MemorySize); + ASSERT_EFI_ERROR (Status); + + return Status; +} + +/** + Publish system RAM and reserve memory regions + +**/ +VOID +InitializeRamRegions ( + VOID + ) +{ + AddMemoryRangeHob(0x81000000UL, 0x81000000UL + 0x3F000000UL); + +} diff --git a/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Platfo= rm.c b/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Platform.c new file mode 100644 index 0000000..543bbf1 --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Platform.c @@ -0,0 +1,319 @@ +/**@file + Platform PEI driver + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
+ Copyright (c) 2011, Andrei Warkentin + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +// +// The package level header files this module uses +// +#include + +// +// The Library classes this module consumes +// +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "Platform.h" + +EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] =3D { + { EfiACPIMemoryNVS, 0x004 }, + { EfiACPIReclaimMemory, 0x008 }, + { EfiReservedMemoryType, 0x004 }, + { EfiRuntimeServicesData, 0x024 }, + { EfiRuntimeServicesCode, 0x030 }, + { EfiBootServicesCode, 0x180 }, + { EfiBootServicesData, 0xF00 }, + { EfiMaxMemoryType, 0x000 } +}; + + +EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] =3D { + { + EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST, + &gEfiPeiMasterBootModePpiGuid, + NULL + } +}; + +EFI_BOOT_MODE mBootMode =3D BOOT_WITH_FULL_CONFIGURATION; + +BOOLEAN mS3Supported =3D FALSE; + + +VOID +AddIoMemoryBaseSizeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + UINT64 MemorySize + ) +{ + BuildResourceDescriptorHob ( + EFI_RESOURCE_MEMORY_MAPPED_IO, + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED, + MemoryBase, + MemorySize + ); +} + +VOID +AddReservedMemoryBaseSizeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + UINT64 MemorySize + ) +{ + BuildResourceDescriptorHob ( + EFI_RESOURCE_MEMORY_RESERVED, + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED, + MemoryBase, + MemorySize + ); +} + +VOID +AddIoMemoryRangeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + EFI_PHYSICAL_ADDRESS MemoryLimit + ) +{ + AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase)); +} + + +VOID +AddMemoryBaseSizeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + UINT64 MemorySize + ) +{ + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED, + MemoryBase, + MemorySize + ); +} + + +VOID +AddMemoryRangeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + EFI_PHYSICAL_ADDRESS MemoryLimit + ) +{ + AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase)); +} + + +VOID +AddUntestedMemoryBaseSizeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + UINT64 MemorySize + ) +{ + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE, + MemoryBase, + MemorySize + ); +} + +VOID +AddUntestedMemoryRangeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + EFI_PHYSICAL_ADDRESS MemoryLimit + ) +{ + AddUntestedMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryB= ase)); +} + +VOID +AddPciResource ( + VOID + ) +{ + // + // Platform-specific + // +} + +VOID +MemMapInitialization ( + VOID + ) +{ + // + // Create Memory Type Information HOB + // + BuildGuidDataHob ( + &gEfiMemoryTypeInformationGuid, + mDefaultMemoryTypeInformation, + sizeof(mDefaultMemoryTypeInformation) + ); + + // + // Add PCI IO Port space available for PCI resource allocations. + // + AddPciResource (); +} + +VOID +MiscInitialization ( + VOID + ) +{ + // + // Build the CPU HOB with guest RAM size dependent address width and 16-= bits + // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed dur= ing + // S3 resume as well, so we build it unconditionally.) + // + BuildCpuHob (32, 32); +} + +/** + Check if system retunrs from S3. + + @return BOOLEAN TRUE, system returned from S3 + FALSE, system is not returned from S3 + +**/ +BOOLEAN +CheckResumeFromS3 ( + VOID + ) +{ + // + //Platform implementation-specific + // + return FALSE; +} + + +VOID +BootModeInitialization ( + VOID + ) +{ + EFI_STATUS Status; + + if (CheckResumeFromS3 () =3D=3D TRUE) { + DEBUG ((EFI_D_INFO, "This is wake from S3\n")); + } else { + DEBUG ((EFI_D_INFO, "This is normal boot\n")); + } + Status =3D PeiServicesSetBootMode (mBootMode); + ASSERT_EFI_ERROR (Status); + + Status =3D PeiServicesInstallPpi (mPpiBootMode); + ASSERT_EFI_ERROR (Status); +} + +/** + Build processor information for U54 Coreplex processor. + + @return EFI_SUCCESS Status. + +**/ +EFI_STATUS +BuildCoreInformationHob ( + VOID +) +{ + EFI_STATUS Status; + RISC_V_PROCESSOR_SMBIOS_DATA_HOB *SmbiosHobPtr; + + Status =3D CreateU5MCCoreplexProcessorSpecificDataHob (0); + if (EFI_ERROR (Status)) { + ASSERT(FALSE); + } + Status =3D CreateU5MCProcessorSmbiosDataHob(0, &SmbiosHobPtr); + if (EFI_ERROR (Status)) { + ASSERT(FALSE); + } + + DEBUG ((EFI_D_INFO, "U5 MC Coreplex SMBIOS DATA HOB at address 0x%x\n", = SmbiosHobPtr)); + + return EFI_SUCCESS; +} + +/** + Perform Platform PEI initialization. + + @param FileHandle Handle of the file being invoked. + @param PeiServices Describes the list of possible PEI Services. + + @return EFI_SUCCESS The PEIM initialized successfully. + +**/ +EFI_STATUS +EFIAPI +InitializePlatform ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + + DEBUG ((EFI_D_INFO, "Platform PEIM Loaded\n")); + + BootModeInitialization (); + DEBUG ((EFI_D_INFO, "Platform BOOT mode initiated.\n")); + PublishPeiMemory (); + DEBUG ((EFI_D_INFO, "PEI memory published.\n")); + InitializeRamRegions (); + DEBUG ((EFI_D_INFO, "Platform RAM regions initiated.\n")); + + if (mBootMode !=3D BOOT_ON_S3_RESUME) { + PeiFvInitialization (); + MemMapInitialization (); + } + + MiscInitialization (); + Status =3D BuildCoreInformationHob (); + if (EFI_ERROR (Status)) { + DEBUG ((EFI_D_ERROR, "Fail to build processor informstion HOB.\n")); + ASSERT(FALSE); + } + return EFI_SUCCESS; +} diff --git a/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Platfo= rm.h b/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Platform.h new file mode 100644 index 0000000..0b2ca27 --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Platform.h @@ -0,0 +1,97 @@ +/** @file + Platform PEI module include file. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#ifndef _PLATFORM_PEI_H_INCLUDED_ +#define _PLATFORM_PEI_H_INCLUDED_ + +VOID +AddIoMemoryBaseSizeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + UINT64 MemorySize + ); + +VOID +AddIoMemoryRangeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + EFI_PHYSICAL_ADDRESS MemoryLimit + ); + +VOID +AddMemoryBaseSizeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + UINT64 MemorySize + ); + +VOID +AddMemoryRangeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + EFI_PHYSICAL_ADDRESS MemoryLimit + ); + +VOID +AddUntestedMemoryBaseSizeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + UINT64 MemorySize + ); + +VOID +AddReservedMemoryBaseSizeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + UINT64 MemorySize + ); + +VOID +AddUntestedMemoryRangeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + EFI_PHYSICAL_ADDRESS MemoryLimit + ); + +VOID +AddressWidthInitialization ( + VOID + ); + +EFI_STATUS +PublishPeiMemory ( + VOID + ); + +UINT32 +GetSystemMemorySizeBelow4gb ( + VOID + ); + +VOID +InitializeRamRegions ( + VOID + ); + +EFI_STATUS +PeiFvInitialization ( + VOID + ); + +EFI_STATUS +InitializeXen ( + VOID + ); + +extern EFI_BOOT_MODE mBootMode; + +extern BOOLEAN mS3Supported; + +extern UINT8 mPhysMemAddressWidth; + +#endif // _PLATFORM_PEI_H_INCLUDED_ diff --git a/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Platfo= rmPei.inf b/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Platfor= mPei.inf new file mode 100644 index 0000000..0e77142 --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/PlatformPei.i= nf @@ -0,0 +1,82 @@ +## @file +# Platform PEI driver +# +# This module provides platform specific function to detect boot mode. +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may b= e found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PlatformPei + FILE_GUID =3D 222c386d-5abc-4fb4-b124-fbb82488acf4 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D InitializePlatform + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC RISCV64 +# + +[Sources] + Fv.c + MemDetect.c + Platform.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + RiscVPkg/RiscVPkg.dec + Platform/RiscV/RiscVPlatformPkg.dec + Silicon/SiFive/SiFive.dec + Platform/RiscV/SiFive/U500Pkg/U500.dec + +[Guids] + gEfiMemoryTypeInformationGuid + gUefiRiscVPlatformU500PkgTokenSpaceGuid + +[LibraryClasses] + DebugLib + HobLib + IoLib + PciLib + PeiResourcePublicationLib + PeiServicesLib + PeiServicesTablePointerLib + PeimEntryPoint + PcdLib + SiliconSiFiveU5MCCoreplexInfoLib + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress + gEfiMdeModulePkgTokenSpaceGuid.PcdVariableStoreSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved + gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvBase + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvSize + + gUefiRiscVPlatformU500PkgTokenSpaceGuid.PcdNumberofU5Cores + gUefiRiscVPlatformU500PkgTokenSpaceGuid.PcdE5MCSupported + + +[Ppis] + gEfiPeiMasterBootModePpiGuid + +[Depex] + TRUE + -- 2.7.4