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Thu, 5 Sep 2019 01:24:44 +0000 From: "Gilbert Chen" To: "devel@edk2.groups.io" Subject: [PATCH 06/15] [platforms/devel-riscv-v2]: RiscV/Universal: Initial version of common RISC-V SEC module Thread-Topic: [PATCH 06/15] [platforms/devel-riscv-v2]: RiscV/Universal: Initial version of common RISC-V SEC module Thread-Index: AdVjiLD0QGq7kDrcRTiKcJPAq6uAdA== Date: Thu, 5 Sep 2019 01:24:44 +0000 Message-ID: Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [16.242.247.133] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: cb58a087-0257-414c-5b78-08d7319fd54e x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600166)(711020)(4605104)(1401327)(4618075)(2017052603328)(7193020);SRVR:TU4PR8401MB1294; x-ms-traffictypediagnostic: TU4PR8401MB1294: x-ms-exchange-purlcount: 1 x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:3631; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Common RISC-V SEC module for RISC-V platforms. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Gilbert Chen --- Platform/RiscV/Universal/Sec/Riscv64/SecEntry.s | 439 ++++++++++++++++++++ Platform/RiscV/Universal/Sec/SecMain.c | 529 ++++++++++++++++++++= ++++ Platform/RiscV/Universal/Sec/SecMain.h | 56 +++ Platform/RiscV/Universal/Sec/SecMain.inf | 81 ++++ 4 files changed, 1105 insertions(+) create mode 100644 Platform/RiscV/Universal/Sec/Riscv64/SecEntry.s create mode 100644 Platform/RiscV/Universal/Sec/SecMain.c create mode 100644 Platform/RiscV/Universal/Sec/SecMain.h create mode 100644 Platform/RiscV/Universal/Sec/SecMain.inf diff --git a/Platform/RiscV/Universal/Sec/Riscv64/SecEntry.s b/Platform/Ris= cV/Universal/Sec/Riscv64/SecEntry.s new file mode 100644 index 0000000..a5ca481 --- /dev/null +++ b/Platform/RiscV/Universal/Sec/Riscv64/SecEntry.s @@ -0,0 +1,439 @@ +/* + * Copyright (c) 2019 , Hewlett Packard Enterprise Development LP. All rig= hts reserved. + * + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2019 Western Digital Corporation or its affiliates. + * + * Authors: + * Anup Patel + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +.text +.align 3 +.global ASM_PFX(_ModuleEntryPoint) +ASM_PFX(_ModuleEntryPoint): + /* + * Jump to warm-boot if this is not the selected core booting, + */ + csrr a6, CSR_MHARTID + li a5, FixedPcdGet32 (PcdBootHartId) + bne a6, a5, _wait_for_boot_hart + + // light LED on + li a5, 0x54002000 + li a4, 0xff + sw a4, 0x08(a5) + li a4, 0x11 + sw a4, 0x0c(a5) + + lira, 0 + call_reset_regs + + /* Preload HART details + * s7 -> HART Count + * s8 -> HART Stack Size + */ + li s7, FixedPcdGet32 (PcdHartCount) + li s8, FixedPcdGet32 (PcdOpenSbiStackSize) + + /* Setup scratch space for all the HARTs*/ + li tp, FixedPcdGet32 (PcdScratchRamBase) + mula5, s7, s8 + addtp, tp, a5 + /* Keep a copy of tp */ + addt3, tp, zero + /* Counter */ + lit2, 1 + /* hartid 0 is mandated by ISA */ + lit1, 0 +_scratch_init: + addtp, t3, zero + mula5, s8, t1 + subtp, tp, a5 + lia5, SBI_SCRATCH_SIZE + subtp, tp, a5 + + /* Initialize scratch space */ + li a4, FixedPcdGet32 (PcdFwStartAddress) + li a5, FixedPcdGet32 (PcdFwEndAddress) + suba5, a5, a4 + sda4, SBI_SCRATCH_FW_START_OFFSET(tp) + sda5, SBI_SCRATCH_FW_SIZE_OFFSET(tp) + /* Note: fw_next_arg1() uses a0, a1, and ra */ + callfw_next_arg1 + sda0, SBI_SCRATCH_NEXT_ARG1_OFFSET(tp) + /* Note: fw_next_addr() uses a0, a1, and ra */ + callfw_next_addr + sda0, SBI_SCRATCH_NEXT_ADDR_OFFSET(tp) + lia4, PRV_S + sda4, SBI_SCRATCH_NEXT_MODE_OFFSET(tp) + laa4, _start_warm + sda4, SBI_SCRATCH_WARMBOOT_ADDR_OFFSET(tp) + laa4, platform + sda4, SBI_SCRATCH_PLATFORM_ADDR_OFFSET(tp) + laa4, _hartid_to_scratch + sda4, SBI_SCRATCH_HARTID_TO_SCRATCH_OFFSET(tp) + sdzero, SBI_SCRATCH_TMP0_OFFSET(tp) +#ifdef FW_OPTIONS + lia4, FW_OPTIONS + sda4, SBI_SCRATCH_OPTIONS_OFFSET(tp) +#else + sdzero, SBI_SCRATCH_OPTIONS_OFFSET(tp) +#endif + addt1, t1, t2 + bltt1, s7, _scratch_init + + /* Fill-out temporary memory with 55aa*/ + lia4, FixedPcdGet32 (PcdTemporaryRamBase) + lia5, FixedPcdGet32 (PcdTemporaryRamSize) + add a5, a4, a5 +1: + li a3, 0x5AA55AA55AA55AA5 + sda3, (a4) + adda4, a4, __SIZEOF_POINTER__ + blta4, a5, 1b + + /* Update boot hart flag */ + laa4, _boot_hart_done + lia5, 1 + sda5, (a4) + + /* Wait for boot hart */ +_wait_for_boot_hart: + laa4, _boot_hart_done + lda5, (a4) + /* Reduce the bus traffic so that boot hart may proceed faster */ + nop + nop + nop + beqza5, _wait_for_boot_hart + +_start_warm: + lira, 0 + call_reset_regs + + /* Disable and clear all interrupts */ + csrwCSR_MIE, zero + csrwCSR_MIP, zero + + li s7, FixedPcdGet32 (PcdHartCount) + li s8, FixedPcdGet32 (PcdOpenSbiStackSize) + + /* HART ID should be within expected limit */ + csrrs6, CSR_MHARTID + bges6, s7, _start_hang + + /* find the scratch space for this hart */ + litp, FixedPcdGet32 (PcdScratchRamBase) + mula5, s7, s8 + addtp, tp, a5 + mula5, s8, s6 + subtp, tp, a5 + lia5, SBI_SCRATCH_SIZE + subtp, tp, a5 + + /* update the mscratch */ + csrwCSR_MSCRATCH, tp + + /*make room for Hart specific Firmware Context*/ + lia5, FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE + subtp, tp, a5 + + /* Setup stack */ + add sp, tp, zero + + /* Setup stack for the Hart executing EFI to top of temporary ram*/ + csrr a6, CSR_MHARTID + li a5, FixedPcdGet32 (PcdBootHartId) + bne a6, a5, 1f + + li a4, FixedPcdGet32(PcdTemporaryRamBase) + li a5, FixedPcdGet32(PcdTemporaryRamSize) + addsp, a4, a5 + 1: + + /* Setup trap handler */ + laa4, _trap_handler + csrwCSR_MTVEC, a4 + /* Make sure that mtvec is updated */ + 1: + csrra5, CSR_MTVEC + bnea4, a5, 1b + + /* Call library constructors before jup to SEC core */ + call ProcessLibraryConstructorList + + /* jump to SEC Core C */ + csrr a0, CSR_MHARTID + csrr a1, CSR_MSCRATCH + call SecCoreStartUpWithStack + + /* We do not expect to reach here hence just hang */ + j_start_hang + + .align 3 + .section .data, "aw" +_boot_hart_done: + RISCV_PTR0 + + .align 3 + .section .entry, "ax", %progbits + .globl _hartid_to_scratch +_hartid_to_scratch: + addsp, sp, -(3 * __SIZEOF_POINTER__) + sds0, (sp) + sds1, (__SIZEOF_POINTER__)(sp) + sds2, (__SIZEOF_POINTER__ * 2)(sp) + /* + * a0 -> HART ID (passed by caller) + * s0 -> HART Stack Size + * s1 -> HART Stack End + * s2 -> Temporary + */ + las2, platform +#if __riscv_xlen =3D=3D 64 + lwus0, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(s2) + lwus2, SBI_PLATFORM_HART_COUNT_OFFSET(s2) +#else + lws0, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(s2) + lws2, SBI_PLATFORM_HART_COUNT_OFFSET(s2) +#endif + muls2, s2, s0 + lis1, FixedPcdGet32 (PcdScratchRamBase) + adds1, s1, s2 + muls2, s0, a0 + subs1, s1, s2 + lis2, SBI_SCRATCH_SIZE + suba0, s1, s2 + lds0, (sp) + lds1, (__SIZEOF_POINTER__)(sp) + lds2, (__SIZEOF_POINTER__ * 2)(sp) + addsp, sp, (3 * __SIZEOF_POINTER__) + ret + + .align 3 + .section .entry, "ax", %progbits + .globl _start_hang +_start_hang: + wfi + j_start_hang + + .align 3 + .section .entry, "ax", %progbits + .globl _trap_handler +_trap_handler: + /* Swap TP and MSCRATCH */ + csrrwtp, CSR_MSCRATCH, tp + + /* Save T0 in scratch space */ + sdt0, SBI_SCRATCH_TMP0_OFFSET(tp) + + /* Check which mode we came from */ + csrrt0, CSR_MSTATUS + srlt0, t0, MSTATUS_MPP_SHIFT + andt0, t0, PRV_M + xorit0, t0, PRV_M + beqt0, zero, _trap_handler_m_mode + + /* We came from S-mode or U-mode */ +_trap_handler_s_mode: + /* Set T0 to original SP */ + addt0, sp, zero + + /* Setup exception stack */ + addsp, tp, -(SBI_TRAP_REGS_SIZE) + + /* Jump to code common for all modes */ + j_trap_handler_all_mode + + /* We came from M-mode */ +_trap_handler_m_mode: + /* Set T0 to original SP */ + addt0, sp, zero + + /* Re-use current SP as exception stack */ + addsp, sp, -(SBI_TRAP_REGS_SIZE) + +_trap_handler_all_mode: + /* Save original SP (from T0) on stack */ + sdt0, SBI_TRAP_REGS_OFFSET(sp)(sp) + + /* Restore T0 from scratch space */ + ldt0, SBI_SCRATCH_TMP0_OFFSET(tp) + + /* Save T0 on stack */ + sdt0, SBI_TRAP_REGS_OFFSET(t0)(sp) + + /* Swap TP and MSCRATCH */ + csrrwtp, CSR_MSCRATCH, tp + + /* Save MEPC and MSTATUS CSRs */ + csrrt0, CSR_MEPC + sdt0, SBI_TRAP_REGS_OFFSET(mepc)(sp) + csrrt0, CSR_MSTATUS + sdt0, SBI_TRAP_REGS_OFFSET(mstatus)(sp) + + /* Save all general regisers except SP and T0 */ + sdzero, SBI_TRAP_REGS_OFFSET(zero)(sp) + sdra, SBI_TRAP_REGS_OFFSET(ra)(sp) + sdgp, SBI_TRAP_REGS_OFFSET(gp)(sp) + sdtp, SBI_TRAP_REGS_OFFSET(tp)(sp) + sdt1, SBI_TRAP_REGS_OFFSET(t1)(sp) + sdt2, SBI_TRAP_REGS_OFFSET(t2)(sp) + sds0, SBI_TRAP_REGS_OFFSET(s0)(sp) + sds1, SBI_TRAP_REGS_OFFSET(s1)(sp) + sda0, SBI_TRAP_REGS_OFFSET(a0)(sp) + sda1, SBI_TRAP_REGS_OFFSET(a1)(sp) + sda2, SBI_TRAP_REGS_OFFSET(a2)(sp) + sda3, SBI_TRAP_REGS_OFFSET(a3)(sp) + sda4, SBI_TRAP_REGS_OFFSET(a4)(sp) + sda5, SBI_TRAP_REGS_OFFSET(a5)(sp) + sda6, SBI_TRAP_REGS_OFFSET(a6)(sp) + sda7, SBI_TRAP_REGS_OFFSET(a7)(sp) + sds2, SBI_TRAP_REGS_OFFSET(s2)(sp) + sds3, SBI_TRAP_REGS_OFFSET(s3)(sp) + sds4, SBI_TRAP_REGS_OFFSET(s4)(sp) + sds5, SBI_TRAP_REGS_OFFSET(s5)(sp) + sds6, SBI_TRAP_REGS_OFFSET(s6)(sp) + sds7, SBI_TRAP_REGS_OFFSET(s7)(sp) + sds8, SBI_TRAP_REGS_OFFSET(s8)(sp) + sds9, SBI_TRAP_REGS_OFFSET(s9)(sp) + sds10, SBI_TRAP_REGS_OFFSET(s10)(sp) + sds11, SBI_TRAP_REGS_OFFSET(s11)(sp) + sdt3, SBI_TRAP_REGS_OFFSET(t3)(sp) + sdt4, SBI_TRAP_REGS_OFFSET(t4)(sp) + sdt5, SBI_TRAP_REGS_OFFSET(t5)(sp) + sdt6, SBI_TRAP_REGS_OFFSET(t6)(sp) + + /* Call C routine */ + adda0, sp, zero + csrra1, CSR_MSCRATCH + callsbi_trap_handler + + /* Restore all general regisers except SP and T0 */ + ldra, SBI_TRAP_REGS_OFFSET(ra)(sp) + ldgp, SBI_TRAP_REGS_OFFSET(gp)(sp) + ldtp, SBI_TRAP_REGS_OFFSET(tp)(sp) + ldt1, SBI_TRAP_REGS_OFFSET(t1)(sp) + ldt2, SBI_TRAP_REGS_OFFSET(t2)(sp) + lds0, SBI_TRAP_REGS_OFFSET(s0)(sp) + lds1, SBI_TRAP_REGS_OFFSET(s1)(sp) + lda0, SBI_TRAP_REGS_OFFSET(a0)(sp) + lda1, SBI_TRAP_REGS_OFFSET(a1)(sp) + lda2, SBI_TRAP_REGS_OFFSET(a2)(sp) + lda3, SBI_TRAP_REGS_OFFSET(a3)(sp) + lda4, SBI_TRAP_REGS_OFFSET(a4)(sp) + lda5, SBI_TRAP_REGS_OFFSET(a5)(sp) + lda6, SBI_TRAP_REGS_OFFSET(a6)(sp) + lda7, SBI_TRAP_REGS_OFFSET(a7)(sp) + lds2, SBI_TRAP_REGS_OFFSET(s2)(sp) + lds3, SBI_TRAP_REGS_OFFSET(s3)(sp) + lds4, SBI_TRAP_REGS_OFFSET(s4)(sp) + lds5, SBI_TRAP_REGS_OFFSET(s5)(sp) + lds6, SBI_TRAP_REGS_OFFSET(s6)(sp) + lds7, SBI_TRAP_REGS_OFFSET(s7)(sp) + lds8, SBI_TRAP_REGS_OFFSET(s8)(sp) + lds9, SBI_TRAP_REGS_OFFSET(s9)(sp) + lds10, SBI_TRAP_REGS_OFFSET(s10)(sp) + lds11, SBI_TRAP_REGS_OFFSET(s11)(sp) + ldt3, SBI_TRAP_REGS_OFFSET(t3)(sp) + ldt4, SBI_TRAP_REGS_OFFSET(t4)(sp) + ldt5, SBI_TRAP_REGS_OFFSET(t5)(sp) + ldt6, SBI_TRAP_REGS_OFFSET(t6)(sp) + + /* Restore MEPC and MSTATUS CSRs */ + ldt0, SBI_TRAP_REGS_OFFSET(mepc)(sp) + csrwCSR_MEPC, t0 + ldt0, SBI_TRAP_REGS_OFFSET(mstatus)(sp) + csrwCSR_MSTATUS, t0 + + /* Restore T0 */ + ldt0, SBI_TRAP_REGS_OFFSET(t0)(sp) + + /* Restore SP */ + ldsp, SBI_TRAP_REGS_OFFSET(sp)(sp) + + mret + + .align 3 + .section .entry, "ax", %progbits + .globl _reset_regs +_reset_regs: + + /* flush the instruction cache */ + fence.i + /* Reset all registers except ra, a0,a1 */ + li sp, 0 + li gp, 0 + li tp, 0 + li t0, 0 + li t1, 0 + li t2, 0 + li s0, 0 + li s1, 0 + li a2, 0 + li a3, 0 + li a4, 0 + li a5, 0 + li a6, 0 + li a7, 0 + li s2, 0 + li s3, 0 + li s4, 0 + li s5, 0 + li s6, 0 + li s7, 0 + li s8, 0 + li s9, 0 + li s10, 0 + li s11, 0 + li t3, 0 + li t4, 0 + li t5, 0 + li t6, 0 + csrw CSR_MSCRATCH, 0 + ret + + .align 3 + .section .entry, "ax", %progbits + .global fw_prev_arg1 +fw_prev_arg1: + /* We return previous arg1 in 'a0' */ + adda0, zero, zero + ret + + .align 3 + .section .entry, "ax", %progbits + .global fw_next_arg1 +fw_next_arg1: + /* We return next arg1 in 'a0' */ + lia0, FixedPcdGet32(PcdRiscVPeiFvBase) + ret + + .align 3 + .section .entry, "ax", %progbits + .global fw_next_addr +fw_next_addr: + /* We return next address in 'a0' */ + laa0, _jump_addr + lda0, (a0) + ret + + .align 3 +.section .entry, "ax", %progbits +_jump_addr: +RISCV_PTR SecCoreStartUpWithStack + diff --git a/Platform/RiscV/Universal/Sec/SecMain.c b/Platform/RiscV/Univer= sal/Sec/SecMain.c new file mode 100644 index 0000000..3dc7bc7 --- /dev/null +++ b/Platform/RiscV/Universal/Sec/SecMain.c @@ -0,0 +1,529 @@ +/** @file + RISC-V SEC phase module. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may be= found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +**/ + +#include "SecMain.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include + +int HartsIn =3D 0; + +EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI mTemporaryRamSupportPpi =3D { + TemporaryRamMigration +}; + +EFI_PEI_TEMPORARY_RAM_DONE_PPI mTemporaryRamDonePpi =3D { + TemporaryRamDone +}; + +EFI_PEI_PPI_DESCRIPTOR mPrivateDispatchTable[] =3D { + { + EFI_PEI_PPI_DESCRIPTOR_PPI, + &gEfiTemporaryRamSupportPpiGuid, + &mTemporaryRamSupportPpi + }, + { + (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gEfiTemporaryRamDonePpiGuid, + &mTemporaryRamDonePpi + }, +}; + +/** + Locates a section within a series of sections + with the specified section type. + + The Instance parameter indicates which instance of the section + type to return. (0 is first instance, 1 is second...) + + @param[in] Sections The sections to search + @param[in] SizeOfSections Total size of all sections + @param[in] SectionType The section type to locate + @param[in] Instance The section instance number + @param[out] FoundSection The FFS section if found + + @retval EFI_SUCCESS The file and section was found + @retval EFI_NOT_FOUND The file and section was not found + @retval EFI_VOLUME_CORRUPTED The firmware volume was corrupted + +**/ +EFI_STATUS +FindFfsSectionInstance ( + IN VOID *Sections, + IN UINTN SizeOfSections, + IN EFI_SECTION_TYPE SectionType, + IN UINTN Instance, + OUT EFI_COMMON_SECTION_HEADER **FoundSection + ) +{ + EFI_PHYSICAL_ADDRESS CurrentAddress; + UINT32 Size; + EFI_PHYSICAL_ADDRESS EndOfSections; + EFI_COMMON_SECTION_HEADER *Section; + EFI_PHYSICAL_ADDRESS EndOfSection; + + // + // Loop through the FFS file sections within the PEI Core FFS file + // + EndOfSection =3D (EFI_PHYSICAL_ADDRESS)(UINTN) Sections; + EndOfSections =3D EndOfSection + SizeOfSections; + for (;;) { + if (EndOfSection =3D=3D EndOfSections) { + break; + } + CurrentAddress =3D (EndOfSection + 3) & ~(3ULL); + if (CurrentAddress >=3D EndOfSections) { + return EFI_VOLUME_CORRUPTED; + } + + Section =3D (EFI_COMMON_SECTION_HEADER*)(UINTN) CurrentAddress; + + Size =3D SECTION_SIZE (Section); + if (Size < sizeof (*Section)) { + return EFI_VOLUME_CORRUPTED; + } + + EndOfSection =3D CurrentAddress + Size; + if (EndOfSection > EndOfSections) { + return EFI_VOLUME_CORRUPTED; + } + + // + // Look for the requested section type + // + if (Section->Type =3D=3D SectionType) { + if (Instance =3D=3D 0) { + *FoundSection =3D Section; + return EFI_SUCCESS; + } else { + Instance--; + } + } + } + + return EFI_NOT_FOUND; +} + +/** + Locates a section within a series of sections + with the specified section type. + + @param[in] Sections The sections to search + @param[in] SizeOfSections Total size of all sections + @param[in] SectionType The section type to locate + @param[out] FoundSection The FFS section if found + + @retval EFI_SUCCESS The file and section was found + @retval EFI_NOT_FOUND The file and section was not found + @retval EFI_VOLUME_CORRUPTED The firmware volume was corrupted + +**/ +EFI_STATUS +FindFfsSectionInSections ( + IN VOID *Sections, + IN UINTN SizeOfSections, + IN EFI_SECTION_TYPE SectionType, + OUT EFI_COMMON_SECTION_HEADER **FoundSection + ) +{ + return FindFfsSectionInstance ( + Sections, + SizeOfSections, + SectionType, + 0, + FoundSection + ); +} + +/** + Locates a FFS file with the specified file type and a section + within that file with the specified section type. + + @param[in] Fv The firmware volume to search + @param[in] FileType The file type to locate + @param[in] SectionType The section type to locate + @param[out] FoundSection The FFS section if found + + @retval EFI_SUCCESS The file and section was found + @retval EFI_NOT_FOUND The file and section was not found + @retval EFI_VOLUME_CORRUPTED The firmware volume was corrupted + +**/ +EFI_STATUS +FindFfsFileAndSection ( + IN EFI_FIRMWARE_VOLUME_HEADER *Fv, + IN EFI_FV_FILETYPE FileType, + IN EFI_SECTION_TYPE SectionType, + OUT EFI_COMMON_SECTION_HEADER **FoundSection + ) +{ + EFI_STATUS Status; + EFI_PHYSICAL_ADDRESS CurrentAddress; + EFI_PHYSICAL_ADDRESS EndOfFirmwareVolume; + EFI_FFS_FILE_HEADER *File; + UINT32 Size; + EFI_PHYSICAL_ADDRESS EndOfFile; + + if (Fv->Signature !=3D EFI_FVH_SIGNATURE) { + DEBUG ((EFI_D_ERROR, "FV at %p does not have FV header signature\n", F= v)); + return EFI_VOLUME_CORRUPTED; + } + + CurrentAddress =3D (EFI_PHYSICAL_ADDRESS)(UINTN) Fv; + EndOfFirmwareVolume =3D CurrentAddress + Fv->FvLength; + + // + // Loop through the FFS files in the Boot Firmware Volume + // + for (EndOfFile =3D CurrentAddress + Fv->HeaderLength; ; ) { + + CurrentAddress =3D (EndOfFile + 7) & ~(7ULL); + if (CurrentAddress > EndOfFirmwareVolume) { + return EFI_VOLUME_CORRUPTED; + } + + File =3D (EFI_FFS_FILE_HEADER*)(UINTN) CurrentAddress; + Size =3D *(UINT32*) File->Size & 0xffffff; + if (Size < (sizeof (*File) + sizeof (EFI_COMMON_SECTION_HEADER))) { + return EFI_VOLUME_CORRUPTED; + } + + EndOfFile =3D CurrentAddress + Size; + if (EndOfFile > EndOfFirmwareVolume) { + return EFI_VOLUME_CORRUPTED; + } + + // + // Look for the request file type + // + if (File->Type !=3D FileType) { + continue; + } + + Status =3D FindFfsSectionInSections ( + (VOID*) (File + 1), + (UINTN) EndOfFile - (UINTN) (File + 1), + SectionType, + FoundSection + ); + if (!EFI_ERROR (Status) || (Status =3D=3D EFI_VOLUME_CORRUPTED)) { + return Status; + } + } +} + +/** + Locates the PEI Core entry point address + + @param[in] Fv The firmware volume to search + @param[out] PeiCoreEntryPoint The entry point of the PEI Core image + + @retval EFI_SUCCESS The file and section was found + @retval EFI_NOT_FOUND The file and section was not found + @retval EFI_VOLUME_CORRUPTED The firmware volume was corrupted + +**/ +EFI_STATUS +FindPeiCoreImageBaseInFv ( + IN EFI_FIRMWARE_VOLUME_HEADER *Fv, + OUT EFI_PHYSICAL_ADDRESS *PeiCoreImageBase + ) +{ + EFI_STATUS Status; + EFI_COMMON_SECTION_HEADER *Section; + + Status =3D FindFfsFileAndSection ( + Fv, + EFI_FV_FILETYPE_PEI_CORE, + EFI_SECTION_PE32, + &Section + ); + if (EFI_ERROR (Status)) { + Status =3D FindFfsFileAndSection ( + Fv, + EFI_FV_FILETYPE_PEI_CORE, + EFI_SECTION_TE, + &Section + ); + if (EFI_ERROR (Status)) { + DEBUG ((EFI_D_ERROR, "Unable to find PEI Core image\n")); + return Status; + } + } + DEBUG ((EFI_D_ERROR, "PeiCoreImageBase found\n")); + *PeiCoreImageBase =3D (EFI_PHYSICAL_ADDRESS)(UINTN)(Section + 1); + return EFI_SUCCESS; +} + +/** + Locates the PEI Core entry point address + + @param[in,out] Fv The firmware volume to search + @param[out] PeiCoreEntryPoint The entry point of the PEI Core image + + @retval EFI_SUCCESS The file and section was found + @retval EFI_NOT_FOUND The file and section was not found + @retval EFI_VOLUME_CORRUPTED The firmware volume was corrupted + +**/ +VOID +FindPeiCoreImageBase ( + IN OUT EFI_FIRMWARE_VOLUME_HEADER **BootFv, + OUT EFI_PHYSICAL_ADDRESS *PeiCoreImageBase + ) +{ + *PeiCoreImageBase =3D 0; + + DEBUG ((EFI_D_INFO, "FindPeiCoreImageBaseInFv\n")); + FindPeiCoreImageBaseInFv (*BootFv, PeiCoreImageBase); +} + +/* + Find and return Pei Core entry point. + + It also find SEC and PEI Core file debug inforamtion. It will report the= m if + remote debug is enabled. + +**/ +VOID +FindAndReportEntryPoints ( + IN EFI_FIRMWARE_VOLUME_HEADER **BootFirmwareVolumePtr, + OUT EFI_PEI_CORE_ENTRY_POINT *PeiCoreEntryPoint + ) +{ + EFI_STATUS Status; + EFI_PHYSICAL_ADDRESS PeiCoreImageBase; + + DEBUG ((EFI_D_INFO, "FindAndReportEntryPoints\n")); + + FindPeiCoreImageBase (BootFirmwareVolumePtr, &PeiCoreImageBase); + // + // Find PEI Core entry point + // + Status =3D PeCoffLoaderGetEntryPoint ((VOID *) (UINTN) PeiCoreImageBase,= (VOID**) PeiCoreEntryPoint); + if (EFI_ERROR(Status)) { + *PeiCoreEntryPoint =3D 0; + } + DEBUG ((EFI_D_INFO, "PeCoffLoaderGetEntryPoint success: %x\n", *PeiCoreE= ntryPoint)); + + return; +} +/* + Print out the content of firmware context. + +**/ +VOID +DebutPrintFirmwareContext ( + EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext + ) +{ + DEBUG ((EFI_D_INFO, "[OpenSBI]: OpenSBI Firmware Context at 0x%x\n", Fir= mwareContext)); + DEBUG ((EFI_D_INFO, " PEI Service at 0x%x\n\n", FirmwareContex= t->PeiServiceTable)); +} + +EFI_STATUS +EFIAPI +TemporaryRamMigration ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase, + IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase, + IN UINTN CopySize + ) +{ + VOID *OldHeap; + VOID *NewHeap; + VOID *OldStack; + VOID *NewStack; + struct sbi_platform *ThisSbiPlatform; + + DEBUG ((EFI_D_INFO, + "TemporaryRamMigration(0x%Lx, 0x%Lx, 0x%Lx)\n", + TemporaryMemoryBase, + PermanentMemoryBase, + (UINT64)CopySize + )); + + OldHeap =3D (VOID*)(UINTN)TemporaryMemoryBase; + NewHeap =3D (VOID*)((UINTN)PermanentMemoryBase + (CopySize >> 1)); + + OldStack =3D (VOID*)((UINTN)TemporaryMemoryBase + (CopySize >> 1)); + NewStack =3D (VOID*)(UINTN)PermanentMemoryBase; + + CopyMem (NewHeap, OldHeap, CopySize >> 1); // Migrate Heap + CopyMem (NewStack, OldStack, CopySize >> 1); // Migrate Stack + + // + // Reset firmware context pointer + // + ThisSbiPlatform =3D (struct sbi_platform *)sbi_platform_ptr(sbi_scratch_= thishart_ptr()); + ThisSbiPlatform->firmware_context +=3D (unsigned long)((UINTN)NewStack -= (UINTN)OldStack); + // + // Relocate PEI Service ** + // + ((EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)ThisSbiPlatform->firmware_context= )->PeiServiceTable +=3D (unsigned long)((UINTN)NewStack - (UINTN)OldStack); + DEBUG ((EFI_D_INFO, "[OpenSBI]: OpenSBI Firmware Context is relocated to= 0x%x\n", ThisSbiPlatform->firmware_context)); + DebutPrintFirmwareContext ((EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)ThisSbi= Platform->firmware_context); + + register uintptr_t a0 asm ("a0") =3D (uintptr_t)((UINTN)NewStack - (UINT= N)OldStack); + asm volatile ("add sp, sp, a0"::"r"(a0):); + return EFI_SUCCESS; +} + +EFI_STATUS EFIAPI TemporaryRamDone (VOID) +{ + DEBUG ((EFI_D_INFO, "2nd time PEI core, temporary ram done.\n")); + return EFI_SUCCESS; +} + +#if 1 +#define GPIO_CTRL_ADDR 0x54002000 +#define GPIO_OUTPUT_VAL 0x0C +static volatile UINT32 * const gpio =3D (void *)GPIO_CTRL_ADDR; +#define REG32(p, i) ((p)[(i)>>2]) +#endif + +static VOID EFIAPI PeiCore(VOID) +{ + EFI_SEC_PEI_HAND_OFF SecCoreData; + EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint; + EFI_FIRMWARE_VOLUME_HEADER *BootFv =3D (EFI_FIRMWARE_VOLUME_HEADER *)Fix= edPcdGet32(PcdRiscVPeiFvBase); + EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT FirmwareContext; + struct sbi_platform *ThisSbiPlatform; + UINT32 HartId; + + REG32(gpio, GPIO_OUTPUT_VAL) =3D 0x88; + FindAndReportEntryPoints (&BootFv, &PeiCoreEntryPoint); + + SecCoreData.DataSize =3D sizeof(EFI_SEC_PEI_HAND_OFF); + SecCoreData.BootFirmwareVolumeBase =3D BootFv; + SecCoreData.BootFirmwareVolumeSize =3D (UINTN) BootFv->FvLength; + SecCoreData.TemporaryRamBase =3D (VOID*)(UINT64) FixedPcdGet32(Pcd= TemporaryRamBase); + SecCoreData.TemporaryRamSize =3D (UINTN) FixedPcdGet32(PcdTempora= ryRamSize); + SecCoreData.PeiTemporaryRamBase =3D SecCoreData.TemporaryRamBase; + SecCoreData.PeiTemporaryRamSize =3D SecCoreData.TemporaryRamSize >> 1; + SecCoreData.StackBase =3D (UINT8 *)SecCoreData.TemporaryRam= Base + (SecCoreData.TemporaryRamSize >> 1); + SecCoreData.StackSize =3D SecCoreData.TemporaryRamSize >> 1; + + // + // Print out scratch address of each hart + // + DEBUG ((EFI_D_INFO, "[OpenSBI]: OpenSBI scratch address for each hart:\n= ")); + for (HartId =3D 0; HartId < FixedPcdGet32 (PcdHartCount); HartId ++) { + DEBUG ((EFI_D_INFO, " Hart %d: 0x%x\n", HartId, sbi_hart_id_t= o_scratch(sbi_scratch_thishart_ptr(), HartId))); + } + + // + // Set up OpepSBI firmware context poitner on boot hart OpenSbi scratch.= Firmware context residents in stack and will be + // switched to memory when temporary ram migration. + // + ZeroMem ((VOID *)&FirmwareContext, sizeof (EFI_RISCV_OPENSBI_FIRMWARE_CO= NTEXT)); + ThisSbiPlatform =3D (struct sbi_platform *)sbi_platform_ptr(sbi_scratch_= thishart_ptr()); + if (ThisSbiPlatform->opensbi_version > OPENSBI_VERSION) { + DEBUG ((EFI_D_ERROR, "[OpenSBI]: OpenSBI platform table version 0x%x= is newer than OpenSBI version 0x%x.\n" + "There maybe be some backward compatable issues= .\n", + ThisSbiPlatform->opensbi_version, + OPENSBI_VERSION + )); + ASSERT(FALSE); + } + DEBUG ((EFI_D_INFO, "[OpenSBI]: OpenSBI platform table at address: 0x%x\= nFirmware Context is located at 0x%x\n", + ThisSbiPlatform, + &FirmwareContext + )); + ThisSbiPlatform->firmware_context =3D (unsigned long)&FirmwareContext; + // + // Set firmware context Hart-specific pointer + // + for (HartId =3D 0; HartId < FixedPcdGet32 (PcdHartCount); HartId ++) { + FirmwareContext.HartSpecific [HartId] =3D \ + (EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *)((UINT8 *)sbi_hart_id_to= _scratch(sbi_scratch_thishart_ptr(), HartId) - FIRMWARE_CONTEXT_HART_SPECIF= IC_SIZE); + DEBUG ((EFI_D_INFO, "[OpenSBI]: OpenSBI Hart %d Firmware Context Hart-= specific at address: 0x%x\n", + HartId, + FirmwareContext.HartSpecific [HartId] + )); + } + + // + // Transfer the control to the PEI core + // + (*PeiCoreEntryPoint) (&SecCoreData, (EFI_PEI_PPI_DESCRIPTOR *)&mPrivateD= ispatchTable); +} +/** + This function initilizes hart specific information and SBI. + For the boot hart, it boots system through PEI core and initial SBI in t= he DXE IPL. + For others, it goes to initial SBI and halt. + + the lay out of memory region for each hart is as below delineates, + + _ = ____ + |----Scratch ends | = | + | | sizeof (sbi_scratch) = | + | _| = | + |----Scratch buffer start s <----- *scratch = | + |----Firmware Context Hart-specific ends _ = | + | | = | + | | FIRMWARE_CONTEXT_HART_SP= ECIFIC_SIZE | + | | = | PcdOpenSbiStackSize + | _| = | + |----Firmware Context Hart-specific starts <----- **HartFirmwareContex= t | + |----Hart stack top _ = | + | | = | + | | = | + | | Stack = | + | | = | + | _| = ____| + |----Hart stack bottom + +**/ +VOID EFIAPI SecCoreStartUpWithStack(unsigned long hartid, struct sbi_scrat= ch *scratch) +{ + EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *HartFirmwareContext; + + // + // Setup EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC for each hart. + // + HartFirmwareContext =3D (EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *)((UI= NT8 *)scratch - FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE); + HartFirmwareContext->IsaExtensionSupported =3D RiscVReadMisa (); + HartFirmwareContext->MachineVendorId.Value64_L =3D RiscVReadMVendorId (); + HartFirmwareContext->MachineVendorId.Value64_H =3D 0; + HartFirmwareContext->MachineArchId.Value64_L =3D RiscVReadMArchId (); + HartFirmwareContext->MachineArchId.Value64_H =3D 0; + HartFirmwareContext->MachineImplId.Value64_L =3D RiscVReadMImplId (); + HartFirmwareContext->MachineImplId.Value64_H =3D 0; + +#if 0 + while (HartsIn !=3D hartid); + DEBUG ((EFI_D_INFO, "[OpenSBI]: Initial Firmware Context Hart-specific f= or HART ID:%d\n", hartid)); + DEBUG ((EFI_D_INFO, " Scratch at address: 0x%x\n", scratch)); + DEBUG ((EFI_D_INFO, " Firmware Context Hart-specific at addres= s: 0x%x\n", HartFirmwareContext)); + DEBUG ((EFI_D_INFO, " stack pointer at address: 0x%x\n", stack= _point)); + DEBUG ((EFI_D_INFO, " MISA: 0x%x\n", HartFirmwareCont= ext->IsaExtensionSupported)); + DEBUG ((EFI_D_INFO, " MVENDORID: 0x%x\n", HartFirmwar= eContext->MachineVendorId.Value64_L)); + DEBUG ((EFI_D_INFO, " MARCHID: 0x%x\n", HartFirmwareC= ontext->MachineArchId.Value64_L)); + DEBUG ((EFI_D_INFO, " MIMPID: 0x%x\n\n", HartFirmware= Context->MachineImplId.Value64_L)); + HartsIn ++; + for (;;); +#endif + + if (hartid =3D=3D FixedPcdGet32(PcdBootHartId)) { + PeiCore(); + } + sbi_init(scratch); +} diff --git a/Platform/RiscV/Universal/Sec/SecMain.h b/Platform/RiscV/Univer= sal/Sec/SecMain.h new file mode 100644 index 0000000..89f238e --- /dev/null +++ b/Platform/RiscV/Universal/Sec/SecMain.h @@ -0,0 +1,56 @@ +/** @file + RISC-V SEC phase module definitions.. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may be= found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +**/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +VOID +SecMachineModeTrapHandler ( + IN VOID + ); + +VOID +EFIAPI +SecStartupPhase2 ( + IN VOID *Context + ); + +EFI_STATUS +EFIAPI +TemporaryRamMigration ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase, + IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase, + IN UINTN CopySize + ); + +EFI_STATUS +EFIAPI +TemporaryRamDone ( + VOID + ); diff --git a/Platform/RiscV/Universal/Sec/SecMain.inf b/Platform/RiscV/Univ= ersal/Sec/SecMain.inf new file mode 100644 index 0000000..4624f35 --- /dev/null +++ b/Platform/RiscV/Universal/Sec/SecMain.inf @@ -0,0 +1,81 @@ +## @file +# RISC-V SEC module. +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may b= e found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D SecMain + FILE_GUID =3D df1ccef6-f301-4a63-9661-fc6030dcc880 + MODULE_TYPE =3D SEC + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D SecMain + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D RISCV64 EBC +# + +[Sources] + SecMain.c + +[Sources.RISCV64] + Riscv64/SecEntry.s + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + RiscVPkg/RiscVPkg.dec + Platform/RiscV/RiscVPlatformPkg.dec + +[LibraryClasses] + BaseLib + DebugLib + BaseMemoryLib + PcdLib + DebugAgentLib + IoLib + PeCoffLib + PeCoffGetEntryPointLib + PeCoffExtraActionLib + ExtractGuidedSectionLib + RiscVCpuLib + PrintLib + SerialPortLib + RiscVOpensbiLib + OpenSbiPlatformLib # This is required library which + # provides platform level opensbi + # functions. + +[Ppis] + gEfiTemporaryRamSupportPpiGuid # PPI ALWAYS_PRODUCED + gEfiTemporaryRamDonePpiGuid # PPI ALWAYS_PRODUCED + +[Guids] + gUefiRiscVMachineContextGuid + +[FixedPcd] + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVPeiFvBase + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVPeiFvSize + +[Pcd] + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwStartAddress + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwEndAddress + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamBase + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamSize + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamBase + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamSize -- 2.7.4