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charset="us-ascii" Content-Transfer-Encoding: quoted-printable > -----Original Message----- > From: Leif Lindholm > Sent: Wednesday, June 17, 2020 8:24 PM > To: Wasim Khan (OSS) > Cc: devel@edk2.groups.io; Meenakshi Aggarwal > ; Varun Sethi ; > ard.biesheuvel@arm.com; Wasim Khan > Subject: Re: [PATCH edk2-platforms 2/8] Silicon/NXP: Chassis2: define SVR > macros >=20 > On Wed, Jun 10, 2020 at 02:50:53 +0530, Wasim Khan wrote: > > From: Wasim Khan > > > > Define macros to retrieve System Version Register(SVR) related > > information > > > > Signed-off-by: Wasim Khan > > --- > > Silicon/NXP/Chassis2/Include/Chassis.h | 4 ++++ > > 1 file changed, 4 insertions(+) > > > > diff --git a/Silicon/NXP/Chassis2/Include/Chassis.h > > b/Silicon/NXP/Chassis2/Include/Chassis.h > > index e5edd80134a4..7e8bf224884b 100644 > > --- a/Silicon/NXP/Chassis2/Include/Chassis.h > > +++ b/Silicon/NXP/Chassis2/Include/Chassis.h > > @@ -12,6 +12,10 @@ > > > > #define NXP_LAYERSCAPE_CHASSIS2_DCFG_ADDRESS 0x1EE0000 > > > > +#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFE) > > +#define SVR_MAJOR(svr) (((svr) >> 4) & 0xf) > > +#define SVR_MINOR(svr) (((svr) >> 0) & 0xf) > > + > > /* SMMU Defintions */ > > #define SMMU_BASE_ADDR 0x09000000 > > #define SMMU_REG_SCR0 (SMMU_BASE_ADDR + 0x0) >=20 > These macros are identical between Chassis2 and Chassis3V2, and they also= look > like exactly the sort of thing you want identical across different chassi= s. Is there > a common header file they can use? Thank you Leif for the review.=20 These MACROS are chassic specific. Upper 24 bits representation is differen= t in Chassis2 and Chassis3V2 (although not used currently and masked for SV= R calculation but we may need it in future).=20 SVR representation may further change for future SoC, so we would like to k= eep them in chassis specific header file. >=20 > (The set is straightforward, I have no other comments on it.) >=20 > / > Leif >=20 > > -- > > 2.7.4 > >