Re: [PATCH edk2-platforms 1/7] Platform/NXP: LX2160aRdbPkg: Add PCIe space in VirtualMemoryMap

["Wasim Khan (OSS)" <wasim.khan@oss.nxp.com>]

> -----Original Message-----
> From: Leif Lindholm <leif@nuviainc.com>
> Sent: Thursday, June 18, 2020 3:22 PM
> To: Wasim Khan (OSS) <wasim.khan@oss.nxp.com>
> Cc: devel@edk2.groups.io; Meenakshi Aggarwal
> <meenakshi.aggarwal@nxp.com>; Varun Sethi <V.Sethi@nxp.com>;
> ard.biesheuvel@arm.com; Wasim Khan <wasim.khan@nxp.com>
> Subject: Re: [PATCH edk2-platforms 1/7] Platform/NXP: LX2160aRdbPkg: Add
> PCIe space in VirtualMemoryMap
> 
> On Wed, Jun 10, 2020 at 03:47:24 +0530, Wasim Khan wrote:
> > From: Wasim Khan <wasim.khan@nxp.com>
> >
> > Add PCIe space in VirtualMemoryMap
> 
> You appear to be adding six spaces to the memory map, not one.
> 
> I may know why, but most people do not. Please describe in the commit
> message what the spaces are and why there's six of them.

Thank for the review.
We have six PCIe controller on LX2160 SoC. Multiple PCIe controller may get enabled based on RCW.
OK, I will update the commit message.

> 
> /
>     Leif
> 
> > Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
> > ---
> >  Silicon/NXP/LX2160A/Include/Soc.h                                     |  8 +++++
> >
> Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
> > | 38 +++++++++++++++++++-
> >  2 files changed, 45 insertions(+), 1 deletion(-)
> >
> > diff --git a/Silicon/NXP/LX2160A/Include/Soc.h
> > b/Silicon/NXP/LX2160A/Include/Soc.h
> > index 6c745d580a6d..7e6359485aaf 100644
> > --- a/Silicon/NXP/LX2160A/Include/Soc.h
> > +++ b/Silicon/NXP/LX2160A/Include/Soc.h
> > @@ -26,6 +26,14 @@
> >  #define LX2160A_FSPI0_PHYS_ADDRESS   (BASE_512MB)
> >  #define LX2160A_FSPI0_SIZE           (SIZE_256MB)
> >
> > +#define LX2160A_PCI1_PHYS_ADDRESS    0x8000000000
> > +#define LX2160A_PCI2_PHYS_ADDRESS    0x8800000000
> > +#define LX2160A_PCI3_PHYS_ADDRESS    0x9000000000
> > +#define LX2160A_PCI4_PHYS_ADDRESS    0x9800000000
> > +#define LX2160A_PCI5_PHYS_ADDRESS    0xa000000000
> > +#define LX2160A_PCI6_PHYS_ADDRESS    0xa800000000
> > +#define LX2160A_PCI_SIZE             SIZE_32GB
> > +
> >  #define LX2160A_DCFG_ADDRESS
> NXP_LAYERSCAPE_CHASSIS3V2_DCFG_ADDRESS
> >
> >  // SVR
> > diff --git
> >
> a/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.
> > c
> >
> b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.
> > c index 391dab265ad7..c03bc23f4a1d 100644
> > ---
> >
> a/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.
> > c
> > +++ b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib
> > +++ Mem.c
> > @@ -12,7 +12,7 @@
> >  #include <Library/MemoryAllocationLib.h>  #include <Soc.h>
> >
> > -#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS          6
> > +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS          12
> >
> >  /**
> >    Return the Virtual Memory Map of your platform @@ -71,6 +71,42 @@
> > ArmPlatformGetVirtualMemoryMap (
> >    VirtualMemoryTable[Index].Length       = LX2160A_FSPI0_SIZE;
> >    VirtualMemoryTable[Index++].Attributes =
> > ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> >
> > +  // PCIe1
> > +  VirtualMemoryTable[Index].PhysicalBase = LX2160A_PCI1_PHYS_ADDRESS;
> > + VirtualMemoryTable[Index].VirtualBase  = LX2160A_PCI1_PHYS_ADDRESS;
> > +  VirtualMemoryTable[Index].Length       = LX2160A_PCI_SIZE;
> > +  VirtualMemoryTable[Index++].Attributes   =
> ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> > +
> > +  // PCIe2
> > +  VirtualMemoryTable[Index].PhysicalBase = LX2160A_PCI2_PHYS_ADDRESS;
> > + VirtualMemoryTable[Index].VirtualBase  = LX2160A_PCI2_PHYS_ADDRESS;
> > +  VirtualMemoryTable[Index].Length       = LX2160A_PCI_SIZE;
> > +  VirtualMemoryTable[Index++].Attributes   =
> ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> > +
> > +  // PCIe3
> > +  VirtualMemoryTable[Index].PhysicalBase = LX2160A_PCI3_PHYS_ADDRESS;
> > + VirtualMemoryTable[Index].VirtualBase  = LX2160A_PCI3_PHYS_ADDRESS;
> > +  VirtualMemoryTable[Index].Length       = LX2160A_PCI_SIZE;
> > +  VirtualMemoryTable[Index++].Attributes   =
> ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> > +
> > +  // PCIe4
> > +  VirtualMemoryTable[Index].PhysicalBase = LX2160A_PCI4_PHYS_ADDRESS;
> > + VirtualMemoryTable[Index].VirtualBase  = LX2160A_PCI4_PHYS_ADDRESS;
> > +  VirtualMemoryTable[Index].Length       = LX2160A_PCI_SIZE;
> > +  VirtualMemoryTable[Index++].Attributes   =
> ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> > +
> > +  // PCIe5
> > +  VirtualMemoryTable[Index].PhysicalBase = LX2160A_PCI5_PHYS_ADDRESS;
> > + VirtualMemoryTable[Index].VirtualBase  = LX2160A_PCI5_PHYS_ADDRESS;
> > +  VirtualMemoryTable[Index].Length       = LX2160A_PCI_SIZE;
> > +  VirtualMemoryTable[Index++].Attributes   =
> ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> > +
> > +  // PCIe6
> > +  VirtualMemoryTable[Index].PhysicalBase = LX2160A_PCI6_PHYS_ADDRESS;
> > + VirtualMemoryTable[Index].VirtualBase  = LX2160A_PCI6_PHYS_ADDRESS;
> > +  VirtualMemoryTable[Index].Length       = LX2160A_PCI_SIZE;
> > +  VirtualMemoryTable[Index++].Attributes   =
> ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> > +
> >    // End of Table
> >    ZeroMem (&VirtualMemoryTable[Index], sizeof
> > (ARM_MEMORY_REGION_DESCRIPTOR));
> >
> > --
> > 2.7.4
> >