From: "Wasim Khan (OSS)" <wasim.khan@oss.nxp.com>
To: Ard Biesheuvel <ard.biesheuvel@arm.com>,
"Wasim Khan (OSS)" <wasim.khan@oss.nxp.com>,
"devel@edk2.groups.io" <devel@edk2.groups.io>,
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>,
Vabhav Sharma <vabhav.sharma@nxp.com>,
Varun Sethi <V.Sethi@nxp.com>,
"leif@nuviainc.com" <leif@nuviainc.com>,
"jon@solid-run.com" <jon@solid-run.com>
Subject: Re: [PATCH edk2-platforms 11/16] Silicon/NXP: PciSegmentLib: Add support PCIe LsGen4 Controller
Date: Sun, 24 May 2020 18:32:07 +0000 [thread overview]
Message-ID: <VE1PR04MB670270A59CAE07B6B1D58D0B90B20@VE1PR04MB6702.eurprd04.prod.outlook.com> (raw)
In-Reply-To: <863b60d6-fa4e-91d4-cbaa-8c1a8b939b61@arm.com>
> -----Original Message-----
> From: Ard Biesheuvel <ard.biesheuvel@arm.com>
> Sent: Friday, May 22, 2020 3:08 PM
> To: Wasim Khan (OSS) <wasim.khan@oss.nxp.com>; devel@edk2.groups.io;
> Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Vabhav Sharma
> <vabhav.sharma@nxp.com>; Varun Sethi <V.Sethi@nxp.com>;
> leif@nuviainc.com; jon@solid-run.com
> Cc: Wasim Khan <wasim.khan@nxp.com>
> Subject: Re: [PATCH edk2-platforms 11/16] Silicon/NXP: PciSegmentLib: Add
> support PCIe LsGen4 Controller
>
> On 5/22/20 1:02 AM, Wasim Khan wrote:
> > From: Wasim Khan <wasim.khan@nxp.com>
> >
> > PCIe Layerscape Gen4 controller is not ECAM complaint and have
>
> compliant
OK
>
> > different PCI config space region for bus 0 (Controller space) and
> > bus[0x1-0xff] on NXP SoCs.
> >
> > For config transactions for Bus0:
> > - Config transaction address = PCIe controller address + offset
> >
> > For config transactions for Bus[0x1-0xff]:
> > - PCIe IP requires target BDF to be written at bit[31:16] of PCIe
> > outbound configuration window.
> >
> > PCIe LsGen4 controller uses paging mechanism to access registers.
> > To access PCIe CCSR registers which are above 3KB offset, page number
> > must be set in Bridge Control Register.
> >
> > Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
> > Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
> > ---
> > .../NXP/Library/PciSegmentLib/PciSegmentLib.inf | 1 +
> > Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c | 60
> +++++++++++++++++++++-
> > 2 files changed, 60 insertions(+), 1 deletion(-)
> >
> > diff --git a/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf
> > b/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf
> > index 936213dc8a9d..d6d7ea6e3b6b 100755
> > --- a/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf
> > +++ b/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf
> > @@ -33,3 +33,4 @@ [FixedPcd]
> >
> > [Pcd]
> > gNxpQoriqLsTokenSpaceGuid.PcdPciCfgShiftEnable
> > + gNxpQoriqLsTokenSpaceGuid.PcdPciLsGen4Ctrl
> > diff --git a/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c
> > b/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c
> > index 552a425c6832..02a1525ef308 100755
> > --- a/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c
> > +++ b/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c
> > @@ -35,6 +35,58 @@ typedef enum {
> > ASSERT (((A) & (0xffff0000f0000000ULL | (M))) == 0)
> >
> > static BOOLEAN CfgShiftEnable;
> > +static BOOLEAN PciLsGen4Ctrl;
> > +
>
> Another compile time constant?
We are initializing PciLsGen4Ctrl with PcdPciLsGen4Ctrl (dynamic PCD).
Based on SoC version, PcdPciLsGen4Ctrl will be set to true for LSGen4 controller (default false).
Support to update these PCDs will come later (Actual use case will be with LX2160 SoC).
>
> > +STATIC
> > +VOID
> > +PcieCfgSetTarget (
> > + IN EFI_PHYSICAL_ADDRESS Dbi,
> > + IN UINT32 Target)
> > +{
> > + PciLsGen4Write32 ((UINTN)Dbi, PAB_AXI_AMAP_PEX_WIN_L(0), Target);
> > + PciLsGen4Write32 ((UINTN)Dbi, PAB_AXI_AMAP_PEX_WIN_H(0), 0); }
> > +
> > +/**
> > + Function to return PCIe Physical Address(PCIe view) or Controller
> > + Address(CPU view) for NXP Layerscape Gen4 SoC
> > +
> > + @param Address Address passed from bus layer.
> > + @param Segment Segment number for Root Complex.
> > + @param Offset Config space register offset.
> > + @param Bus PCIe Bus number.
> > +
> > + @return Return PCIe CPU or Controller address.
> > +
> > +**/
> > +STATIC
> > +UINT64
> > +PciLsGen4GetConfigBase (
> > + IN UINT64 Address,
> > + IN UINT16 Segment,
> > + IN UINT16 Offset,
> > + IN UINT8 Bus
> > + )
> > +{
> > + UINT32 Target;
> > +
> > + if (Bus) {
>
> Bus > 0
>
> > + Target = ((((Address >> 20) & 0xFF) << 24) |
> > + (((Address >> 15) & 0x1F) << 19) |
> > + (((Address >> 12) & 0x7) << 16));
>
> Drop the outer ()
>
> > +
> > + PcieCfgSetTarget ((PCI_SEG0_DBI_BASE + PCI_DBI_SIZE_DIFF* Segment),
> Target);
> > + return PCI_SEG0_MMIO_MEMBASE + Offset + PCI_BASE_DIFF * Segment;
> > + } else {
> > + if (Offset < INDIRECT_ADDR_BNDRY) {
> > + PciLsGen4SetPg (PCI_SEG0_DBI_BASE + PCI_DBI_SIZE_DIFF * Segment,
> 0);
> > + return (PCI_SEG0_DBI_BASE + PCI_DBI_SIZE_DIFF * Segment + Offset);
> > + }
> > + PciLsGen4SetPg (PCI_SEG0_DBI_BASE + PCI_DBI_SIZE_DIFF * Segment,
> OFFSET_TO_PAGE_IDX (Offset));
> > + Offset = OFFSET_TO_PAGE_ADDR (Offset);
> > + return (PCI_SEG0_DBI_BASE + PCI_DBI_SIZE_DIFF * Segment +
> > +Offset);
> > + }
> > +}
> >
> > STATIC
> > UINT64
> > @@ -129,7 +181,12 @@ PciSegmentLibGetConfigBase (
> > UINT8 Bus;
> >
> > Bus = ((UINT32)Address >> 20) & 0xff;
> > - return PciLsGetConfigBase (Address, Segment, Offset, Bus);
> > +
> > + if (PciLsGen4Ctrl) {
> > + return PciLsGen4GetConfigBase (Address, Segment, Offset, Bus); }
> > + else {
> > + return PciLsGetConfigBase (Address, Segment, Offset, Bus); }
> > }
> >
> > /**
> > @@ -620,5 +677,6 @@ PciSegLibInit (
> > )
> > {
> > CfgShiftEnable = CFG_SHIFT_ENABLE;
> > + PciLsGen4Ctrl = PCI_LS_GEN4_CTRL;
> > return EFI_SUCCESS;
> > }
> >
next prev parent reply other threads:[~2020-05-24 18:32 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-21 23:02 [PATCH edk2-platforms 00/16] Add PCIe Support Wasim Khan
2020-05-21 23:02 ` [PATCH edk2-platforms 01/16] Silicon/NXP/NxpQoriqLs.dec: Add PCIe related PCDs Wasim Khan
2020-05-22 9:12 ` Ard Biesheuvel
2020-05-24 18:31 ` Wasim Khan (OSS)
2020-05-26 6:16 ` Ard Biesheuvel
2020-05-21 23:02 ` [PATCH edk2-platforms 02/16] Silicon/NXP: LS1043A: Define " Wasim Khan
2020-05-21 23:02 ` [PATCH edk2-platforms 03/16] Silicon/NXP: Implement PciHostBridgeLib support Wasim Khan
2020-05-22 9:20 ` Ard Biesheuvel
2020-05-21 23:02 ` [PATCH edk2-platforms 04/16] Silicon/NXP: PciHostBridgeLib: CFG Shift feature support for PCIeLS Ctrl Wasim Khan
2020-05-22 9:22 ` Ard Biesheuvel
2020-05-21 23:02 ` [PATCH edk2-platforms 05/16] Silicon/NXP: PciHostBridgeLib: Setup PCIe LsGen4 Controller and ATU Windows Wasim Khan
2020-05-22 9:24 ` Ard Biesheuvel
2020-05-24 18:31 ` Wasim Khan (OSS)
2020-05-21 23:02 ` [PATCH edk2-platforms 06/16] Silicon/NXP: PciHostBridgeLib: add Workaround for A-011451 Wasim Khan
2020-05-21 23:02 ` [PATCH edk2-platforms 07/16] Silicon/NXP: PciHostBridgeLib: Dump Layerscale Gen4 ATU windows Wasim Khan
2020-05-22 9:33 ` Ard Biesheuvel
2020-05-21 23:02 ` [PATCH edk2-platforms 08/16] Silicon/NXP: PciHostBridgeLib: Dump Layerscale iATU windows Wasim Khan
2020-05-22 9:31 ` Ard Biesheuvel
2020-05-21 23:02 ` [PATCH edk2-platforms 09/16] Silicon/NXP: Implement PciSegmentLib for PCIe Layerscape Controller Wasim Khan
2020-05-22 9:29 ` Ard Biesheuvel
2020-05-24 18:32 ` Wasim Khan (OSS)
2020-05-25 4:30 ` Jon Nettleton
2020-05-25 15:21 ` Wasim Khan (OSS)
2020-05-21 23:02 ` [PATCH edk2-platforms 10/16] Silicon/NXP: PciSegmentLib: Add ECAM config support for PCIe LS Controller Wasim Khan
2020-05-22 9:36 ` Ard Biesheuvel
2020-05-24 18:32 ` Wasim Khan (OSS)
2020-05-21 23:02 ` [PATCH edk2-platforms 11/16] Silicon/NXP: PciSegmentLib: Add support PCIe LsGen4 Controller Wasim Khan
2020-05-22 9:38 ` Ard Biesheuvel
2020-05-24 18:32 ` Wasim Khan (OSS) [this message]
2020-05-21 23:02 ` [PATCH edk2-platforms 12/16] Silicon/NXP: PciSegmentLib: LsGen4Ctrl: Add Workaround for A-011264 Wasim Khan
2020-05-22 9:39 ` Ard Biesheuvel
2020-05-24 18:32 ` Wasim Khan (OSS)
2020-05-21 23:02 ` [PATCH edk2-platforms 13/16] Silicon/NXP/Drivers: Implement PciCpuIo2Dxe Driver Wasim Khan
2020-05-22 9:42 ` Ard Biesheuvel
2020-05-21 23:02 ` [PATCH edk2-platforms 14/16] Platform/NXP: LS1043aRdbPkg: Enable NetworkPkg Wasim Khan
2020-05-22 9:42 ` Ard Biesheuvel
2020-05-21 23:02 ` [PATCH edk2-platforms 15/16] Platform/NXP: LS1043aRdbPkg: Enable PCIE support Wasim Khan
2020-05-21 23:02 ` [PATCH edk2-platforms 16/16] Platform/NXP: LS1043aRdbPkg : Increase fv image size Wasim Khan
2020-05-22 9:44 ` Ard Biesheuvel
2020-05-22 9:46 ` [PATCH edk2-platforms 00/16] Add PCIe Support Ard Biesheuvel
2020-05-22 10:58 ` Leif Lindholm
2020-05-24 18:32 ` Wasim Khan (OSS)
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