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From: "Wasim Khan" <wasim.khan@nxp.com>
To: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: edk2-devel-groups-io <devel@edk2.groups.io>,
	Varun Sethi <V.Sethi@nxp.com>, "Wu, Hao A" <hao.a.wu@intel.com>,
	"Ni, Ray" <ray.ni@intel.com>
Subject: Re: [PATCH] MdeModulePkg/PciHostBridge: Update Mem and PMem Limit Checks
Date: Fri, 24 Apr 2020 04:35:13 +0000	[thread overview]
Message-ID: <VE1PR04MB6702CF99033B0CB4D8C6C16B90D00@VE1PR04MB6702.eurprd04.prod.outlook.com> (raw)
In-Reply-To: <CAKv+Gu9WdRAq2yYvMgj-8QKY36tKDfCZZd0hkMkVMtdChc+iuw@mail.gmail.com>



> -----Original Message-----
> From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> Sent: Friday, April 24, 2020 12:27 AM
> To: Wasim Khan <wasim.khan@nxp.com>
> Cc: edk2-devel-groups-io <devel@edk2.groups.io>; Varun Sethi
> <V.Sethi@nxp.com>; Wu, Hao A <hao.a.wu@intel.com>; Ni, Ray
> <ray.ni@intel.com>
> Subject: Re: [PATCH] MdeModulePkg/PciHostBridge: Update Mem and PMem
> Limit Checks
> 
> On Thu, 23 Apr 2020 at 12:43, Wasim Khan <wasim.khan@nxp.com> wrote:
> >
> > With Address Translation Support, it is possible and also correct that
> > Mem and Pmem Limit cross the 4GB boundary.
> > Update the checks so that Mem/PMem Limit should not cross 4GB from the
> > Mem/PMem Base address.
> >
> > Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
> > ---
> >  MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c | 8 ++++----
> >  1 file changed, 4 insertions(+), 4 deletions(-)
> >
> > diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
> > b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
> > index d304fae..9cf7e98 100644
> > --- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
> > +++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
> > @@ -117,8 +117,8 @@ CreateRootBridge (
> >    // Make sure Mem and MemAbove4G apertures are valid
> >    //
> >    if (RESOURCE_VALID (&Bridge->Mem)) {
> > -    ASSERT (Bridge->Mem.Limit < SIZE_4GB);
> > -    if (Bridge->Mem.Limit >= SIZE_4GB) {
> > +    ASSERT (Bridge->Mem.Limit < (Bridge->Mem.Base + SIZE_4GB));
> > +    if (Bridge->Mem.Limit >= (Bridge->Mem.Base + SIZE_4GB)) {
> >        return NULL;
> >      }
> >    }
> > @@ -129,8 +129,8 @@ CreateRootBridge (
> >      }
> >    }
> >    if (RESOURCE_VALID (&Bridge->PMem)) {
> > -    ASSERT (Bridge->PMem.Limit < SIZE_4GB);
> > -    if (Bridge->PMem.Limit >= SIZE_4GB) {
> > +    ASSERT (Bridge->PMem.Limit < (Bridge->PMem.Base + SIZE_4GB));
> > +    if (Bridge->PMem.Limit >= (Bridge->PMem.Base + SIZE_4GB)) {
> >        return NULL;
> >      }
> >    }
> > --
> > 2.7.4
> >
> 
> This is not the right fix.
> 
> The translation offset should be taken into account for these checks

Thanks for the review Ard. 
device address = host address + translation offset.
Mem and Pmem represents "device address" , so that are already taking translation offset into account.

  reply	other threads:[~2020-04-24  4:35 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-04-23 10:43 [PATCH] MdeModulePkg/PciHostBridge: Update Mem and PMem Limit Checks Wasim Khan
2020-04-23 11:36 ` Ni, Ray
2020-04-23 13:52   ` Wasim Khan
2020-04-23 14:28     ` [edk2-devel] " Ni, Ray
2020-04-23 14:53       ` Wasim Khan
2020-04-23 15:17         ` Ni, Ray
2020-04-23 16:04           ` Wasim Khan
2020-04-23 18:56 ` Ard Biesheuvel
2020-04-24  4:35   ` Wasim Khan [this message]
2020-04-24  6:07     ` [edk2-devel] " Ard Biesheuvel
2020-04-24  7:32       ` Wasim Khan

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