From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=40.92.70.51; helo=eur03-am5-obe.outbound.protection.outlook.com; envelope-from=marvin.haeuser@outlook.com; receiver=edk2-devel@lists.01.org Received: from EUR03-AM5-obe.outbound.protection.outlook.com (mail-oln040092070051.outbound.protection.outlook.com [40.92.70.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 03822210C125D for ; Tue, 24 Jul 2018 05:09:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=outlook.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=fATHOrdMIOVTQxtqm4Qhf7D6YPVhIvObQvipDRUMh1k=; b=Xxw0LXgexSx8DHc2kzuot/AyzQouUHNB3/HNtVYsx0Dt79Z76fuZGwFS0Yn8JJ5ut1+tnF6sBAIRqzhuEdsV3gnesy1ryVDCY+Pe34ZBSBquY1ts/fDL4OzMVa18Of9AMBX71Dbn4+7LdlGmbNMJKRFo9EFuw38e6EWdgyAWj5cyILq7ZH6ua6Yqrhc9IcTSPsYFYINht5GBmeXYztoRq68BYgK1473ivfLbbKD3r/B9PISXlsyQOgL3z4DAkbCveXp4lFY+vCMd1dgI60IxMCsIVrotohQY/Hx9cQJnInfMwuBnMGocZbhWb8Z8RMWqZtoW04PUIlP2HpkFQ+Q9pA== Received: from DB5EUR03FT017.eop-EUR03.prod.protection.outlook.com (10.152.20.54) by DB5EUR03HT173.eop-EUR03.prod.protection.outlook.com (10.152.21.58) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.20.995.12; Tue, 24 Jul 2018 12:09:49 +0000 Received: from VI1PR0801MB1790.eurprd08.prod.outlook.com (10.152.20.51) by DB5EUR03FT017.mail.protection.outlook.com (10.152.20.114) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.20.995.12 via Frontend Transport; Tue, 24 Jul 2018 12:09:49 +0000 Received: from VI1PR0801MB1790.eurprd08.prod.outlook.com ([fe80::7532:4dc6:e9f7:4765]) by VI1PR0801MB1790.eurprd08.prod.outlook.com ([fe80::7532:4dc6:e9f7:4765%2]) with mapi id 15.20.0973.022; Tue, 24 Jul 2018 12:09:49 +0000 From: =?iso-8859-1?Q?Marvin_H=E4user?= To: "edk2-devel@lists.01.org" CC: "michael.d.kinney@intel.com" , "liming.gao@intel.com" , "star.zeng@intel.com" , "eric.dong@intel.com" , "ruiyu.ni@intel.com" Thread-Topic: [PATCH v2 1/2] MdePkg: Add PI 1.5 MM PPI declarations. Thread-Index: AQHUI0c3hUEKIDdbX0ijAZWLNqmZZQ== Date: Tue, 24 Jul 2018 12:09:49 +0000 Message-ID: References: In-Reply-To: Accept-Language: de-DE, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: LO2P265CA0152.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:9::20) To VI1PR0801MB1790.eurprd08.prod.outlook.com (2603:10a6:800:5b::15) x-incomingtopheadermarker: OriginalChecksum:03B4E6D28F9571BFDD19A381AFDCD4474F4ADC39634049BDA73BEAED8ED319FD; UpperCasedChecksum:74C9BF4E0D02D6B2CFBFA2918181840FCF6A7F6244A80DF74E77D1D4F7D4AB15; SizeAsReceived:7748; Count:50 x-ms-exchange-messagesentrepresentingtype: 1 x-tmn: [ZdxKPVuYm3rsqdERYMlCw/klgaGQkpZx] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; DB5EUR03HT173; 6:R+euY9qcoB89ou7C9yu5Ahv7mo/eWTrjeJaIKuERAzFBwhmYdxB1vvA5vBLcGnIAUSmtiJnAkBM1zLFVhIqgJ5VgcW0PKYULPgSXJwaqwf7ff4bkP2y/qiyBEoh7ylVT8qqsjyCvihd9qC8lYRi8Uvf4SOPDNnxy+kU8kv6z7JwO2ea31JJVpmEDyjLeq9orNMB77LzXx6rwsAQjgvHBjlN2RgjatvXVNzjuQmEaokUsTBgX7iGAQtyDQI+0KzC67eFCTSBdiD9Ij8CQQhPehWPnX+A6P75T9JiqRXolxab0Tinxb+b2GGHZqnrKNXzawTM72Q9azfVr0opaLbMc0WMzNLjCC6EghJ4wYybE8DONdpVhM7/uM/7hmPIwBqGllqVlI7bFmkaFM0i2yBkFoceUujvgetg2j+i/k4egVyW9PkhNOYbVJYbcwEJwAdngOhv5PlEWzDximdqBdHE5Nw==; 5:8BxKDxqYug3xL/1zsg77n12a+55rNQLdJKbpIthXUYkY6nYNvwYL6G1FactfyF2vDevXFazHdCZBNrNTLid8uhQHdX010f0Z60rtMl3BTV7LFuqIL2yfCDnKXotl62uSCi8FG95oQsmoxKFG3LzZqFOIdDeENj8OYR5+iDk9FFQ=; 7:inU9Wlb0nIKR7pEaXHgpZnMcErYDyDJJk4PoFripyMg4bVUMxTeDw3g36+jrQRB/3FxdmMcQHHj3P5LL1UNLVJ7I39ylTGbq2C5JQR+G1Y83DWNAJ1A/HB+HV1aX+mD6iVw+OEz4gn3dJjqhuQjT6xJ714fI/Fw0Uv/pWFYr2yyIqFKqT8IJCgGqF4embY0FcHEgXKgp674JS5rt1imqYdb751ccyw2y7PP4c7iiMCIF8xSI2tfjEBESXBhbcnka x-incomingheadercount: 50 x-eopattributedmessage: 0 x-microsoft-antispam: BCL:0; PCL:0; RULEID:(7020095)(201702061078)(5061506573)(5061507331)(1603103135)(2017031320274)(2017031324274)(2017031323274)(2017031322404)(1601125500)(1603101448)(1701031045); SRVR:DB5EUR03HT173; x-ms-traffictypediagnostic: DB5EUR03HT173: x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(82015058); SRVR:DB5EUR03HT173; BCL:0; PCL:0; RULEID:; SRVR:DB5EUR03HT173; x-forefront-prvs: 0743E8D0A6 x-forefront-antispam-report: SFV:NSPM; SFS:(7070007)(60444003)(189003)(199004)(8676002)(5660300001)(7696005)(74316002)(305945005)(8936002)(82202002)(2900100001)(33656002)(6916009)(86362001)(575784001)(6436002)(76176011)(966005)(87572001)(55016002)(54906003)(53946003)(20460500001)(6306002)(5640700003)(72206003)(68736007)(2351001)(476003)(102836004)(426003)(16799955002)(446003)(104016004)(6346003)(15188155005)(14454004)(11346002)(256004)(486006)(386003)(56003)(4326008)(97736004)(53376002)(26005)(14444005)(99286004)(5250100002)(105586002)(25786009)(81156014)(106356001)(2501003); DIR:OUT; SFP:1901; SCL:1; SRVR:DB5EUR03HT173; H:VI1PR0801MB1790.eurprd08.prod.outlook.com; FPR:; SPF:None; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: outlook.com does not designate permitted sender hosts) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Marvin.Haeuser@outlook.com; x-microsoft-antispam-message-info: 839JQXBXPozI7bFsgOfDSVn7HxiErX9rQwH7H6ItxEifoVJZ7P0ZaR4f/Pe2qshpnyfg8iTye1U5Jjn0BP7Ow2Cc5AEvrFT35IjDsFPW2+RpugUaHcLWgxdbXASK046Ti6RsngKdXxGI2z6/NOGMnyEt60KWhwvZlidKZa43IlvnhPO5XMl82862qucDcbbkw8h/TzwqYZrmPvYBqMVyCLw//yi2/BgnK+15fIMiZpo= MIME-Version: 1.0 X-OriginatorOrg: outlook.com X-MS-Exchange-CrossTenant-RMS-PersistedConsumerOrg: 7181d4b0-87d6-4f4e-ba33-0d3746212cec X-MS-Exchange-CrossTenant-Network-Message-Id: ccdfa98b-95da-4153-fd2c-08d5f15e5a0d X-MS-Exchange-CrossTenant-rms-persistedconsumerorg: 7181d4b0-87d6-4f4e-ba33-0d3746212cec X-MS-Exchange-CrossTenant-originalarrivaltime: 24 Jul 2018 12:09:49.1156 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Internet X-MS-Exchange-CrossTenant-id: 84df9e7f-e9f6-40af-b435-aaaaaaaaaaaa X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB5EUR03HT173 Subject: [PATCH v2 1/2] MdePkg: Add PI 1.5 MM PPI declarations. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 Jul 2018 12:09:52 -0000 Content-Language: en-US Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Add the declarations for the MM PPIs introduced in PI 1.5. MmAccess, MmCommunication and MmControl are directly derieved from their Smm* counterparts in MdeModulePkg. MmConfiguration is directly derieved from the MmConfiguration Protocol declaration. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marvin Haeuser --- MdePkg/Include/Ppi/MmAccess.h | 146 ++++++++++++++++++++ MdePkg/Include/Ppi/MmCommunication.h | 64 +++++++++ MdePkg/Include/Ppi/MmConfiguration.h | 86 ++++++++++++ MdePkg/Include/Ppi/MmControl.h | 96 +++++++++++++ MdePkg/MdePkg.dec | 12 ++ 5 files changed, 404 insertions(+) diff --git a/MdePkg/Include/Ppi/MmAccess.h b/MdePkg/Include/Ppi/MmAccess.h new file mode 100644 index 000000000000..b1a751aff42c --- /dev/null +++ b/MdePkg/Include/Ppi/MmAccess.h @@ -0,0 +1,146 @@ +/** @file + EFI MM Access PPI definition. + + This PPI is used to control the visibility of the MMRAM on the platform. + It abstracts the location and characteristics of MMRAM. The expectation= is + that the north bridge or memory controller would publish this PPI. + + The principal functionality found in the memory controller includes the = following: + - Exposing the MMRAM to all non-MM agents, or the "open" state + - Shrouding the MMRAM to all but the MM agents, or the "closed" state + - Preserving the system integrity, or "locking" the MMRAM, such that the= settings cannot be + perturbed by either boot service or runtime agents + +Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.
+ +This program and the accompanying materials +are licensed and made available under the terms and conditions +of the BSD License which accompanies this distribution. The +full text of the license may be found at +http://opensource.org/licenses/bsd-license.php + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLI= ED. + +**/ + +#ifndef _MM_ACCESS_PPI_H_ +#define _MM_ACCESS_PPI_H_ + +#define EFI_PEI_MM_ACCESS_PPI_GUID \ + { 0x268f33a9, 0xcccd, 0x48be, { 0x88, 0x17, 0x86, 0x5, 0x3a, 0xc3, 0x2e,= 0xd6 }} + +typedef struct _EFI_PEI_MM_ACCESS_PPI EFI_PEI_MM_ACCESS_PPI; + +/** + Opens the MMRAM area to be accessible by a PEIM driver. + + This function "opens" MMRAM so that it is visible while not inside of MM= . The function should + return EFI_UNSUPPORTED if the hardware does not support hiding of MMRAM.= The function + should return EFI_DEVICE_ERROR if the MMRAM configuration is locked. + + @param PeiServices General purpose services available to eve= ry PEIM. + @param This The pointer to the MM Access Interface. + @param DescriptorIndex The region of MMRAM to Open. + + @retval EFI_SUCCESS The region was successfully opened. + @retval EFI_DEVICE_ERROR The region could not be opened because lo= cked by chipset. + @retval EFI_INVALID_PARAMETER The descriptor index was out of bounds. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_MM_OPEN)( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_MM_ACCESS_PPI *This, + IN UINTN DescriptorIndex + ); + +/** + Inhibits access to the MMRAM. + + This function "closes" MMRAM so that it is not visible while outside of = MM. The function should + return EFI_UNSUPPORTED if the hardware does not support hiding of MMRAM. + + @param PeiServices General purpose services available to e= very PEIM. + @param This The pointer to the MM Access Interface. + @param DescriptorIndex The region of MMRAM to Close. + + @retval EFI_SUCCESS The region was successfully closed. + @retval EFI_DEVICE_ERROR The region could not be closed because = locked by chipset. + @retval EFI_INVALID_PARAMETER The descriptor index was out of bounds. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_MM_CLOSE)( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_MM_ACCESS_PPI *This, + IN UINTN DescriptorIndex + ); + +/** + Inhibits access to the MMRAM. + + This function prohibits access to the MMRAM region. This function is us= ually implemented such + that it is a write-once operation. + + @param PeiServices General purpose services available to e= very PEIM. + @param This The pointer to the MM Access Interface. + @param DescriptorIndex The region of MMRAM to Close. + + @retval EFI_SUCCESS The region was successfully locked. + @retval EFI_DEVICE_ERROR The region could not be locked because at= least + one range is still open. + @retval EFI_INVALID_PARAMETER The descriptor index was out of bounds. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_MM_LOCK)( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_MM_ACCESS_PPI *This, + IN UINTN DescriptorIndex + ); + +/** + Queries the memory controller for the possible regions that will support= MMRAM. + + @param PeiServices General purpose services available to ever= y PEIM. + @param This The pointer to the SmmAccessPpi Interface. + @param SmramMapSize The pointer to the variable containing siz= e of the + buffer to contain the description informat= ion. + @param SmramMap The buffer containing the data describing = the Smram + region descriptors. + + @retval EFI_BUFFER_TOO_SMALL The user did not provide a sufficient buff= er. + @retval EFI_SUCCESS The user provided a sufficiently-sized buf= fer. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_MM_CAPABILITIES)( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_MM_ACCESS_PPI *This, + IN OUT UINTN *SmramMapSize, + IN OUT EFI_MMRAM_DESCRIPTOR *SmramMap + ); + +/// +/// EFI MM Access PPI is used to control the visibility of the MMRAM on t= he platform. +/// It abstracts the location and characteristics of MMRAM. The platform = should report +/// all MMRAM via EFI_PEI_MM_ACCESS_PPI. The expectation is that the nort= h bridge or +/// memory controller would publish this PPI. +/// +struct _EFI_PEI_MM_ACCESS_PPI { + EFI_PEI_MM_OPEN Open; + EFI_PEI_MM_CLOSE Close; + EFI_PEI_MM_LOCK Lock; + EFI_PEI_MM_CAPABILITIES GetCapabilities; + BOOLEAN LockState; + BOOLEAN OpenState; +}; + +extern EFI_GUID gEfiPeiMmAccessPpiGuid; + +#endif diff --git a/MdePkg/Include/Ppi/MmCommunication.h b/MdePkg/Include/Ppi/MmCo= mmunication.h new file mode 100644 index 000000000000..9dce6f8df8dc --- /dev/null +++ b/MdePkg/Include/Ppi/MmCommunication.h @@ -0,0 +1,64 @@ +/** @file + EFI MM Communication PPI definition. + + This Ppi provides a means of communicating between PEIM and MMI + handlers inside of MM. + This Ppi is produced and consumed only in S3 resume boot path. + It is NOT available in normal boot path. + +Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.
+ +This program and the accompanying materials +are licensed and made available under the terms and conditions +of the BSD License which accompanies this distribution. The +full text of the license may be found at +http://opensource.org/licenses/bsd-license.php + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLI= ED. + +**/ + + +#ifndef _MM_COMMUNICATION_PPI_H_ +#define _MM_COMMUNICATION_PPI_H_ + +#define EFI_PEI_MM_COMMUNICATION_PPI_GUID \ + { \ + 0xae933e1c, 0xcc47, 0x4e38, { 0x8f, 0xe, 0xe2, 0xf6, 0x1d, 0x26, 0x5, = 0xdf } \ + } + +typedef struct _EFI_PEI_MM_COMMUNICATION_PPI EFI_PEI_MM_COMMUNICATION_PPI= ; + +/** + Communicates with a registered handler. + + This function provides a service to send and receive messages from a reg= istered UEFI service. + + @param[in] This The EFI_PEI_MM_COMMUNICATION_PPI instance= . + @param[in] CommBuffer A pointer to the buffer to convey into MM= RAM. + @param[in] CommSize The size of the data buffer being passed = in.On exit, the size of data + being returned. Zero if the handler does = not wish to reply with any data. + + @retval EFI_SUCCESS The message was successfully posted. + @retval EFI_INVALID_PARAMETER The CommBuffer was NULL. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_MM_COMMUNICATE)( + IN CONST EFI_PEI_MM_COMMUNICATION_PPI *This, + IN OUT VOID *CommBuffer, + IN OUT UINTN *CommSize + ); + +/// +/// EFI MM Communication PPI provides runtime services for communicating +/// between PEIMs and a registered MMI handler. +/// +struct _EFI_PEI_MM_COMMUNICATION_PPI { + EFI_PEI_MM_COMMUNICATE Communicate; +}; + +extern EFI_GUID gEfiPeiMmCommunicationPpiGuid; + +#endif diff --git a/MdePkg/Include/Ppi/MmConfiguration.h b/MdePkg/Include/Ppi/MmCo= nfiguration.h new file mode 100644 index 000000000000..bbb3ef1360b9 --- /dev/null +++ b/MdePkg/Include/Ppi/MmConfiguration.h @@ -0,0 +1,86 @@ +/** @file + EFI MM Configuration PPI as defined in the PI 1.5 specification. + + This PPI is used to: + 1) report the portions of MMRAM regions which cannot be used for the MMR= AM heap. + 2) register the MM Foundation entry point with the processor code. The e= ntry + point will be invoked by the MM processor entry code. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#ifndef _MM_CONFIGURATION_H_ +#define _MM_CONFIGURATION_H_ + +#include + +#define EFI_PEI_MM_CONFIGURATION_PPI_GUID \ + { \ + 0xc109319, 0xc149, 0x450e, { 0xa3, 0xe3, 0xb9, 0xba, 0xdd, 0x9d, 0xc3,= 0xa4 } \ + } + +/// +/// Structure describing a MMRAM region which cannot be used for the MMRAM= heap. +/// +typedef struct _EFI_PEI_MM_RESERVED_MMRAM_REGION { + /// + /// Starting address of the reserved MMRAM area, as it appears while MMR= AM is open. + /// Ignored if MmramReservedSize is 0. + /// + EFI_PHYSICAL_ADDRESS MmramReservedStart; + /// + /// Number of bytes occupied by the reserved MMRAM area. A size of zero = indicates the + /// last MMRAM area. + /// + UINT64 MmramReservedSize; +} EFI_PEI_MM_RESERVED_MMRAM_REGION; + +typedef struct _EFI_PEI_MM_CONFIGURATION_PPI EFI_PEI_MM_CONFIGURATION_PPI= ; + +/** + Register the MM Foundation entry point. + + This function registers the MM Foundation entry point with the processor= code. This entry point + will be invoked by the MM Processor entry code. + + @param[in] This The EFI_PEI_MM_CONFIGURATION_PPI instance= . + @param[in] MmEntryPoint MM Foundation entry point. + + @retval EFI_SUCCESS Success to register MM Entry Point. + @retval EFI_INVALID_PARAMETER MmEntryPoint is NULL. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_MM_REGISTER_MM_ENTRY)( + IN CONST EFI_PEI_MM_CONFIGURATION_PPI *This, + IN EFI_MM_ENTRY_POINT MmEntryPoint + ); + +/// +/// The EFI MM Configuration PPI is a PPI published by a CPU PEIM to +/// indicate which areas within MMRAM are reserved for use by the CPU for = any purpose, +/// such as stack, save state or MM entry point. +/// +/// The RegistermmEntry() function allows the MM IPL PEIM to register the = MM +/// Foundation entry point with the MM entry vector code. +/// +struct _EFI_PEI_MM_CONFIGURATION_PPI { + /// + /// A pointer to an array MMRAM ranges used by the initial MM entry code= . + /// + EFI_PEI_MM_RESERVED_MMRAM_REGION *MmramReservedRegions; + EFI_PEI_MM_REGISTER_MM_ENTRY RegisterMmEntry; +}; + +extern EFI_GUID gEfiPeiMmConfigurationPpiGuid; + +#endif + diff --git a/MdePkg/Include/Ppi/MmControl.h b/MdePkg/Include/Ppi/MmControl.= h new file mode 100644 index 000000000000..5981c3ac80ed --- /dev/null +++ b/MdePkg/Include/Ppi/MmControl.h @@ -0,0 +1,96 @@ +/** @file + EFI MM Control PPI definition. + + This PPI is used to initiate MMI/PMI activations. This PPO could be publ= ished by either: + - A processor driver to abstract the MMI/PMI IPI + - The driver that abstracts the ASIC that is supporting the APM port, su= ch as the ICH in an + Intel chipset + Because of the possibility of performing MMI or PMI IPI transactions, th= e ability to generate this + event from a platform chipset agent is an optional capability for both I= A-32 and Itanium-based + systems. + + Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions + of the BSD License which accompanies this distribution. The + full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + + +#ifndef _MM_CONTROL_PPI_H_ +#define _MM_CONTROL_PPI_H_ + +#define EFI_PEI_MM_CONTROL_PPI_GUID \ + { 0x61c68702, 0x4d7e, 0x4f43, 0x8d, 0xef, 0xa7, 0x43, 0x5, 0xce, 0x74, 0= xc5 } + +typedef struct _EFI_PEI_MM_CONTROL_PPI EFI_PEI_MM_CONTROL_PPI; + +/** + Invokes MMI activation from either the preboot or runtime environment. + + @param PeiServices General purpose services available to ever= y PEIM. + @param This The EFI_PEI_MM_CONTROL_PPI instance. + @param ArgumentBuffer The optional sized data to pass into the P= PI activation. + @param ArgumentBufferSize The optional size of the data. + @param Periodic An optional mechanism to periodically repe= at activation. + @param ActivationInterval An optional parameter to repeat at this pe= riod one + time or, if the Periodic Boolean is set, p= eriodically. + + @retval EFI_SUCCESS The MMI/PMI has been engendered. + @retval EFI_DEVICE_ERROR The timing is unsupported. + @retval EFI_INVALID_PARAMETER The activation period is unsupported. + @retval EFI_NOT_STARTED The MM base service has not been initializ= ed. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_MM_ACTIVATE) ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_MM_CONTROL_PPI * This, + IN OUT INT8 *ArgumentBuffer OPTIO= NAL, + IN OUT UINTN *ArgumentBufferSize O= PTIONAL, + IN BOOLEAN Periodic OPTIONAL, + IN UINTN ActivationInterval OP= TIONAL + ); + +/** + Clears any system state that was created in response to the Active call. + + @param PeiServices General purpose services available to ever= y PEIM. + @param This The EFI_PEI_MM_CONTROL_PPI instance. + @param Periodic Optional parameter to repeat at this perio= d one + time or, if the Periodic Boolean is set, p= eriodically. + + @retval EFI_SUCCESS The MMI/PMI has been engendered. + @retval EFI_DEVICE_ERROR The source could not be cleared. + @retval EFI_INVALID_PARAMETER The service did not support the Periodic i= nput argument. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_MM_DEACTIVATE) ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_MM_CONTROL_PPI * This, + IN BOOLEAN Periodic OPTIONAL + ); + +/// +/// PEI MM Control PPI is used to initiate MMI/PMI activations. This PPI = could be published by either: +/// - A processor driver to abstract the MMI/PMI IPI +/// - The driver that abstracts the ASIC that is supporting the APM port,= such as the ICH in an +/// Intel chipset +/// +struct _EFI_PEI_MM_CONTROL_PPI { + EFI_PEI_MM_ACTIVATE Trigger; + EFI_PEI_MM_DEACTIVATE Clear; +}; + +extern EFI_GUID gEfiPeiMmControlPpiGuid; + +#endif diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec index 94ad814dc9d6..3994f35f83dc 100644 --- a/MdePkg/MdePkg.dec +++ b/MdePkg/MdePkg.dec @@ -935,6 +935,18 @@ [Ppis] ## Include/Ppi/SecHobData.h gEfiSecHobDataPpiGuid =3D { 0x3ebdaf20, 0x6667, 0x40d8, {0xb4, 0xee, 0xf= 5, 0x99, 0x9a, 0xc1, 0xb7, 0x1f } } =20 + ## Include/Ppi/MmCommunication.h + gEfiPeiMmCommunicationPpiGuid =3D { 0xae933e1c, 0xcc47, 0x4e38, { 0x8f= , 0xe, 0xe2, 0xf6, 0x1d, 0x26, 0x5, 0xdf }} + + ## Include/Ppi/MmAccess.h + gEfiPeiMmAccessPpiGuid =3D { 0x268f33a9, 0xcccd, 0x48be, { 0x88= , 0x17, 0x86, 0x5, 0x3a, 0xc3, 0x2e, 0xd6 }} + + ## Include/Ppi/MmControl.h + gEfiPeiMmControlPpiGuid =3D { 0x61c68702, 0x4d7e, 0x4f43, { 0x8d= , 0xef, 0xa7, 0x43, 0x5, 0xce, 0x74, 0xc5 }} + + ## Include/Ppi/MmConfiguration.h + gEfiPeiMmConfigurationPpiGuid =3D { 0xc109319, 0xc149, 0x450e, { 0xa3, = 0xe3, 0xb9, 0xba, 0xdd, 0x9d, 0xc3, 0xa4 }} + [Protocols] ## Include/Protocol/Pcd.h gPcdProtocolGuid =3D { 0x11B34006, 0xD85B, 0x4D0A, { 0xA2,= 0x90, 0xD5, 0xA5, 0x71, 0x31, 0x0E, 0xF7 }} --=20 2.18.0.windows.1