[PATCH 1/8] MdePkg: Add PI 1.5 MM PPI declarations.

[PATCH 1/8] MdePkg: Add PI 1.5 MM PPI declarations.

[Marvin Häuser]

Add the declarations for the MM PPIs introduced in PI 1.5.
MmAccess, MmCommunication and MmControl are directly derieved from
their Smm* counterparts in MdeModulePkg.
MmConfiguration is directly derieved from the MmConfiguration
Protocol declaration.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marvin Haeuser <Marvin.Haeuser@outlook.com>
---
 MdePkg/Include/Ppi/MmAccess.h        | 146 ++++++++++++++++++++
 MdePkg/Include/Ppi/MmCommunication.h |  64 +++++++++
 MdePkg/Include/Ppi/MmConfiguration.h |  86 ++++++++++++
 MdePkg/Include/Ppi/MmControl.h       |  96 +++++++++++++
 MdePkg/MdePkg.dec                    |  12 ++
 5 files changed, 404 insertions(+)

diff --git a/MdePkg/Include/Ppi/MmAccess.h b/MdePkg/Include/Ppi/MmAccess.h
new file mode 100644
index 000000000000..b1a751aff42c
--- /dev/null
+++ b/MdePkg/Include/Ppi/MmAccess.h
@@ -0,0 +1,146 @@
+/** @file
+  EFI MM Access PPI definition.
+
+  This PPI is used to control the visibility of the MMRAM on the platform.
+  It abstracts the location and characteristics of MMRAM.  The expectation is
+  that the north bridge or memory controller would publish this PPI.
+
+  The principal functionality found in the memory controller includes the following:
+  - Exposing the MMRAM to all non-MM agents, or the "open" state
+  - Shrouding the MMRAM to all but the MM agents, or the "closed" state
+  - Preserving the system integrity, or "locking" the MMRAM, such that the settings cannot be
+    perturbed by either boot service or runtime agents
+
+Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions
+of the BSD License which accompanies this distribution.  The
+full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _MM_ACCESS_PPI_H_
+#define _MM_ACCESS_PPI_H_
+
+#define EFI_PEI_MM_ACCESS_PPI_GUID \
+  { 0x268f33a9, 0xcccd, 0x48be, { 0x88, 0x17, 0x86, 0x5, 0x3a, 0xc3, 0x2e, 0xd6 }}
+
+typedef struct _EFI_PEI_MM_ACCESS_PPI  EFI_PEI_MM_ACCESS_PPI;
+
+/**
+  Opens the MMRAM area to be accessible by a PEIM driver.
+
+  This function "opens" MMRAM so that it is visible while not inside of MM. The function should
+  return EFI_UNSUPPORTED if the hardware does not support hiding of MMRAM. The function
+  should return EFI_DEVICE_ERROR if the MMRAM configuration is locked.
+
+  @param  PeiServices            General purpose services available to every PEIM.
+  @param  This                   The pointer to the MM Access Interface.
+  @param  DescriptorIndex        The region of MMRAM to Open.
+
+  @retval EFI_SUCCESS            The region was successfully opened.
+  @retval EFI_DEVICE_ERROR       The region could not be opened because locked by chipset.
+  @retval EFI_INVALID_PARAMETER  The descriptor index was out of bounds.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_MM_OPEN)(
+  IN EFI_PEI_SERVICES                **PeiServices,
+  IN EFI_PEI_MM_ACCESS_PPI           *This,
+  IN UINTN                           DescriptorIndex
+  );
+
+/**
+  Inhibits access to the MMRAM.
+
+  This function "closes" MMRAM so that it is not visible while outside of MM. The function should
+  return EFI_UNSUPPORTED if the hardware does not support hiding of MMRAM.
+
+  @param  PeiServices              General purpose services available to every PEIM.
+  @param  This                     The pointer to the MM Access Interface.
+  @param  DescriptorIndex          The region of MMRAM to Close.
+
+  @retval EFI_SUCCESS              The region was successfully closed.
+  @retval EFI_DEVICE_ERROR         The region could not be closed because locked by chipset.
+  @retval EFI_INVALID_PARAMETER    The descriptor index was out of bounds.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_MM_CLOSE)(
+  IN EFI_PEI_SERVICES                **PeiServices,
+  IN EFI_PEI_MM_ACCESS_PPI           *This,
+  IN UINTN                           DescriptorIndex
+  );
+
+/**
+  Inhibits access to the MMRAM.
+
+  This function prohibits access to the MMRAM region.  This function is usually implemented such
+  that it is a write-once operation.
+
+  @param  PeiServices              General purpose services available to every PEIM.
+  @param  This                     The pointer to the MM Access Interface.
+  @param  DescriptorIndex          The region of MMRAM to Close.
+
+  @retval EFI_SUCCESS            The region was successfully locked.
+  @retval EFI_DEVICE_ERROR       The region could not be locked because at least
+                                 one range is still open.
+  @retval EFI_INVALID_PARAMETER  The descriptor index was out of bounds.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_MM_LOCK)(
+  IN EFI_PEI_SERVICES                **PeiServices,
+  IN EFI_PEI_MM_ACCESS_PPI           *This,
+  IN UINTN                           DescriptorIndex
+  );
+
+/**
+  Queries the memory controller for the possible regions that will support MMRAM.
+
+  @param  PeiServices           General purpose services available to every PEIM.
+  @param This                   The pointer to the SmmAccessPpi Interface.
+  @param SmramMapSize           The pointer to the variable containing size of the
+                                buffer to contain the description information.
+  @param SmramMap               The buffer containing the data describing the Smram
+                                region descriptors.
+
+  @retval EFI_BUFFER_TOO_SMALL  The user did not provide a sufficient buffer.
+  @retval EFI_SUCCESS           The user provided a sufficiently-sized buffer.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_MM_CAPABILITIES)(
+  IN EFI_PEI_SERVICES                **PeiServices,
+  IN EFI_PEI_MM_ACCESS_PPI           *This,
+  IN OUT UINTN                       *SmramMapSize,
+  IN OUT EFI_MMRAM_DESCRIPTOR        *SmramMap
+  );
+
+///
+///  EFI MM Access PPI is used to control the visibility of the MMRAM on the platform.
+///  It abstracts the location and characteristics of MMRAM. The platform should report
+///  all MMRAM via EFI_PEI_MM_ACCESS_PPI. The expectation is that the north bridge or
+///  memory controller would publish this PPI.
+///
+struct _EFI_PEI_MM_ACCESS_PPI {
+  EFI_PEI_MM_OPEN          Open;
+  EFI_PEI_MM_CLOSE         Close;
+  EFI_PEI_MM_LOCK          Lock;
+  EFI_PEI_MM_CAPABILITIES  GetCapabilities;
+  BOOLEAN                  LockState;
+  BOOLEAN                  OpenState;
+};
+
+extern EFI_GUID gEfiPeiMmAccessPpiGuid;
+
+#endif
diff --git a/MdePkg/Include/Ppi/MmCommunication.h b/MdePkg/Include/Ppi/MmCommunication.h
new file mode 100644
index 000000000000..9dce6f8df8dc
--- /dev/null
+++ b/MdePkg/Include/Ppi/MmCommunication.h
@@ -0,0 +1,64 @@
+/** @file
+  EFI MM Communication PPI definition.
+
+  This Ppi provides a means of communicating between PEIM and MMI
+  handlers inside of MM.
+  This Ppi is produced and consumed only in S3 resume boot path.
+  It is NOT available in normal boot path.
+
+Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions
+of the BSD License which accompanies this distribution.  The
+full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+
+#ifndef _MM_COMMUNICATION_PPI_H_
+#define _MM_COMMUNICATION_PPI_H_
+
+#define EFI_PEI_MM_COMMUNICATION_PPI_GUID \
+  { \
+    0xae933e1c, 0xcc47, 0x4e38, { 0x8f, 0xe, 0xe2, 0xf6, 0x1d, 0x26, 0x5, 0xdf } \
+  }
+
+typedef struct _EFI_PEI_MM_COMMUNICATION_PPI  EFI_PEI_MM_COMMUNICATION_PPI;
+
+/**
+  Communicates with a registered handler.
+
+  This function provides a service to send and receive messages from a registered UEFI service.
+
+  @param[in] This                The EFI_PEI_MM_COMMUNICATION_PPI instance.
+  @param[in] CommBuffer          A pointer to the buffer to convey into MMRAM.
+  @param[in] CommSize            The size of the data buffer being passed in.On exit, the size of data
+                                 being returned. Zero if the handler does not wish to reply with any data.
+
+  @retval EFI_SUCCESS            The message was successfully posted.
+  @retval EFI_INVALID_PARAMETER  The CommBuffer was NULL.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_MM_COMMUNICATE)(
+  IN CONST EFI_PEI_MM_COMMUNICATION_PPI   *This,
+  IN OUT VOID                             *CommBuffer,
+  IN OUT UINTN                            *CommSize
+  );
+
+///
+/// EFI MM Communication PPI provides runtime services for communicating
+/// between PEIMs and a registered MMI handler.
+///
+struct _EFI_PEI_MM_COMMUNICATION_PPI {
+  EFI_PEI_MM_COMMUNICATE  Communicate;
+};
+
+extern EFI_GUID gEfiPeiMmCommunicationPpiGuid;
+
+#endif
diff --git a/MdePkg/Include/Ppi/MmConfiguration.h b/MdePkg/Include/Ppi/MmConfiguration.h
new file mode 100644
index 000000000000..bbb3ef1360b9
--- /dev/null
+++ b/MdePkg/Include/Ppi/MmConfiguration.h
@@ -0,0 +1,86 @@
+/** @file
+  EFI MM Configuration PPI as defined in the PI 1.5 specification.
+
+  This PPI is used to:
+  1) report the portions of MMRAM regions which cannot be used for the MMRAM heap.
+  2) register the MM Foundation entry point with the processor code. The entry
+     point will be invoked by the MM processor entry code.
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _MM_CONFIGURATION_H_
+#define _MM_CONFIGURATION_H_
+
+#include <Pi/PiMmCis.h>
+
+#define EFI_PEI_MM_CONFIGURATION_PPI_GUID \
+  { \
+    0xc109319, 0xc149, 0x450e, { 0xa3, 0xe3, 0xb9, 0xba, 0xdd, 0x9d, 0xc3, 0xa4 } \
+  }
+
+///
+/// Structure describing a MMRAM region which cannot be used for the MMRAM heap.
+///
+typedef struct _EFI_PEI_MM_RESERVED_MMRAM_REGION {
+  ///
+  /// Starting address of the reserved MMRAM area, as it appears while MMRAM is open.
+  /// Ignored if MmramReservedSize is 0.
+  ///
+  EFI_PHYSICAL_ADDRESS    MmramReservedStart;
+  ///
+  /// Number of bytes occupied by the reserved MMRAM area. A size of zero indicates the
+  /// last MMRAM area.
+  ///
+  UINT64                  MmramReservedSize;
+} EFI_PEI_MM_RESERVED_MMRAM_REGION;
+
+typedef struct _EFI_PEI_MM_CONFIGURATION_PPI  EFI_PEI_MM_CONFIGURATION_PPI;
+
+/**
+  Register the MM Foundation entry point.
+
+  This function registers the MM Foundation entry point with the processor code. This entry point
+  will be invoked by the MM Processor entry code.
+
+  @param[in] This                The EFI_PEI_MM_CONFIGURATION_PPI instance.
+  @param[in] MmEntryPoint        MM Foundation entry point.
+
+  @retval EFI_SUCCESS            Success to register MM Entry Point.
+  @retval EFI_INVALID_PARAMETER  MmEntryPoint is NULL.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_MM_REGISTER_MM_ENTRY)(
+  IN CONST EFI_PEI_MM_CONFIGURATION_PPI  *This,
+  IN EFI_MM_ENTRY_POINT                  MmEntryPoint
+  );
+
+///
+/// The EFI MM Configuration PPI is a PPI published by a CPU PEIM to
+/// indicate which areas within MMRAM are reserved for use by the CPU for any purpose,
+/// such as stack, save state or MM entry point.
+///
+/// The RegistermmEntry() function allows the MM IPL PEIM to register the MM
+/// Foundation entry point with the MM entry vector code.
+///
+struct _EFI_PEI_MM_CONFIGURATION_PPI {
+  ///
+  /// A pointer to an array MMRAM ranges used by the initial MM entry code.
+  ///
+  EFI_PEI_MM_RESERVED_MMRAM_REGION  *MmramReservedRegions;
+  EFI_PEI_MM_REGISTER_MM_ENTRY      RegisterMmEntry;
+};
+
+extern EFI_GUID gEfiPeiMmConfigurationPpiGuid;
+
+#endif
+
diff --git a/MdePkg/Include/Ppi/MmControl.h b/MdePkg/Include/Ppi/MmControl.h
new file mode 100644
index 000000000000..5981c3ac80ed
--- /dev/null
+++ b/MdePkg/Include/Ppi/MmControl.h
@@ -0,0 +1,96 @@
+/** @file
+  EFI MM Control PPI definition.
+
+  This PPI is used to initiate MMI/PMI activations. This PPO could be published by either:
+  - A processor driver to abstract the MMI/PMI IPI
+  - The driver that abstracts the ASIC that is supporting the APM port, such as the ICH in an
+  Intel chipset
+  Because of the possibility of performing MMI or PMI IPI transactions, the ability to generate this
+  event from a platform chipset agent is an optional capability for both IA-32 and Itanium-based
+  systems.
+
+  Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions
+  of the BSD License which accompanies this distribution.  The
+  full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+
+#ifndef _MM_CONTROL_PPI_H_
+#define _MM_CONTROL_PPI_H_
+
+#define EFI_PEI_MM_CONTROL_PPI_GUID \
+  { 0x61c68702, 0x4d7e, 0x4f43, 0x8d, 0xef, 0xa7, 0x43, 0x5, 0xce, 0x74, 0xc5 }
+
+typedef struct _EFI_PEI_MM_CONTROL_PPI  EFI_PEI_MM_CONTROL_PPI;
+
+/**
+  Invokes MMI activation from either the preboot or runtime environment.
+
+  @param  PeiServices           General purpose services available to every PEIM.
+  @param  This                  The EFI_PEI_MM_CONTROL_PPI instance.
+  @param  ArgumentBuffer        The optional sized data to pass into the PPI activation.
+  @param  ArgumentBufferSize    The optional size of the data.
+  @param  Periodic              An optional mechanism to periodically repeat activation.
+  @param  ActivationInterval    An optional parameter to repeat at this period one
+                                time or, if the Periodic Boolean is set, periodically.
+
+  @retval EFI_SUCCESS           The MMI/PMI has been engendered.
+  @retval EFI_DEVICE_ERROR      The timing is unsupported.
+  @retval EFI_INVALID_PARAMETER The activation period is unsupported.
+  @retval EFI_NOT_STARTED       The MM base service has not been initialized.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_MM_ACTIVATE) (
+  IN EFI_PEI_SERVICES                                **PeiServices,
+  IN EFI_PEI_MM_CONTROL_PPI                          * This,
+  IN OUT INT8                                        *ArgumentBuffer OPTIONAL,
+  IN OUT UINTN                                       *ArgumentBufferSize OPTIONAL,
+  IN BOOLEAN                                         Periodic OPTIONAL,
+  IN UINTN                                           ActivationInterval OPTIONAL
+  );
+
+/**
+  Clears any system state that was created in response to the Active call.
+
+  @param  PeiServices           General purpose services available to every PEIM.
+  @param  This                  The EFI_PEI_MM_CONTROL_PPI instance.
+  @param  Periodic              Optional parameter to repeat at this period one
+                                time or, if the Periodic Boolean is set, periodically.
+
+  @retval EFI_SUCCESS           The MMI/PMI has been engendered.
+  @retval EFI_DEVICE_ERROR      The source could not be cleared.
+  @retval EFI_INVALID_PARAMETER The service did not support the Periodic input argument.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_MM_DEACTIVATE) (
+  IN EFI_PEI_SERVICES                      **PeiServices,
+  IN EFI_PEI_MM_CONTROL_PPI                * This,
+  IN BOOLEAN                               Periodic OPTIONAL
+  );
+
+///
+///  PEI MM Control PPI is used to initiate MMI/PMI activations. This PPI could be published by either:
+///  - A processor driver to abstract the MMI/PMI IPI
+///  - The driver that abstracts the ASIC that is supporting the APM port, such as the ICH in an
+///  Intel chipset
+///
+struct _EFI_PEI_MM_CONTROL_PPI {
+  EFI_PEI_MM_ACTIVATE    Trigger;
+  EFI_PEI_MM_DEACTIVATE  Clear;
+};
+
+extern EFI_GUID gEfiPeiMmControlPpiGuid;
+
+#endif
diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec
index 94ad814dc9d6..3994f35f83dc 100644
--- a/MdePkg/MdePkg.dec
+++ b/MdePkg/MdePkg.dec
@@ -935,6 +935,18 @@ [Ppis]
   ## Include/Ppi/SecHobData.h
   gEfiSecHobDataPpiGuid = { 0x3ebdaf20, 0x6667, 0x40d8, {0xb4, 0xee, 0xf5, 0x99, 0x9a, 0xc1, 0xb7, 0x1f } }
 
+  ## Include/Ppi/MmCommunication.h
+  gEfiPeiMmCommunicationPpiGuid  =  { 0xae933e1c, 0xcc47, 0x4e38, { 0x8f, 0xe, 0xe2, 0xf6, 0x1d, 0x26, 0x5, 0xdf }}
+
+  ## Include/Ppi/MmAccess.h
+  gEfiPeiMmAccessPpiGuid         =  { 0x268f33a9, 0xcccd, 0x48be, { 0x88, 0x17, 0x86, 0x5, 0x3a, 0xc3, 0x2e, 0xd6 }}
+
+  ## Include/Ppi/MmControl.h
+  gEfiPeiMmControlPpiGuid        =  { 0x61c68702, 0x4d7e, 0x4f43, { 0x8d, 0xef, 0xa7, 0x43, 0x5, 0xce, 0x74, 0xc5 }}
+
+  ## Include/Ppi/MmConfiguration.h
+  gEfiPeiMmConfigurationPpiGuid  = { 0xc109319, 0xc149, 0x450e, { 0xa3, 0xe3, 0xb9, 0xba, 0xdd, 0x9d, 0xc3, 0xa4 }}
+
 [Protocols]
   ## Include/Protocol/Pcd.h
   gPcdProtocolGuid               = { 0x11B34006, 0xD85B, 0x4D0A, { 0xA2, 0x90, 0xD5, 0xA5, 0x71, 0x31, 0x0E, 0xF7 }}
-- 
2.18.0.windows.1