* [edk2-platforms][PATCH v3 0/4] Platform: Add initial support for N1SDP board
@ 2020-07-03 7:02 Pranav Madhu
2020-07-03 7:02 ` [edk2-platforms][PATCH v3 1/4] Silicon/ARM/N1SoC: Add platform library implementation Pranav Madhu
` (3 more replies)
0 siblings, 4 replies; 9+ messages in thread
From: Pranav Madhu @ 2020-07-03 7:02 UTC (permalink / raw)
To: devel
Changes since v2:
- Addressed comments from Thomas.
- Renamed Silicon/ARM/N1Sdp to Silicon/ARM/NeoverseN1Soc.
Changes since v1:
- Addressed comments from Ard.
- Split the code between Silicon and Platform directories.
Arm's N1SDP is a Arm v8.2-A Neoverse N1 CPU based reference design platform
primariliy intended for development on Arm64 based platform. This patch series
adds initial platform support for this board.
The first patch in this series adds the platform libary implementation. The
second patch adds a custom implementation of the PciExpressLib due to a PCIe
integration issue which results in all config space accesses to non-existing
BDFs resulting in a Serror (bus abort). To avoid this, the N1 SoC specific
PciExpressLib implementation provides a workaround for this issue. The third
patch in this series adds the platform library for the PciHostBridge. The
fourth patch adds the initial platform support for the N1SDP platform.
Deepak Pandey (4):
Silicon/ARM/N1SoC: Add platform library implementation
Silicon/ARM/N1SoC: Implement Neoverse N1 Soc specific PciExpressLib
Silicon/ARM/N1SoC: Implement the PciHostBridgeLib library
Platform/ARM/N1SDP: Add initial N1SDP platform support
.../ARM/NeoverseN1Soc/NeoverseN1SocPlatform.dec | 46 +
Platform/ARM/N1Sdp/N1SdpPlatform.dsc | 245 ++++
Platform/ARM/N1Sdp/N1SdpPlatform.fdf | 294 ++++
.../NeoverseN1SocPciExpressLib.inf | 39 +
.../Library/PciHostBridgeLib/PciHostBridgeLib.inf | 49 +
.../Library/PlatformLib/PlatformLib.inf | 54 +
.../NeoverseN1Soc/Include/NeoverseN1SocPlatform.h | 68 +
.../NeoverseN1SocPciExpressLib.c | 1545 ++++++++++++++++++++
.../Library/PciHostBridgeLib/PciHostBridgeLib.c | 187 +++
.../Library/PlatformLib/PlatformLib.c | 67 +
.../Library/PlatformLib/PlatformLibMem.c | 152 ++
.../Library/PlatformLib/AArch64/Helper.S | 84 ++
12 files changed, 2830 insertions(+)
create mode 100644 Silicon/ARM/NeoverseN1Soc/NeoverseN1SocPlatform.dec
create mode 100644 Platform/ARM/N1Sdp/N1SdpPlatform.dsc
create mode 100644 Platform/ARM/N1Sdp/N1SdpPlatform.fdf
create mode 100644 Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/NeoverseN1SocPciExpressLib.inf
create mode 100644 Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf
create mode 100644 Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
create mode 100644 Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1SocPlatform.h
create mode 100644 Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/NeoverseN1SocPciExpressLib.c
create mode 100644 Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c
create mode 100644 Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c
create mode 100644 Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
create mode 100644 Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S
--
2.7.4
^ permalink raw reply [flat|nested] 9+ messages in thread* [edk2-platforms][PATCH v3 1/4] Silicon/ARM/N1SoC: Add platform library implementation 2020-07-03 7:02 [edk2-platforms][PATCH v3 0/4] Platform: Add initial support for N1SDP board Pranav Madhu @ 2020-07-03 7:02 ` Pranav Madhu 2020-07-03 10:35 ` Ard Biesheuvel 2020-07-03 7:02 ` [edk2-platforms][PATCH v3 2/4] Silicon/ARM/N1SoC: Implement Neoverse N1 Soc specific PciExpressLib Pranav Madhu ` (2 subsequent siblings) 3 siblings, 1 reply; 9+ messages in thread From: Pranav Madhu @ 2020-07-03 7:02 UTC (permalink / raw) To: devel; +Cc: Ard Biesheuvel, Leif Lindholm From: Deepak Pandey <Deepak.Pandey@arm.com> Add the initial Arm's Neoverse N1 System-on-Chip platform library support. This includes the virtual memory map and helper functions for platform initialization. Cc: Ard Biesheuvel <ard.biesheuvel@arm.com> Cc: Leif Lindholm <leif@nuviainc.com> Signed-off-by: Pranav Madhu <pranav.madhu@arm.com> diff --git a/Silicon/ARM/NeoverseN1Soc/NeoverseN1SocPlatform.dec b/Silicon/ARM/NeoverseN1Soc/NeoverseN1SocPlatform.dec new file mode 100644 index 000000000000..dba49e6489c0 --- /dev/null +++ b/Silicon/ARM/NeoverseN1Soc/NeoverseN1SocPlatform.dec @@ -0,0 +1,27 @@ +# +# Copyright (c) 2018 - 2020, ARM Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +[Defines] + DEC_SPECIFICATION = 0x0001001A + PACKAGE_NAME = NeoverseN1Soc + PACKAGE_GUID = b6d2d197-76d0-401f-a3e0-826a26f350c9 + PACKAGE_VERSION = 0.1 + +################################################################################ +# +# Include Section - list of Include Paths that are provided by this package. +# Comments are used for Keywords and Module Types. +# +################################################################################ +[Includes.common] + Include # Root include for the package + +[Guids.common] + gArmNeoverseN1SocTokenSpaceGuid = { 0xab93eb78, 0x60d7, 0x4099, { 0xac, 0xeb, 0x6d, 0xb5, 0x02, 0x58, 0x7c, 0x24 } } + +[PcdsFixedAtBuild] + # Secondary DDR memory + gArmNeoverseN1SocTokenSpaceGuid.PcdDramBlock2Base|0|UINT64|0x00000001 diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf new file mode 100644 index 000000000000..b2ea10756071 --- /dev/null +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf @@ -0,0 +1,43 @@ +## @file +# +# Copyright (c) 2018-2020, ARM Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = ArmNeoverseN1SocLib + FILE_GUID = 3d0eafcf-abc1-43d8-9269-709bb24f9d21 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = ArmPlatformLib + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/ARM/NeoverseN1Soc/NeoverseN1SocPlatform.dec + +[Sources.common] + PlatformLibMem.c + PlatformLib.c + +[Sources.AARCH64] + AArch64/Helper.S | GCC + +[FixedPcd] + gArmTokenSpaceGuid.PcdSystemMemoryBase + gArmTokenSpaceGuid.PcdSystemMemorySize + gArmTokenSpaceGuid.PcdArmPrimaryCore + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask + + gArmNeoverseN1SocTokenSpaceGuid.PcdDramBlock2Base + +[Guids] + gEfiHobListGuid ## CONSUMES ## SystemTable + +[Ppis] + gArmMpCoreInfoPpiGuid diff --git a/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1SocPlatform.h b/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1SocPlatform.h new file mode 100644 index 000000000000..c47039c24293 --- /dev/null +++ b/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1SocPlatform.h @@ -0,0 +1,68 @@ +/** @file +* +* Copyright (c) 2018 - 2020, ARM Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#ifndef __NEOVERSEN1SOC_PLATFORM_H__ +#define __NEOVERSEN1SOC_PLATFORM_H__ + +#define NEOVERSEN1SOC_DRAM_BLOCK1_SIZE SIZE_2GB + +//****************************************************************************** +// Platform Memory Map +//****************************************************************************** + +// SubSystem Peripherals - UART0 +#define NEOVERSEN1SOC_UART0_BASE 0x2A400000 +#define NEOVERSEN1SOC_UART0_SZ SIZE_64KB + +// SubSystem Peripherals - UART1 +#define NEOVERSEN1SOC_UART1_BASE 0x2A410000 +#define NEOVERSEN1SOC_UART1_SZ SIZE_64KB + +// SubSystem Peripherals - Generic Watchdog +#define NEOVERSEN1SOC_GENERIC_WDOG_BASE 0x2A440000 +#define NEOVERSEN1SOC_GENERIC_WDOG_SZ SIZE_128KB + +// SubSystem Peripherals - GIC(600) +#define NEOVERSEN1SOC_GIC_BASE 0x30000000 +#define NEOVERSEN1SOC_GICR_BASE 0x300C0000 +#define NEOVERSEN1SOC_GIC_SZ SIZE_256KB +#define NEOVERSEN1SOC_GICR_SZ SIZE_1MB + +// SubSystem non-secure SRAM +#define NEOVERSEN1SOC_NON_SECURE_SRAM_BASE 0x06000000 +#define NEOVERSEN1SOC_NON_SECURE_SRAM_SZ SIZE_64KB + +// AXI Expansion peripherals +#define NEOVERSEN1SOC_EXP_PERIPH_BASE0 0x1C000000 +#define NEOVERSEN1SOC_EXP_PERIPH_BASE0_SZ 0x1300000 + +// Base address to a structure of type NEOVERSEN1SOC_PLAT_INFO which is +// pre-populated by a earlier boot stage +#define NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE (NEOVERSEN1SOC_NON_SECURE_SRAM_BASE + \ + 0x00008000) + +/* + * Platform information structure stored in non secure SRAM. Platform + * information are passed from the trusted firmware with the below structure + * format. The elements of NEOVERSEN1SOC_PLAT_INFO should be always in sync + * with the lower level firmware. + */ +#pragma pack(1) +typedef struct { + /*! 0 - Single Chip, 1 - Chip to Chip (C2C) */ + BOOLEAN MultichipMode; + /*! Slave count in C2C mode */ + UINT8 SlaveCount; + /*! Local DDR memory size in GigaBytes */ + UINT8 LocalDdrSize; + /*! Remote DDR memory size in GigaBytes */ + UINT8 RemoteDdrSize; +} NEOVERSEN1SOC_PLAT_INFO; +#pragma pack() + +#endif diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c new file mode 100644 index 000000000000..6cb699b29716 --- /dev/null +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c @@ -0,0 +1,67 @@ +/** @file +* +* Copyright (c) 2018-2020, ARM Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include <Library/ArmPlatformLib.h> +#include <Library/BaseLib.h> +#include <Ppi/ArmMpCoreInfo.h> + +STATIC ARM_CORE_INFO mCoreInfoTable[] = { + { 0x0, 0x0 }, // Cluster 0, Core 0 + { 0x0, 0x1 }, // Cluster 0, Core 1 + { 0x1, 0x0 }, // Cluster 1, Core 0 + { 0x1, 0x1 } // Cluster 1, Core 1 +}; + +EFI_BOOT_MODE +ArmPlatformGetBootMode ( + VOID + ) +{ + return BOOT_WITH_FULL_CONFIGURATION; +} + +RETURN_STATUS +ArmPlatformInitialize ( + IN UINTN MpId + ) +{ + return RETURN_SUCCESS; +} + +EFI_STATUS +PrePeiCoreGetMpCoreInfo ( + OUT UINTN *CoreCount, + OUT ARM_CORE_INFO **ArmCoreTable + ) +{ + *CoreCount = sizeof (mCoreInfoTable) / sizeof (ARM_CORE_INFO); + *ArmCoreTable = mCoreInfoTable; + return EFI_SUCCESS; +} + +STATIC ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { + PrePeiCoreGetMpCoreInfo +}; + +EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = { + { + EFI_PEI_PPI_DESCRIPTOR_PPI, + &gArmMpCoreInfoPpiGuid, + &mMpCoreInfoPpi + } +}; + +VOID +ArmPlatformGetPlatformPpiList ( + OUT UINTN *PpiListSize, + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList + ) +{ + *PpiListSize = sizeof (gPlatformPpiTable); + *PpiList = gPlatformPpiTable; +} diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c new file mode 100644 index 000000000000..0234748fa72e --- /dev/null +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c @@ -0,0 +1,126 @@ +/** @file +* +* Copyright (c) 2018 - 2020, ARM Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include <Library/ArmPlatformLib.h> +#include <Library/DebugLib.h> +#include <Library/HobLib.h> +#include <Library/MemoryAllocationLib.h> +#include <NeoverseN1SocPlatform.h> + +// The total number of descriptors, including the final "end-of-table" descriptor. +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 9 + +/** + Returns the Virtual Memory Map of the platform. + + This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU + on your platform. + + @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing + a Physical-to-Virtual Memory mapping. This array + must be ended by a zero-filled entry. +**/ +VOID +ArmPlatformGetVirtualMemoryMap ( + IN ARM_MEMORY_REGION_DESCRIPTOR **VirtualMemoryMap + ) +{ + UINTN Index = 0; + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes; + NEOVERSEN1SOC_PLAT_INFO *PlatInfo; + UINT64 DramBlock2Size; + + PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE; + DramBlock2Size = ((UINT64)(PlatInfo->LocalDdrSize - + NEOVERSEN1SOC_DRAM_BLOCK1_SIZE / SIZE_1GB) * + (UINT64)SIZE_1GB); + + ResourceAttributes = + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED; + + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + ResourceAttributes, + FixedPcdGet64 (PcdDramBlock2Base), + DramBlock2Size); + + ASSERT (VirtualMemoryMap != NULL); + Index = 0; + + VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR *)AllocatePages + (EFI_SIZE_TO_PAGES (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) * + MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS)); + if (VirtualMemoryTable == NULL) { + return; + } + + // SubSystem Peripherals - Generic Watchdog + VirtualMemoryTable[Index].PhysicalBase = NEOVERSEN1SOC_GENERIC_WDOG_BASE; + VirtualMemoryTable[Index].VirtualBase = NEOVERSEN1SOC_GENERIC_WDOG_BASE; + VirtualMemoryTable[Index].Length = NEOVERSEN1SOC_GENERIC_WDOG_SZ; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + // SubSystem Peripherals - GIC-600 + VirtualMemoryTable[++Index].PhysicalBase = NEOVERSEN1SOC_GIC_BASE; + VirtualMemoryTable[Index].VirtualBase = NEOVERSEN1SOC_GIC_BASE; + VirtualMemoryTable[Index].Length = NEOVERSEN1SOC_GIC_SZ; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + // SubSystem Peripherals - GICR-600 + VirtualMemoryTable[++Index].PhysicalBase = NEOVERSEN1SOC_GICR_BASE; + VirtualMemoryTable[Index].VirtualBase = NEOVERSEN1SOC_GICR_BASE; + VirtualMemoryTable[Index].Length = NEOVERSEN1SOC_GICR_SZ; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + // OnChip non-secure SRAM + VirtualMemoryTable[++Index].PhysicalBase = NEOVERSEN1SOC_NON_SECURE_SRAM_BASE; + VirtualMemoryTable[Index].VirtualBase = NEOVERSEN1SOC_NON_SECURE_SRAM_BASE; + VirtualMemoryTable[Index].Length = NEOVERSEN1SOC_NON_SECURE_SRAM_SZ; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED; + + // SubSystem Pheripherals - UART0 + VirtualMemoryTable[++Index].PhysicalBase = NEOVERSEN1SOC_UART0_BASE; + VirtualMemoryTable[Index].VirtualBase = NEOVERSEN1SOC_UART0_BASE; + VirtualMemoryTable[Index].Length = NEOVERSEN1SOC_UART0_SZ; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + // DDR Primary (2GB) + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdSystemMemoryBase); + VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdSystemMemoryBase); + VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemMemorySize); + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK; + + // DDR Secondary + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdDramBlock2Base); + VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdDramBlock2Base); + VirtualMemoryTable[Index].Length = DramBlock2Size; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK; + + // Expansion Peripherals + VirtualMemoryTable[++Index].PhysicalBase = NEOVERSEN1SOC_EXP_PERIPH_BASE0; + VirtualMemoryTable[Index].VirtualBase = NEOVERSEN1SOC_EXP_PERIPH_BASE0; + VirtualMemoryTable[Index].Length = NEOVERSEN1SOC_EXP_PERIPH_BASE0_SZ; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + // End of Table + VirtualMemoryTable[++Index].PhysicalBase = 0; + VirtualMemoryTable[Index].VirtualBase = 0; + VirtualMemoryTable[Index].Length = 0; + VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0; + + ASSERT((Index) < MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); + DEBUG ((DEBUG_INIT, "Virtual Memory Table setup complete.\n")); + + *VirtualMemoryMap = VirtualMemoryTable; +} diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S new file mode 100644 index 000000000000..8d2069dea837 --- /dev/null +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S @@ -0,0 +1,84 @@ +/** @file +* +* Copyright (c) 2019 - 2020, ARM Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include <AsmMacroIoLibV8.h> +#include <Library/ArmLib.h> + +.text +.align 3 + +GCC_ASM_EXPORT(ArmPlatformPeiBootAction) +GCC_ASM_EXPORT(ArmPlatformGetCorePosition) +GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId) +GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore) + +// +// First platform specific function to be called in the PEI phase +// +// This function is actually the first function called by the PrePi +// or PrePeiCore modules. It allows to retrieve arguments passed to +// the UEFI firmware through the CPU registers. +// +ASM_PFX(ArmPlatformPeiBootAction): + ret + +// +// Return the core position from the value of its MpId register +// +// This function returns core position from the position 0 in the processor. +// This function might be called from assembler before any stack is set. +// +// @return Return the core position +// +//UINTN +//ArmPlatformGetCorePosition ( +// IN UINTN MpId +// ); +// With this function: CorePos = (ClusterId * 2) + CoreId +ASM_PFX(ArmPlatformGetCorePosition): + and x1, x0, #ARM_CORE_MASK + and x0, x0, #ARM_CLUSTER_MASK + add x0, x1, x0, LSR #7 + ret + +// +// Return the MpId of the primary core +// +// This function returns the MpId of the primary core. +// This function might be called from assembler before any stack is set. +// +// @return Return the MpId of the primary core +// +//UINTN +//ArmPlatformGetPrimaryCoreMpId ( +// VOID +// ); +ASM_PFX(ArmPlatformGetPrimaryCoreMpId): + MOV32 (w0, FixedPcdGet32(PcdArmPrimaryCore)) + ret + +// +// Return a non-zero value if the callee is the primary core +// +// This function returns a non-zero value if the callee is the primary core. +// Primary core is the core responsible to initialize hardware and run UEFI. +// This function might be called from assembler before any stack is set. +// +// @return Return a non-zero value if the callee is the primary core. +// +//UINTN +//ArmPlatformIsPrimaryCore ( +// IN UINTN MpId +// ); +ASM_PFX(ArmPlatformIsPrimaryCore): + MOV32 (w1, FixedPcdGet32(PcdArmPrimaryCoreMask)) + and x0, x0, x1 + MOV32 (w1, FixedPcdGet32(PcdArmPrimaryCore)) + cmp w0, w1 + cset x0, eq + ret -- 2.7.4 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [edk2-platforms][PATCH v3 1/4] Silicon/ARM/N1SoC: Add platform library implementation 2020-07-03 7:02 ` [edk2-platforms][PATCH v3 1/4] Silicon/ARM/N1SoC: Add platform library implementation Pranav Madhu @ 2020-07-03 10:35 ` Ard Biesheuvel 2020-07-03 11:23 ` Pranav Madhu 0 siblings, 1 reply; 9+ messages in thread From: Ard Biesheuvel @ 2020-07-03 10:35 UTC (permalink / raw) To: Pranav Madhu, devel; +Cc: Leif Lindholm Please repost this series with a cover letter, and without stripping the diffstats from the patches. Are you using git format-patch? On 7/3/20 9:02 AM, Pranav Madhu wrote: > From: Deepak Pandey <Deepak.Pandey@arm.com> > > Add the initial Arm's Neoverse N1 System-on-Chip platform library > support. This includes the virtual memory map and helper functions for > platform initialization. > > Cc: Ard Biesheuvel <ard.biesheuvel@arm.com> > Cc: Leif Lindholm <leif@nuviainc.com> > Signed-off-by: Pranav Madhu <pranav.madhu@arm.com> > > diff --git a/Silicon/ARM/NeoverseN1Soc/NeoverseN1SocPlatform.dec b/Silicon/ARM/NeoverseN1Soc/NeoverseN1SocPlatform.dec > new file mode 100644 > index 000000000000..dba49e6489c0 > --- /dev/null > +++ b/Silicon/ARM/NeoverseN1Soc/NeoverseN1SocPlatform.dec > @@ -0,0 +1,27 @@ > +# > +# Copyright (c) 2018 - 2020, ARM Limited. All rights reserved. > +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > + > +[Defines] > + DEC_SPECIFICATION = 0x0001001A > + PACKAGE_NAME = NeoverseN1Soc > + PACKAGE_GUID = b6d2d197-76d0-401f-a3e0-826a26f350c9 > + PACKAGE_VERSION = 0.1 > + > +################################################################################ > +# > +# Include Section - list of Include Paths that are provided by this package. > +# Comments are used for Keywords and Module Types. > +# > +################################################################################ > +[Includes.common] > + Include # Root include for the package > + > +[Guids.common] > + gArmNeoverseN1SocTokenSpaceGuid = { 0xab93eb78, 0x60d7, 0x4099, { 0xac, 0xeb, 0x6d, 0xb5, 0x02, 0x58, 0x7c, 0x24 } } > + > +[PcdsFixedAtBuild] > + # Secondary DDR memory > + gArmNeoverseN1SocTokenSpaceGuid.PcdDramBlock2Base|0|UINT64|0x00000001 > diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf > new file mode 100644 > index 000000000000..b2ea10756071 > --- /dev/null > +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf > @@ -0,0 +1,43 @@ > +## @file > +# > +# Copyright (c) 2018-2020, ARM Limited. All rights reserved. > +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +## > + > +[Defines] > + INF_VERSION = 0x0001001A > + BASE_NAME = ArmNeoverseN1SocLib > + FILE_GUID = 3d0eafcf-abc1-43d8-9269-709bb24f9d21 > + MODULE_TYPE = BASE > + VERSION_STRING = 1.0 > + LIBRARY_CLASS = ArmPlatformLib > + > +[Packages] > + ArmPkg/ArmPkg.dec > + ArmPlatformPkg/ArmPlatformPkg.dec > + MdeModulePkg/MdeModulePkg.dec > + MdePkg/MdePkg.dec > + Silicon/ARM/NeoverseN1Soc/NeoverseN1SocPlatform.dec > + > +[Sources.common] > + PlatformLibMem.c > + PlatformLib.c > + > +[Sources.AARCH64] > + AArch64/Helper.S | GCC > + > +[FixedPcd] > + gArmTokenSpaceGuid.PcdSystemMemoryBase > + gArmTokenSpaceGuid.PcdSystemMemorySize > + gArmTokenSpaceGuid.PcdArmPrimaryCore > + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask > + > + gArmNeoverseN1SocTokenSpaceGuid.PcdDramBlock2Base > + > +[Guids] > + gEfiHobListGuid ## CONSUMES ## SystemTable > + > +[Ppis] > + gArmMpCoreInfoPpiGuid > diff --git a/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1SocPlatform.h b/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1SocPlatform.h > new file mode 100644 > index 000000000000..c47039c24293 > --- /dev/null > +++ b/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1SocPlatform.h > @@ -0,0 +1,68 @@ > +/** @file > +* > +* Copyright (c) 2018 - 2020, ARM Limited. All rights reserved. > +* > +* SPDX-License-Identifier: BSD-2-Clause-Patent > +* > +**/ > + > +#ifndef __NEOVERSEN1SOC_PLATFORM_H__ > +#define __NEOVERSEN1SOC_PLATFORM_H__ > + > +#define NEOVERSEN1SOC_DRAM_BLOCK1_SIZE SIZE_2GB > + > +//****************************************************************************** > +// Platform Memory Map > +//****************************************************************************** > + > +// SubSystem Peripherals - UART0 > +#define NEOVERSEN1SOC_UART0_BASE 0x2A400000 > +#define NEOVERSEN1SOC_UART0_SZ SIZE_64KB > + > +// SubSystem Peripherals - UART1 > +#define NEOVERSEN1SOC_UART1_BASE 0x2A410000 > +#define NEOVERSEN1SOC_UART1_SZ SIZE_64KB > + > +// SubSystem Peripherals - Generic Watchdog > +#define NEOVERSEN1SOC_GENERIC_WDOG_BASE 0x2A440000 > +#define NEOVERSEN1SOC_GENERIC_WDOG_SZ SIZE_128KB > + > +// SubSystem Peripherals - GIC(600) > +#define NEOVERSEN1SOC_GIC_BASE 0x30000000 > +#define NEOVERSEN1SOC_GICR_BASE 0x300C0000 > +#define NEOVERSEN1SOC_GIC_SZ SIZE_256KB > +#define NEOVERSEN1SOC_GICR_SZ SIZE_1MB > + > +// SubSystem non-secure SRAM > +#define NEOVERSEN1SOC_NON_SECURE_SRAM_BASE 0x06000000 > +#define NEOVERSEN1SOC_NON_SECURE_SRAM_SZ SIZE_64KB > + > +// AXI Expansion peripherals > +#define NEOVERSEN1SOC_EXP_PERIPH_BASE0 0x1C000000 > +#define NEOVERSEN1SOC_EXP_PERIPH_BASE0_SZ 0x1300000 > + > +// Base address to a structure of type NEOVERSEN1SOC_PLAT_INFO which is > +// pre-populated by a earlier boot stage > +#define NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE (NEOVERSEN1SOC_NON_SECURE_SRAM_BASE + \ > + 0x00008000) > + > +/* > + * Platform information structure stored in non secure SRAM. Platform > + * information are passed from the trusted firmware with the below structure > + * format. The elements of NEOVERSEN1SOC_PLAT_INFO should be always in sync > + * with the lower level firmware. > + */ > +#pragma pack(1) > +typedef struct { > + /*! 0 - Single Chip, 1 - Chip to Chip (C2C) */ > + BOOLEAN MultichipMode; > + /*! Slave count in C2C mode */ > + UINT8 SlaveCount; > + /*! Local DDR memory size in GigaBytes */ > + UINT8 LocalDdrSize; > + /*! Remote DDR memory size in GigaBytes */ > + UINT8 RemoteDdrSize; > +} NEOVERSEN1SOC_PLAT_INFO; > +#pragma pack() > + > +#endif > diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c > new file mode 100644 > index 000000000000..6cb699b29716 > --- /dev/null > +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c > @@ -0,0 +1,67 @@ > +/** @file > +* > +* Copyright (c) 2018-2020, ARM Limited. All rights reserved. > +* > +* SPDX-License-Identifier: BSD-2-Clause-Patent > +* > +**/ > + > +#include <Library/ArmPlatformLib.h> > +#include <Library/BaseLib.h> > +#include <Ppi/ArmMpCoreInfo.h> > + > +STATIC ARM_CORE_INFO mCoreInfoTable[] = { > + { 0x0, 0x0 }, // Cluster 0, Core 0 > + { 0x0, 0x1 }, // Cluster 0, Core 1 > + { 0x1, 0x0 }, // Cluster 1, Core 0 > + { 0x1, 0x1 } // Cluster 1, Core 1 > +}; > + > +EFI_BOOT_MODE > +ArmPlatformGetBootMode ( > + VOID > + ) > +{ > + return BOOT_WITH_FULL_CONFIGURATION; > +} > + > +RETURN_STATUS > +ArmPlatformInitialize ( > + IN UINTN MpId > + ) > +{ > + return RETURN_SUCCESS; > +} > + > +EFI_STATUS > +PrePeiCoreGetMpCoreInfo ( > + OUT UINTN *CoreCount, > + OUT ARM_CORE_INFO **ArmCoreTable > + ) > +{ > + *CoreCount = sizeof (mCoreInfoTable) / sizeof (ARM_CORE_INFO); > + *ArmCoreTable = mCoreInfoTable; > + return EFI_SUCCESS; > +} > + > +STATIC ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { > + PrePeiCoreGetMpCoreInfo > +}; > + > +EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = { > + { > + EFI_PEI_PPI_DESCRIPTOR_PPI, > + &gArmMpCoreInfoPpiGuid, > + &mMpCoreInfoPpi > + } > +}; > + > +VOID > +ArmPlatformGetPlatformPpiList ( > + OUT UINTN *PpiListSize, > + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList > + ) > +{ > + *PpiListSize = sizeof (gPlatformPpiTable); > + *PpiList = gPlatformPpiTable; > +} > diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c > new file mode 100644 > index 000000000000..0234748fa72e > --- /dev/null > +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c > @@ -0,0 +1,126 @@ > +/** @file > +* > +* Copyright (c) 2018 - 2020, ARM Limited. All rights reserved. > +* > +* SPDX-License-Identifier: BSD-2-Clause-Patent > +* > +**/ > + > +#include <Library/ArmPlatformLib.h> > +#include <Library/DebugLib.h> > +#include <Library/HobLib.h> > +#include <Library/MemoryAllocationLib.h> > +#include <NeoverseN1SocPlatform.h> > + > +// The total number of descriptors, including the final "end-of-table" descriptor. > +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 9 > + > +/** > + Returns the Virtual Memory Map of the platform. > + > + This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU > + on your platform. > + > + @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing > + a Physical-to-Virtual Memory mapping. This array > + must be ended by a zero-filled entry. > +**/ > +VOID > +ArmPlatformGetVirtualMemoryMap ( > + IN ARM_MEMORY_REGION_DESCRIPTOR **VirtualMemoryMap > + ) > +{ > + UINTN Index = 0; > + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; > + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes; > + NEOVERSEN1SOC_PLAT_INFO *PlatInfo; > + UINT64 DramBlock2Size; > + > + PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE; > + DramBlock2Size = ((UINT64)(PlatInfo->LocalDdrSize - > + NEOVERSEN1SOC_DRAM_BLOCK1_SIZE / SIZE_1GB) * > + (UINT64)SIZE_1GB); > + > + ResourceAttributes = > + EFI_RESOURCE_ATTRIBUTE_PRESENT | > + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | > + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | > + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | > + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | > + EFI_RESOURCE_ATTRIBUTE_TESTED; > + > + BuildResourceDescriptorHob ( > + EFI_RESOURCE_SYSTEM_MEMORY, > + ResourceAttributes, > + FixedPcdGet64 (PcdDramBlock2Base), > + DramBlock2Size); > + > + ASSERT (VirtualMemoryMap != NULL); > + Index = 0; > + > + VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR *)AllocatePages > + (EFI_SIZE_TO_PAGES (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) * > + MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS)); > + if (VirtualMemoryTable == NULL) { > + return; > + } > + > + // SubSystem Peripherals - Generic Watchdog > + VirtualMemoryTable[Index].PhysicalBase = NEOVERSEN1SOC_GENERIC_WDOG_BASE; > + VirtualMemoryTable[Index].VirtualBase = NEOVERSEN1SOC_GENERIC_WDOG_BASE; > + VirtualMemoryTable[Index].Length = NEOVERSEN1SOC_GENERIC_WDOG_SZ; > + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; > + > + // SubSystem Peripherals - GIC-600 > + VirtualMemoryTable[++Index].PhysicalBase = NEOVERSEN1SOC_GIC_BASE; > + VirtualMemoryTable[Index].VirtualBase = NEOVERSEN1SOC_GIC_BASE; > + VirtualMemoryTable[Index].Length = NEOVERSEN1SOC_GIC_SZ; > + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; > + > + // SubSystem Peripherals - GICR-600 > + VirtualMemoryTable[++Index].PhysicalBase = NEOVERSEN1SOC_GICR_BASE; > + VirtualMemoryTable[Index].VirtualBase = NEOVERSEN1SOC_GICR_BASE; > + VirtualMemoryTable[Index].Length = NEOVERSEN1SOC_GICR_SZ; > + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; > + > + // OnChip non-secure SRAM > + VirtualMemoryTable[++Index].PhysicalBase = NEOVERSEN1SOC_NON_SECURE_SRAM_BASE; > + VirtualMemoryTable[Index].VirtualBase = NEOVERSEN1SOC_NON_SECURE_SRAM_BASE; > + VirtualMemoryTable[Index].Length = NEOVERSEN1SOC_NON_SECURE_SRAM_SZ; > + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED; > + > + // SubSystem Pheripherals - UART0 > + VirtualMemoryTable[++Index].PhysicalBase = NEOVERSEN1SOC_UART0_BASE; > + VirtualMemoryTable[Index].VirtualBase = NEOVERSEN1SOC_UART0_BASE; > + VirtualMemoryTable[Index].Length = NEOVERSEN1SOC_UART0_SZ; > + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; > + > + // DDR Primary (2GB) > + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdSystemMemoryBase); > + VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdSystemMemoryBase); > + VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemMemorySize); > + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK; > + > + // DDR Secondary > + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdDramBlock2Base); > + VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdDramBlock2Base); > + VirtualMemoryTable[Index].Length = DramBlock2Size; > + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK; > + > + // Expansion Peripherals > + VirtualMemoryTable[++Index].PhysicalBase = NEOVERSEN1SOC_EXP_PERIPH_BASE0; > + VirtualMemoryTable[Index].VirtualBase = NEOVERSEN1SOC_EXP_PERIPH_BASE0; > + VirtualMemoryTable[Index].Length = NEOVERSEN1SOC_EXP_PERIPH_BASE0_SZ; > + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; > + > + // End of Table > + VirtualMemoryTable[++Index].PhysicalBase = 0; > + VirtualMemoryTable[Index].VirtualBase = 0; > + VirtualMemoryTable[Index].Length = 0; > + VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0; > + > + ASSERT((Index) < MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); > + DEBUG ((DEBUG_INIT, "Virtual Memory Table setup complete.\n")); > + > + *VirtualMemoryMap = VirtualMemoryTable; > +} > diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S > new file mode 100644 > index 000000000000..8d2069dea837 > --- /dev/null > +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S > @@ -0,0 +1,84 @@ > +/** @file > +* > +* Copyright (c) 2019 - 2020, ARM Limited. All rights reserved. > +* > +* SPDX-License-Identifier: BSD-2-Clause-Patent > +* > +**/ > + > +#include <AsmMacroIoLibV8.h> > +#include <Library/ArmLib.h> > + > +.text > +.align 3 > + > +GCC_ASM_EXPORT(ArmPlatformPeiBootAction) > +GCC_ASM_EXPORT(ArmPlatformGetCorePosition) > +GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId) > +GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore) > + > +// > +// First platform specific function to be called in the PEI phase > +// > +// This function is actually the first function called by the PrePi > +// or PrePeiCore modules. It allows to retrieve arguments passed to > +// the UEFI firmware through the CPU registers. > +// > +ASM_PFX(ArmPlatformPeiBootAction): > + ret > + > +// > +// Return the core position from the value of its MpId register > +// > +// This function returns core position from the position 0 in the processor. > +// This function might be called from assembler before any stack is set. > +// > +// @return Return the core position > +// > +//UINTN > +//ArmPlatformGetCorePosition ( > +// IN UINTN MpId > +// ); > +// With this function: CorePos = (ClusterId * 2) + CoreId > +ASM_PFX(ArmPlatformGetCorePosition): > + and x1, x0, #ARM_CORE_MASK > + and x0, x0, #ARM_CLUSTER_MASK > + add x0, x1, x0, LSR #7 > + ret > + > +// > +// Return the MpId of the primary core > +// > +// This function returns the MpId of the primary core. > +// This function might be called from assembler before any stack is set. > +// > +// @return Return the MpId of the primary core > +// > +//UINTN > +//ArmPlatformGetPrimaryCoreMpId ( > +// VOID > +// ); > +ASM_PFX(ArmPlatformGetPrimaryCoreMpId): > + MOV32 (w0, FixedPcdGet32(PcdArmPrimaryCore)) > + ret > + > +// > +// Return a non-zero value if the callee is the primary core > +// > +// This function returns a non-zero value if the callee is the primary core. > +// Primary core is the core responsible to initialize hardware and run UEFI. > +// This function might be called from assembler before any stack is set. > +// > +// @return Return a non-zero value if the callee is the primary core. > +// > +//UINTN > +//ArmPlatformIsPrimaryCore ( > +// IN UINTN MpId > +// ); > +ASM_PFX(ArmPlatformIsPrimaryCore): > + MOV32 (w1, FixedPcdGet32(PcdArmPrimaryCoreMask)) > + and x0, x0, x1 > + MOV32 (w1, FixedPcdGet32(PcdArmPrimaryCore)) > + cmp w0, w1 > + cset x0, eq > + ret > ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [edk2-platforms][PATCH v3 1/4] Silicon/ARM/N1SoC: Add platform library implementation 2020-07-03 10:35 ` Ard Biesheuvel @ 2020-07-03 11:23 ` Pranav Madhu 0 siblings, 0 replies; 9+ messages in thread From: Pranav Madhu @ 2020-07-03 11:23 UTC (permalink / raw) To: Ard Biesheuvel, devel@edk2.groups.io; +Cc: Leif Lindholm Hi Ard, > -----Original Message----- > From: Ard Biesheuvel <ard.biesheuvel@arm.com> > Sent: Friday, July 3, 2020 4:05 PM > To: Pranav Madhu <Pranav.Madhu@arm.com>; devel@edk2.groups.io > Cc: Leif Lindholm <leif@nuviainc.com> > Subject: Re: [edk2-platforms][PATCH v3 1/4] Silicon/ARM/N1SoC: Add > platform library implementation > > Please repost this series with a cover letter, and without stripping the > diffstats from the patches. Are you using git format-patch? > Yes, I used git format-patch, but missed to add the option to generate diffstat. This has been fixed now and the series has been posted again as v3. Thanks, Pranav <...> IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ^ permalink raw reply [flat|nested] 9+ messages in thread
* [edk2-platforms][PATCH v3 2/4] Silicon/ARM/N1SoC: Implement Neoverse N1 Soc specific PciExpressLib 2020-07-03 7:02 [edk2-platforms][PATCH v3 0/4] Platform: Add initial support for N1SDP board Pranav Madhu 2020-07-03 7:02 ` [edk2-platforms][PATCH v3 1/4] Silicon/ARM/N1SoC: Add platform library implementation Pranav Madhu @ 2020-07-03 7:02 ` Pranav Madhu 2020-07-03 7:02 ` [edk2-platforms][PATCH v3 3/4] Silicon/ARM/N1SoC: Implement the PciHostBridgeLib library Pranav Madhu 2020-07-03 7:02 ` [edk2-platforms][PATCH v3 4/4] Platform/ARM/N1SDP: Add initial N1SDP platform support Pranav Madhu 3 siblings, 0 replies; 9+ messages in thread From: Pranav Madhu @ 2020-07-03 7:02 UTC (permalink / raw) To: devel; +Cc: Ard Biesheuvel, Leif Lindholm From: Deepak Pandey <Deepak.Pandey@arm.com> A slave error is generated when host accesses the config space of non-available device or unimplemented function on a given bus. So implement a n1sdp specific PciExpressLib library with a workaround to return 0xffffffff for all such access. Cc: Ard Biesheuvel <ard.biesheuvel@arm.com> Cc: Leif Lindholm <leif@nuviainc.com> Signed-off-by: Pranav Madhu <pranav.madhu@arm.com> diff --git a/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/NeoverseN1SocPciExpressLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/NeoverseN1SocPciExpressLib.inf new file mode 100644 index 000000000000..7154085efc19 --- /dev/null +++ b/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/NeoverseN1SocPciExpressLib.inf @@ -0,0 +1,39 @@ +## @file +# Instance of PCI Express Library using the 256 MB PCI Express MMIO window. +# +# PCI Express Library that uses the 256 MB PCI Express MMIO window to perform +# PCI Configuration cycles. Layers on top of an I/O Library instance. +# +# Copyright (c) 2007 - 2019, Intel Corporation. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = BasePciExpressLib + FILE_GUID = b378dd06-de7f-4e8c-8fb0-5126adfb34bf + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = PciExpressLib + +[Sources] + NeoverseN1SocPciExpressLib.c + +[Packages] + MdePkg/MdePkg.dec + Silicon/ARM/NeoverseN1Soc/NeoverseN1SocPlatform.dec + +[FixedPcd] + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseAddress + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseSize + +[LibraryClasses] + BaseLib + PcdLib + DebugLib + IoLib + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES diff --git a/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/NeoverseN1SocPciExpressLib.c b/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/NeoverseN1SocPciExpressLib.c new file mode 100644 index 000000000000..7433348d7104 --- /dev/null +++ b/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/NeoverseN1SocPciExpressLib.c @@ -0,0 +1,1545 @@ +/** @file +* Functions in this library instance make use of MMIO functions in IoLib to +* access memory mapped PCI configuration space. +* +* All assertions for I/O operations are handled in MMIO functions in the IoLib +* Library. +* +* Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved. +* +* slave error is generated when host accesses the configuration space of +* non-available device or unimplemented function on a given bus. So this +* library introduces a workaround using CheckBdfValidity(), to return +* 0xffffffff for all such access. +* +* Copyright (c) 2020, ARM Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include <Base.h> +#include <Library/BaseLib.h> +#include <Library/PciExpressLib.h> +#include <Library/IoLib.h> +#include <Library/DebugLib.h> +#include <Library/PcdLib.h> +#include <NeoverseN1SocPlatform.h> + +/** + Assert the validity of a PCI address. A valid PCI address should contain 1's + only in the low 32 bits. + + @param A The address to validate. +**/ +#define ASSERT_INVALID_PCI_ADDRESS(A) \ + ASSERT (((A) & ~0xffffffff) == 0) + +#define EFI_PCIE_ADDRESS(bus, dev, func, reg) \ + (UINT64) ( \ + (((UINTN) bus) << 20) | \ + (((UINTN) dev) << 15) | \ + (((UINTN) func) << 12) | \ + (((UINTN) (reg)) < 4096 ? ((UINTN) (reg)) : (UINT64) (LShiftU64 ((UINT64) (reg), 32)))) + +#define GET_PCIE_BASE_ADDRESS(Address) (Address & 0xF8000000) + +/* Root port Entry, BDF Entries Count */ +#define BDF_TABLE_ENTRY_SIZE 4 +#define BDF_TABLE_HEADER_COUNT 2 +#define BDF_TABLE_HEADER_SIZE 8 + +/* BDF table offsets for PCIe */ +#define PCIE_BDF_TABLE_OFFSET 0 + +#define GET_BUS_NUM(Address) ((Address>>20) & 0x7f) +#define GET_DEV_NUM(Address) ((Address>>15) & 0x1f) +#define GET_FUNC_NUM(Address) ((Address>>12) & 0x07) +#define GET_REG_NUM(Address) ((Address) & 0xFFF) + +/** + BDF Table structure : (Header + BDF Entries) + ------------------- + ROOT PORT ADDRESS + BDF ENTRIES COUNT + BDF ENTRY 0 + BDF ENTRY 1 + BDF ENTRY 2 + BDF ENTRY 3 + BDF ENTRY 4 + ... + BDF ENTRY N + ------------------ +**/ + +UINTN DummyPciData = 0xffffffff; + +/** + Registers a PCI device so PCI configuration registers may be accessed after + SetVirtualAddressMap(). + + Registers the PCI device specified by Address so all the PCI configuration + registers associated with that PCI device may be accessed after SetVirtualAddressMap() + is called. + + If Address > 0x0FFFFFFF, then ASSERT(). + + @param Address The address that encodes the PCI Bus, Device, Function and + Register. + + @retval RETURN_SUCCESS The PCI device was registered for runtime access. + @retval RETURN_UNSUPPORTED An attempt was made to call this function + after ExitBootServices(). + @retval RETURN_UNSUPPORTED The resources required to access the PCI device + at runtime could not be mapped. + @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to + complete the registration. +**/ +RETURN_STATUS +EFIAPI +PciExpressRegisterForRuntimeAccess ( + IN UINTN Address + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + return RETURN_UNSUPPORTED; +} + +/** + Checks if the incoming PCI address is a valid BDF address. + + SCP performs the initial bus scan and prepares a table of valid BDF addresses + and shares them through non-trusted SRAM. This function validates if the PCI + address from any PCI request falls within the table of valid entries. If not, + this function will return false. This is a workaround to avoid bus fault that + happens when accessing unavailable PCI device due to RTL bug. + + @param Address The address that encodes the PCI Bus, Device, Function and + Register. + + @return The base address of PCI Express. +**/ +STATIC +BOOLEAN +CheckBdfValidity ( + IN UINTN Address + ) +{ + UINT8 Bus, Device, Function; + UINTN BdfCount, BdfValue; + UINTN BdfEntry; + UINTN Count; + UINTN TableBase; + UINTN PciAddress; + + Bus = GET_BUS_NUM (Address); + Device = GET_DEV_NUM (Address); + Function = GET_FUNC_NUM (Address); + + PciAddress = EFI_PCIE_ADDRESS (Bus, Device, Function, 0); + + if (GET_PCIE_BASE_ADDRESS (Address) == FixedPcdGet64 (PcdPciExpressBaseAddress)) { + TableBase = NEOVERSEN1SOC_NON_SECURE_SRAM_BASE + PCIE_BDF_TABLE_OFFSET; + } + + BdfCount = MmioRead32 (TableBase + BDF_TABLE_ENTRY_SIZE); + BdfEntry = TableBase + BDF_TABLE_HEADER_SIZE; + + /* Skip the header & check remaining entry */ + for (Count = 0; Count < BdfCount; Count++, BdfEntry += BDF_TABLE_ENTRY_SIZE) { + BdfValue = MmioRead32 (BdfEntry); + if (BdfValue == PciAddress) { + return TRUE; + } + } + + return FALSE; +} + +/** + Gets the base address of PCI Express. + + This internal functions retrieves PCI Express Base Address via a PCD entry. + + @param Address The address that encodes the PCI Bus, Device, Function and + Register. + + @return The base address of PCI Express. +**/ +STATIC +VOID* +GetPciExpressAddress ( + IN UINTN Address + ) +{ + UINT8 Bus, Device, Function; + UINT16 Register; + UINTN ConvAddress; + + // Get the EFI notation + Bus = GET_BUS_NUM (Address); + Device = GET_DEV_NUM (Address); + Function = GET_FUNC_NUM (Address); + Register = GET_REG_NUM (Address); + + if ((Bus == 0) && (Device == 0) && (Function == 0)) { + ConvAddress = PcdGet32 (PcdPcieRootPortConfigBaseAddress + + EFI_PCIE_ADDRESS (Bus, Device, Function, Register)); + } else { + ConvAddress = PcdGet64 (PcdPciExpressBaseAddress + + EFI_PCIE_ADDRESS (Bus, Device, Function, Register)); + } + + if (!((Bus == 0) && (Device == 0) && (Function == 0))) { + if (!CheckBdfValidity(Address)) { + ConvAddress = (UINTN) &DummyPciData; + } + } + + return (VOID*)ConvAddress; +} + +/** + Reads an 8-bit PCI configuration register. + + Reads and returns the 8-bit PCI configuration register specified by Address. + This function must guarantee that all PCI read and write operations are + serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + + @param Address The address that encodes the PCI Bus, Device, Function and + Register. + + @return The read value from the PCI configuration register. +**/ +UINT8 +EFIAPI +PciExpressRead8 ( + IN UINTN Address + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + return MmioRead8 ((UINTN) GetPciExpressAddress (Address)); +} + +/** + Writes an 8-bit PCI configuration register. + + Writes the 8-bit PCI configuration register specified by Address with the + value specified by Value. Value is returned. This function must guarantee + that all PCI read and write operations are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + + @param Address The address that encodes the PCI Bus, Device, Function and + Register. + @param Value The value to write. + + @return The value written to the PCI configuration register. +**/ +UINT8 +EFIAPI +PciExpressWrite8 ( + IN UINTN Address, + IN UINT8 Value + ) +{ + UINT32 Data; + UINT8 Offset; + UINT8 Bus; + UINT8 Device; + UINT8 Function; + + ASSERT_INVALID_PCI_ADDRESS (Address); + + // Get the EFI notation + Bus = GET_BUS_NUM (Address); + Device = GET_DEV_NUM (Address); + Function = GET_FUNC_NUM (Address); + + if( (Bus == 0) && (Device == 0) && (Function == 0) ) { + Data = MmioRead32 ((UINTN) GetPciExpressAddress (Address & 0xFFFFFFFC)); + Offset = Address & 0x3; + Data |= (Value << (8 * Offset)); + MmioWrite32 ((UINTN) GetPciExpressAddress (Address & 0xFFFFFFFC), Data); + } else { + MmioWrite8 ((UINTN) GetPciExpressAddress (Address), Value); + } + return Value; +} + +/** + Performs a bitwise OR of an 8-bit PCI configuration register with + an 8-bit value. + + Reads the 8-bit PCI configuration register specified by Address, performs a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 8-bit PCI configuration register + specified by Address. The value written to the PCI configuration register is + returned. This function must guarantee that all PCI read and write operations + are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + + @param Address The address that encodes the PCI Bus, Device, Function and + Register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. +**/ +UINT8 +EFIAPI +PciExpressOr8 ( + IN UINTN Address, + IN UINT8 OrData + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + return MmioOr8 ((UINTN) GetPciExpressAddress (Address), OrData); +} + +/** + Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit + value. + + Reads the 8-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, and + writes the result to the 8-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + + @param Address The address that encodes the PCI Bus, Device, Function and + Register. + @param AndData The value to AND with the PCI configuration register. + + @return The value written back to the PCI configuration register. +**/ +UINT8 +EFIAPI +PciExpressAnd8 ( + IN UINTN Address, + IN UINT8 AndData + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + return MmioAnd8 ((UINTN) GetPciExpressAddress (Address), AndData); +} + +/** + Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit + value, followed a bitwise OR with another 8-bit value. + + Reads the 8-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, + performs a bitwise OR between the result of the AND operation and + the value specified by OrData, and writes the result to the 8-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that all PCI + read and write operations are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + + @param Address The address that encodes the PCI Bus, Device, Function and + Register. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. +**/ +UINT8 +EFIAPI +PciExpressAndThenOr8 ( + IN UINTN Address, + IN UINT8 AndData, + IN UINT8 OrData + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + return MmioAndThenOr8 ( + (UINTN) GetPciExpressAddress (Address), + AndData, + OrData + ); +} + +/** + Reads a bit field of a PCI configuration register. + + Reads the bit field in an 8-bit PCI configuration register. The bit field is + specified by the StartBit and the EndBit. The value of the bit field is + returned. + + If Address > 0x0FFFFFFF, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param Address The PCI configuration register to read. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + + @return The value of the bit field read from the PCI configuration register. +**/ +UINT8 +EFIAPI +PciExpressBitFieldRead8 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + return MmioBitFieldRead8 ( + (UINTN) GetPciExpressAddress (Address), + StartBit, + EndBit + ); +} + +/** + Writes a bit field to a PCI configuration register. + + Writes Value to the bit field of the PCI configuration register. The bit + field is specified by the StartBit and the EndBit. All other bits in the + destination PCI configuration register are preserved. The new value of the + 8-bit register is returned. + + If Address > 0x0FFFFFFF, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + @param Value The new value of the bit field. + + @return The value written back to the PCI configuration register. +**/ +UINT8 +EFIAPI +PciExpressBitFieldWrite8 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 Value + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + return MmioBitFieldWrite8 ( + (UINTN) GetPciExpressAddress (Address), + StartBit, + EndBit, + Value + ); +} + +/** + Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and + writes the result back to the bit field in the 8-bit port. + + Reads the 8-bit PCI configuration register specified by Address, performs a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 8-bit PCI configuration register + specified by Address. The value written to the PCI configuration register is + returned. This function must guarantee that all PCI read and write operations + are serialized. Extra left bits in OrData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. +**/ +UINT8 +EFIAPI +PciExpressBitFieldOr8 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 OrData + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + return MmioBitFieldOr8 ( + (UINTN) GetPciExpressAddress (Address), + StartBit, + EndBit, + OrData + ); +} + +/** + Reads a bit field in an 8-bit PCI configuration register, performs a bitwise + AND, and writes the result back to the bit field in the 8-bit register. + + Reads the 8-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, and + writes the result to the 8-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. Extra left bits in AndData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + @param AndData The value to AND with the PCI configuration register. + + @return The value written back to the PCI configuration register. +**/ +UINT8 +EFIAPI +PciExpressBitFieldAnd8 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 AndData + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + return MmioBitFieldAnd8 ( + (UINTN) GetPciExpressAddress (Address), + StartBit, + EndBit, + AndData + ); +} + +/** + Reads a bit field in an 8-bit port, performs a bitwise AND followed by a + bitwise OR, and writes the result back to the bit field in the + 8-bit port. + + Reads the 8-bit PCI configuration register specified by Address, performs a + bitwise AND followed by a bitwise OR between the read result and + the value specified by AndData, and writes the result to the 8-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that all PCI + read and write operations are serialized. Extra left bits in both AndData and + OrData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. +**/ +UINT8 +EFIAPI +PciExpressBitFieldAndThenOr8 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 AndData, + IN UINT8 OrData + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + return MmioBitFieldAndThenOr8 ( + (UINTN) GetPciExpressAddress (Address), + StartBit, + EndBit, + AndData, + OrData + ); +} + +/** + Reads a 16-bit PCI configuration register. + + Reads and returns the 16-bit PCI configuration register specified by Address. + This function must guarantee that all PCI read and write operations are + serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Bus, Device, Function and + Register. + + @return The read value from the PCI configuration register. +**/ +UINT16 +EFIAPI +PciExpressRead16 ( + IN UINTN Address + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + return MmioRead16 ((UINTN) GetPciExpressAddress (Address)); +} + +/** + Writes a 16-bit PCI configuration register. + + Writes the 16-bit PCI configuration register specified by Address with the + value specified by Value. Value is returned. This function must guarantee + that all PCI read and write operations are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Bus, Device, Function and + Register. + @param Value The value to write. + + @return The value written to the PCI configuration register. +**/ +UINT16 +EFIAPI +PciExpressWrite16 ( + IN UINTN Address, + IN UINT16 Value + ) +{ + UINT32 Data; + UINT8 Offset; + UINT8 Bus; + UINT8 Device; + UINT8 Function; + + ASSERT_INVALID_PCI_ADDRESS (Address); + + // Get the EFI notation + Bus = GET_BUS_NUM (Address); + Device = GET_DEV_NUM (Address); + Function = GET_FUNC_NUM (Address); + + if( (Bus == 0) && (Device == 0) && (Function == 0) ) { + Data = MmioRead32 ((UINTN) GetPciExpressAddress (Address & 0xFFFFFFFC)); + Offset = Address & 0x3; + Data |= (Value << (8 * Offset)); + MmioWrite32 ((UINTN) GetPciExpressAddress (Address & 0xFFFFFFFC), Data); + } else { + MmioWrite16 ((UINTN) GetPciExpressAddress (Address), Value); + } + return Value; +} + +/** + Performs a bitwise OR of a 16-bit PCI configuration register with + a 16-bit value. + + Reads the 16-bit PCI configuration register specified by Address, performs a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 16-bit PCI configuration register + specified by Address. The value written to the PCI configuration register is + returned. This function must guarantee that all PCI read and write operations + are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Bus, Device, Function and + Register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. +**/ +UINT16 +EFIAPI +PciExpressOr16 ( + IN UINTN Address, + IN UINT16 OrData + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + return MmioOr16 ((UINTN) GetPciExpressAddress (Address), OrData); +} + +/** + Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit + value. + + Reads the 16-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, and + writes the result to the 16-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Bus, Device, Function and + Register. + @param AndData The value to AND with the PCI configuration register. + + @return The value written back to the PCI configuration register. +**/ +UINT16 +EFIAPI +PciExpressAnd16 ( + IN UINTN Address, + IN UINT16 AndData + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + return MmioAnd16 ((UINTN) GetPciExpressAddress (Address), AndData); +} + +/** + Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit + value, followed a bitwise OR with another 16-bit value. + + Reads the 16-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, + performs a bitwise OR between the result of the AND operation and + the value specified by OrData, and writes the result to the 16-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that all PCI + read and write operations are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Bus, Device, Function and + Register. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. +**/ +UINT16 +EFIAPI +PciExpressAndThenOr16 ( + IN UINTN Address, + IN UINT16 AndData, + IN UINT16 OrData + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + return MmioAndThenOr16 ( + (UINTN) GetPciExpressAddress (Address), + AndData, + OrData + ); +} + +/** + Reads a bit field of a PCI configuration register. + + Reads the bit field in a 16-bit PCI configuration register. The bit field is + specified by the StartBit and the EndBit. The value of the bit field is + returned. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param Address The PCI configuration register to read. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + + @return The value of the bit field read from the PCI configuration register. +**/ +UINT16 +EFIAPI +PciExpressBitFieldRead16 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + return MmioBitFieldRead16 ( + (UINTN) GetPciExpressAddress (Address), + StartBit, + EndBit + ); +} + +/** + Writes a bit field to a PCI configuration register. + + Writes Value to the bit field of the PCI configuration register. The bit + field is specified by the StartBit and the EndBit. All other bits in the + destination PCI configuration register are preserved. The new value of the + 16-bit register is returned. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + @param Value The new value of the bit field. + + @return The value written back to the PCI configuration register. +**/ +UINT16 +EFIAPI +PciExpressBitFieldWrite16 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 Value + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + return MmioBitFieldWrite16 ( + (UINTN) GetPciExpressAddress (Address), + StartBit, + EndBit, + Value + ); +} + +/** + Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and + writes the result back to the bit field in the 16-bit port. + + Reads the 16-bit PCI configuration register specified by Address, performs a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 16-bit PCI configuration register + specified by Address. The value written to the PCI configuration register is + returned. This function must guarantee that all PCI read and write operations + are serialized. Extra left bits in OrData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. +**/ +UINT16 +EFIAPI +PciExpressBitFieldOr16 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 OrData + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + return MmioBitFieldOr16 ( + (UINTN) GetPciExpressAddress (Address), + StartBit, + EndBit, + OrData + ); +} + +/** + Reads a bit field in a 16-bit PCI configuration register, performs a bitwise + AND, and writes the result back to the bit field in the 16-bit register. + + Reads the 16-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, and + writes the result to the 16-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. Extra left bits in AndData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + @param AndData The value to AND with the PCI configuration register. + + @return The value written back to the PCI configuration register. +**/ +UINT16 +EFIAPI +PciExpressBitFieldAnd16 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 AndData + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + return MmioBitFieldAnd16 ( + (UINTN) GetPciExpressAddress (Address), + StartBit, + EndBit, + AndData + ); +} + +/** + Reads a bit field in a 16-bit port, performs a bitwise AND followed by a + bitwise OR, and writes the result back to the bit field in the + 16-bit port. + + Reads the 16-bit PCI configuration register specified by Address, performs a + bitwise AND followed by a bitwise OR between the read result and + the value specified by AndData, and writes the result to the 16-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that all PCI + read and write operations are serialized. Extra left bits in both AndData and + OrData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. +**/ +UINT16 +EFIAPI +PciExpressBitFieldAndThenOr16 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 AndData, + IN UINT16 OrData + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + return MmioBitFieldAndThenOr16 ( + (UINTN) GetPciExpressAddress (Address), + StartBit, + EndBit, + AndData, + OrData + ); +} + +/** + Reads a 32-bit PCI configuration register. + + Reads and returns the 32-bit PCI configuration register specified by Address. + This function must guarantee that all PCI read and write operations are + serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Bus, Device, Function and + Register. + + @return The read value from the PCI configuration register. +**/ +UINT32 +EFIAPI +PciExpressRead32 ( + IN UINTN Address + ) +{ + UINTN address; + UINT32 value; + ASSERT_INVALID_PCI_ADDRESS (Address); + address = (UINTN) GetPciExpressAddress (Address); + value = MmioRead32 (address); + return value; +} + +/** + Writes a 32-bit PCI configuration register. + + Writes the 32-bit PCI configuration register specified by Address with the + value specified by Value. Value is returned. This function must guarantee + that all PCI read and write operations are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Bus, Device, Function and + Register. + @param Value The value to write. + + @return The value written to the PCI configuration register. +**/ +UINT32 +EFIAPI +PciExpressWrite32 ( + IN UINTN Address, + IN UINT32 Value + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + return MmioWrite32 ((UINTN) GetPciExpressAddress (Address), Value); +} + +/** + Performs a bitwise OR of a 32-bit PCI configuration register with + a 32-bit value. + + Reads the 32-bit PCI configuration register specified by Address, performs a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 32-bit PCI configuration register + specified by Address. The value written to the PCI configuration register is + returned. This function must guarantee that all PCI read and write operations + are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Bus, Device, Function and + Register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. +**/ +UINT32 +EFIAPI +PciExpressOr32 ( + IN UINTN Address, + IN UINT32 OrData + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + return MmioOr32 ((UINTN) GetPciExpressAddress (Address), OrData); +} + +/** + Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit + value. + + Reads the 32-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, and + writes the result to the 32-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Bus, Device, Function and + Register. + @param AndData The value to AND with the PCI configuration register. + + @return The value written back to the PCI configuration register. +**/ +UINT32 +EFIAPI +PciExpressAnd32 ( + IN UINTN Address, + IN UINT32 AndData + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + return MmioAnd32 ((UINTN) GetPciExpressAddress (Address), AndData); +} + +/** + Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit + value, followed a bitwise OR with another 32-bit value. + + Reads the 32-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, + performs a bitwise OR between the result of the AND operation and + the value specified by OrData, and writes the result to the 32-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that all PCI + read and write operations are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Bus, Device, Function and + Register. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. +**/ +UINT32 +EFIAPI +PciExpressAndThenOr32 ( + IN UINTN Address, + IN UINT32 AndData, + IN UINT32 OrData + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + return MmioAndThenOr32 ( + (UINTN) GetPciExpressAddress (Address), + AndData, + OrData + ); +} + +/** + Reads a bit field of a PCI configuration register. + + Reads the bit field in a 32-bit PCI configuration register. The bit field is + specified by the StartBit and the EndBit. The value of the bit field is + returned. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param Address The PCI configuration register to read. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + + @return The value of the bit field read from the PCI configuration register. +**/ +UINT32 +EFIAPI +PciExpressBitFieldRead32 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + return MmioBitFieldRead32 ( + (UINTN) GetPciExpressAddress (Address), + StartBit, + EndBit + ); +} + +/** + Writes a bit field to a PCI configuration register. + + Writes Value to the bit field of the PCI configuration register. The bit + field is specified by the StartBit and the EndBit. All other bits in the + destination PCI configuration register are preserved. The new value of the + 32-bit register is returned. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + @param Value The new value of the bit field. + + @return The value written back to the PCI configuration register. +**/ +UINT32 +EFIAPI +PciExpressBitFieldWrite32 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 Value + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + return MmioBitFieldWrite32 ( + (UINTN) GetPciExpressAddress (Address), + StartBit, + EndBit, + Value + ); +} + +/** + Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and + writes the result back to the bit field in the 32-bit port. + + Reads the 32-bit PCI configuration register specified by Address, performs a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 32-bit PCI configuration register + specified by Address. The value written to the PCI configuration register is + returned. This function must guarantee that all PCI read and write operations + are serialized. Extra left bits in OrData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. +**/ +UINT32 +EFIAPI +PciExpressBitFieldOr32 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 OrData + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + return MmioBitFieldOr32 ( + (UINTN) GetPciExpressAddress (Address), + StartBit, + EndBit, + OrData + ); +} + +/** + Reads a bit field in a 32-bit PCI configuration register, performs a bitwise + AND, and writes the result back to the bit field in the 32-bit register. + + Reads the 32-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, and + writes the result to the 32-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. Extra left bits in AndData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + @param AndData The value to AND with the PCI configuration register. + + @return The value written back to the PCI configuration register. +**/ +UINT32 +EFIAPI +PciExpressBitFieldAnd32 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 AndData + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + return MmioBitFieldAnd32 ( + (UINTN) GetPciExpressAddress (Address), + StartBit, + EndBit, + AndData + ); +} + +/** + Reads a bit field in a 32-bit port, performs a bitwise AND followed by a + bitwise OR, and writes the result back to the bit field in the + 32-bit port. + + Reads the 32-bit PCI configuration register specified by Address, performs a + bitwise AND followed by a bitwise OR between the read result and + the value specified by AndData, and writes the result to the 32-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that all PCI + read and write operations are serialized. Extra left bits in both AndData and + OrData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. +**/ +UINT32 +EFIAPI +PciExpressBitFieldAndThenOr32 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 AndData, + IN UINT32 OrData + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + return MmioBitFieldAndThenOr32 ( + (UINTN) GetPciExpressAddress (Address), + StartBit, + EndBit, + AndData, + OrData + ); +} + +/** + Reads a range of PCI configuration registers into a caller supplied buffer. + + Reads the range of PCI configuration registers specified by StartAddress and + Size into the buffer specified by Buffer. This function only allows the PCI + configuration registers from a single PCI function to be read. Size is + returned. When possible 32-bit PCI configuration read cycles are used to read + from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit + and 16-bit PCI configuration read cycles may be used at the beginning and the + end of the range. + + If StartAddress > 0x0FFFFFFF, then ASSERT(). + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). + If Size > 0 and Buffer is NULL, then ASSERT(). + + @param StartAddress The starting address that encodes the PCI Bus, Device, + Function and Register. + @param Size The size in bytes of the transfer. + @param Buffer The pointer to a buffer receiving the data read. + + @return Size read data from StartAddress. +**/ +UINTN +EFIAPI +PciExpressReadBuffer ( + IN UINTN StartAddress, + IN UINTN Size, + OUT VOID *Buffer + ) +{ + UINTN ReturnValue; + + ASSERT_INVALID_PCI_ADDRESS (StartAddress); + ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000); + + if (Size == 0) { + return Size; + } + + ASSERT (Buffer != NULL); + + // + // Save Size for return + // + ReturnValue = Size; + + if ((StartAddress & 1) != 0) { + // + // Read a byte if StartAddress is byte aligned + // + *(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress); + StartAddress += sizeof (UINT8); + Size -= sizeof (UINT8); + Buffer = (UINT8*)Buffer + 1; + } + + if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) { + // + // Read a word if StartAddress is word aligned + // + WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (StartAddress)); + + StartAddress += sizeof (UINT16); + Size -= sizeof (UINT16); + Buffer = (UINT16*)Buffer + 1; + } + + while (Size >= sizeof (UINT32)) { + // + // Read as many double words as possible + // + WriteUnaligned32 ((UINT32 *) Buffer, (UINT32) PciExpressRead32 (StartAddress)); + + StartAddress += sizeof (UINT32); + Size -= sizeof (UINT32); + Buffer = (UINT32*)Buffer + 1; + } + + if (Size >= sizeof (UINT16)) { + // + // Read the last remaining word if exist + // + WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (StartAddress)); + StartAddress += sizeof (UINT16); + Size -= sizeof (UINT16); + Buffer = (UINT16*)Buffer + 1; + } + + if (Size >= sizeof (UINT8)) { + // + // Read the last remaining byte if exist + // + *(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress); + } + + return ReturnValue; +} + +/** + Copies the data in a caller supplied buffer to a specified range of PCI + configuration space. + + Writes the range of PCI configuration registers specified by StartAddress and + Size from the buffer specified by Buffer. This function only allows the PCI + configuration registers from a single PCI function to be written. Size is + returned. When possible 32-bit PCI configuration write cycles are used to + write from StartAdress to StartAddress + Size. Due to alignment restrictions, + 8-bit and 16-bit PCI configuration write cycles may be used at the beginning + and the end of the range. + + If StartAddress > 0x0FFFFFFF, then ASSERT(). + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). + If Size > 0 and Buffer is NULL, then ASSERT(). + + @param StartAddress The starting address that encodes the PCI Bus, Device, + Function and Register. + @param Size The size in bytes of the transfer. + @param Buffer The pointer to a buffer containing the data to write. + + @return Size written to StartAddress. +**/ +UINTN +EFIAPI +PciExpressWriteBuffer ( + IN UINTN StartAddress, + IN UINTN Size, + IN VOID *Buffer + ) +{ + UINTN ReturnValue; + + ASSERT_INVALID_PCI_ADDRESS (StartAddress); + ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000); + + if (Size == 0) { + return 0; + } + + ASSERT (Buffer != NULL); + + // + // Save Size for return + // + ReturnValue = Size; + + if ((StartAddress & 1) != 0) { + // + // Write a byte if StartAddress is byte aligned + // + PciExpressWrite8 (StartAddress, *(UINT8*)Buffer); + StartAddress += sizeof (UINT8); + Size -= sizeof (UINT8); + Buffer = (UINT8*)Buffer + 1; + } + + if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) { + // + // Write a word if StartAddress is word aligned + // + PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer)); + StartAddress += sizeof (UINT16); + Size -= sizeof (UINT16); + Buffer = (UINT16*)Buffer + 1; + } + + while (Size >= sizeof (UINT32)) { + // + // Write as many double words as possible + // + PciExpressWrite32 (StartAddress, ReadUnaligned32 ((UINT32*)Buffer)); + StartAddress += sizeof (UINT32); + Size -= sizeof (UINT32); + Buffer = (UINT32*)Buffer + 1; + } + + if (Size >= sizeof (UINT16)) { + // + // Write the last remaining word if exist + // + PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer)); + StartAddress += sizeof (UINT16); + Size -= sizeof (UINT16); + Buffer = (UINT16*)Buffer + 1; + } + + if (Size >= sizeof (UINT8)) { + // + // Write the last remaining byte if exist + // + PciExpressWrite8 (StartAddress, *(UINT8*)Buffer); + } + + return ReturnValue; +} -- 2.7.4 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [edk2-platforms][PATCH v3 3/4] Silicon/ARM/N1SoC: Implement the PciHostBridgeLib library 2020-07-03 7:02 [edk2-platforms][PATCH v3 0/4] Platform: Add initial support for N1SDP board Pranav Madhu 2020-07-03 7:02 ` [edk2-platforms][PATCH v3 1/4] Silicon/ARM/N1SoC: Add platform library implementation Pranav Madhu 2020-07-03 7:02 ` [edk2-platforms][PATCH v3 2/4] Silicon/ARM/N1SoC: Implement Neoverse N1 Soc specific PciExpressLib Pranav Madhu @ 2020-07-03 7:02 ` Pranav Madhu 2020-07-03 7:02 ` [edk2-platforms][PATCH v3 4/4] Platform/ARM/N1SDP: Add initial N1SDP platform support Pranav Madhu 3 siblings, 0 replies; 9+ messages in thread From: Pranav Madhu @ 2020-07-03 7:02 UTC (permalink / raw) To: devel; +Cc: Ard Biesheuvel, Leif Lindholm From: Deepak Pandey <Deepak.Pandey@arm.com> Neoverse N1 SoC includes a PCIe root complex to which a AHCI, GbE and USB controllers are attached as an endpoint. So implement the PciHostBridgeLib glue layer and enable support for PCIe controller and all the devices connected over the PCIe bus. Cc: Ard Biesheuvel <ard.biesheuvel@arm.com> Cc: Leif Lindholm <leif@nuviainc.com> Signed-off-by: Pranav Madhu <pranav.madhu@arm.com> diff --git a/Silicon/ARM/NeoverseN1Soc/NeoverseN1SocPlatform.dec b/Silicon/ARM/NeoverseN1Soc/NeoverseN1SocPlatform.dec index dba49e6489c0..da2443fcc52f 100644 --- a/Silicon/ARM/NeoverseN1Soc/NeoverseN1SocPlatform.dec +++ b/Silicon/ARM/NeoverseN1Soc/NeoverseN1SocPlatform.dec @@ -23,5 +23,24 @@ [Guids.common] gArmNeoverseN1SocTokenSpaceGuid = { 0xab93eb78, 0x60d7, 0x4099, { 0xac, 0xeb, 0x6d, 0xb5, 0x02, 0x58, 0x7c, 0x24 } } [PcdsFixedAtBuild] + # PCIe + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusCount|18|UINT32|0x00000002 + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax|17|UINT32|0x00000003 + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin|0|UINT32|0x00000004 + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoBase|0x0|UINT32|0x00000005 + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoMaxBase|0x00FFFFFF|UINT32|0x00000006 + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoSize|0x01000000|UINT32|0x00000007 + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoTranslation|0x75200000|UINT32|0x00000008 + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Base|0x71200000|UINT32|0x00000009 + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32MaxBase|0x751FFFFF|UINT32|0x0000000A + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Size|0x04000000|UINT32|0x0000000B + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Translation|0x0|UINT32|0x0000000C + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Base|0x0900000000|UINT64|0x0000000D + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64MaxBase|0x28FFFFFFFF|UINT64|0x0000000E + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Size|0x2000000000|UINT64|0x0000000F + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Translation|0x0|UINT64|0x00000010 + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseAddress|0x60000000|UINT32|0x00000011 + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseSize|0x00001000|UINT32|0x00000012 + # Secondary DDR memory gArmNeoverseN1SocTokenSpaceGuid.PcdDramBlock2Base|0|UINT64|0x00000001 diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf new file mode 100644 index 000000000000..7327a4d7337e --- /dev/null +++ b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf @@ -0,0 +1,49 @@ +## @file +# PCI Host Bridge Library instance for ARM Neoverse N1 platform. +# +# Copyright (c) 2019 - 2020, ARM Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = PciHostBridgeLib + FILE_GUID = daa340e1-89dd-4bd2-b645-ebe75e541f8b + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + LIBRARY_CLASS = PciHostBridgeLib|DXE_DRIVER + +[Sources] + PciHostBridgeLib.c + +[Packages] + ArmPkg/ArmPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/ARM/NeoverseN1Soc/NeoverseN1SocPlatform.dec + +[LibraryClasses] + BaseLib + DebugLib + DevicePathLib + IoLib + MemoryAllocationLib + UefiBootServicesTableLib + +[FixedPcd] + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoBase + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoSize + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Base + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Size + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Base + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Size + +[Protocols] + gEfiCpuIo2ProtocolGuid + +[Depex] + gEfiCpuIo2ProtocolGuid diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf index b2ea10756071..b8b5a5734ad6 100644 --- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf @@ -29,11 +29,22 @@ [Sources.AARCH64] AArch64/Helper.S | GCC [FixedPcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + gArmTokenSpaceGuid.PcdSystemMemoryBase gArmTokenSpaceGuid.PcdSystemMemorySize gArmTokenSpaceGuid.PcdArmPrimaryCore gArmTokenSpaceGuid.PcdArmPrimaryCoreMask + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Base + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Size + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Base + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Size + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseAddress + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseSize + gArmNeoverseN1SocTokenSpaceGuid.PcdDramBlock2Base [Guids] diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c new file mode 100644 index 000000000000..4038dbf7b7fb --- /dev/null +++ b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c @@ -0,0 +1,187 @@ +/** @file +* PCI Host Bridge Library instance for ARM Neoverse N1 platform +* +* Copyright (c) 2019 - 2020, ARM Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include <PiDxe.h> +#include <Library/DebugLib.h> +#include <Library/DevicePathLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Library/PcdLib.h> +#include <Library/PciHostBridgeLib.h> +#include <Protocol/PciHostBridgeResourceAllocation.h> +#include <Protocol/PciRootBridgeIo.h> + +GLOBAL_REMOVE_IF_UNREFERENCED +STATIC CHAR16 CONST * CONST mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = { + L"Mem", L"I/O", L"Bus" +}; + +#pragma pack (1) +typedef struct { + ACPI_HID_DEVICE_PATH AcpiDevicePath; + EFI_DEVICE_PATH_PROTOCOL EndDevicePath; +} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; +#pragma pack () + +STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] = { + // PCIe + { + { + { + ACPI_DEVICE_PATH, + ACPI_DP, + { + (UINT8)sizeof (ACPI_HID_DEVICE_PATH), + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8) + } + }, + EISA_PNP_ID (0x0A08), // PCIe + 0 + }, + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + END_DEVICE_PATH_LENGTH, + 0 + } + } + } +}; + +STATIC PCI_ROOT_BRIDGE mPciRootBridge[] = { + { + 0, // Segment + 0, // Supports + 0, // Attributes + TRUE, // DmaAbove4G + FALSE, // NoExtendedConfigSpace + FALSE, // ResourceAssigned + EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttributes + EFI_PCI_HOST_BRIDGE_MEM64_DECODE, + { + // Bus + FixedPcdGet32 (PcdPcieBusMin), + FixedPcdGet32 (PcdPcieBusMax) + }, { + // Io + FixedPcdGet64 (PcdPcieIoBase), + FixedPcdGet64 (PcdPcieIoBase) + FixedPcdGet64 (PcdPcieIoSize) - 1 + }, { + // Mem + FixedPcdGet32 (PcdPcieMmio32Base), + FixedPcdGet32 (PcdPcieMmio32Base) + FixedPcdGet32 (PcdPcieMmio32Size) - 1 + }, { + // MemAbove4G + FixedPcdGet64 (PcdPcieMmio64Base), + FixedPcdGet64 (PcdPcieMmio64Base) + FixedPcdGet64 (PcdPcieMmio64Size) - 1 + }, { + // PMem + MAX_UINT64, + 0 + }, { + // PMemAbove4G + MAX_UINT64, + 0 + }, + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[0] + } +}; + +/** + Return all the root bridge instances in an array. + + @param Count Return the count of root bridge instances. + + @return All the root bridge instances in an array. + The array should be passed into PciHostBridgeFreeRootBridges() + when it's not used. +**/ +PCI_ROOT_BRIDGE * +EFIAPI +PciHostBridgeGetRootBridges ( + UINTN *Count + ) +{ + *Count = ARRAY_SIZE (mPciRootBridge); + return mPciRootBridge; +} + +/** + Free the root bridge instances array returned from PciHostBridgeGetRootBridges(). + + @param Bridges The root bridge instances array. + @param Count The count of the array. +**/ +VOID +EFIAPI +PciHostBridgeFreeRootBridges ( + PCI_ROOT_BRIDGE *Bridges, + UINTN Count + ) +{ +} + +/** + Inform the platform that the resource conflict happens. + + @param HostBridgeHandle Handle of the Host Bridge. + @param Configuration Pointer to PCI I/O and PCI memory resource + descriptors. The Configuration contains the resources + for all the root bridges. The resource for each root + bridge is terminated with END descriptor and an + additional END is appended indicating the end of the + entire resources. The resource descriptor field + values follow the description in + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\ + SubmitResources(). +**/ +VOID +EFIAPI +PciHostBridgeResourceConflict ( + EFI_HANDLE HostBridgeHandle, + VOID *Configuration + ) +{ + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor; + UINTN RootBridgeIndex = 0; + + DEBUG ((DEBUG_ERROR, "PciHostBridge: Resource conflict happened!\n")); + Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration; + + while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) { + DEBUG ((DEBUG_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++)); + + for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) { + ASSERT (Descriptor->ResType < + (sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr) / + sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr[0]) + ) + ); + DEBUG ((DEBUG_ERROR, " %s: Length/Alignment = 0x%lx / 0x%lx\n", + mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType], + Descriptor->AddrLen, Descriptor->AddrRangeMax + )); + if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) { + DEBUG ((DEBUG_ERROR, " Granularity/SpecificFlag = %ld / %02x%s\n", + Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag, + ((Descriptor->SpecificFlag & + EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE + ) != 0) ? L" (Prefetchable)" : L"" + )); + } + } + // + // Skip the END descriptor for root bridge + // + ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR); + Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)( + (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1 + ); + } +} diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c index 0234748fa72e..2c2e5a67e8ec 100644 --- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c @@ -13,7 +13,7 @@ #include <NeoverseN1SocPlatform.h> // The total number of descriptors, including the final "end-of-table" descriptor. -#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 9 +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 13 /** Returns the Virtual Memory Map of the platform. @@ -89,6 +89,32 @@ ArmPlatformGetVirtualMemoryMap ( VirtualMemoryTable[Index].Length = NEOVERSEN1SOC_NON_SECURE_SRAM_SZ; VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED; + // PCIe RC Configuration Space + VirtualMemoryTable[++Index].PhysicalBase = PcdGet32 (PcdPcieRootPortConfigBaseAddress); + VirtualMemoryTable[Index].VirtualBase = PcdGet32 (PcdPcieRootPortConfigBaseAddress); + VirtualMemoryTable[Index].Length = PcdGet32 (PcdPcieRootPortConfigBaseSize); + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + // PCIe ECAM Configuration Space + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdPciExpressBaseAddress); + VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdPciExpressBaseAddress); + VirtualMemoryTable[Index].Length = (FixedPcdGet32 (PcdPcieBusMax) - + FixedPcdGet32 (PcdPcieBusMin) + 1) * + SIZE_1MB; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + // PCIe MMIO32 Memory Space + VirtualMemoryTable[++Index].PhysicalBase = PcdGet32 (PcdPcieMmio32Base); + VirtualMemoryTable[Index].VirtualBase = PcdGet32 (PcdPcieMmio32Base); + VirtualMemoryTable[Index].Length = PcdGet32 (PcdPcieMmio32Size); + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + // PCIe MMIO64 Memory Space + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdPcieMmio64Base); + VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdPcieMmio64Base); + VirtualMemoryTable[Index].Length = PcdGet64 (PcdPcieMmio64Size); + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + // SubSystem Pheripherals - UART0 VirtualMemoryTable[++Index].PhysicalBase = NEOVERSEN1SOC_UART0_BASE; VirtualMemoryTable[Index].VirtualBase = NEOVERSEN1SOC_UART0_BASE; -- 2.7.4 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [edk2-platforms][PATCH v3 4/4] Platform/ARM/N1SDP: Add initial N1SDP platform support 2020-07-03 7:02 [edk2-platforms][PATCH v3 0/4] Platform: Add initial support for N1SDP board Pranav Madhu ` (2 preceding siblings ...) 2020-07-03 7:02 ` [edk2-platforms][PATCH v3 3/4] Silicon/ARM/N1SoC: Implement the PciHostBridgeLib library Pranav Madhu @ 2020-07-03 7:02 ` Pranav Madhu 3 siblings, 0 replies; 9+ messages in thread From: Pranav Madhu @ 2020-07-03 7:02 UTC (permalink / raw) To: devel; +Cc: Ard Biesheuvel, Leif Lindholm From: Deepak Pandey <Deepak.Pandey@arm.com> Neoverse N1 System Development Platform (N1SDP) is an infrastructure segment development platform. It includes a Neoverse N1 SoC and an IOFPGA that provides access to low-bandwidth peripherals. It also enables development of CCIX-enabled FPGA accelerators. Cc: Ard Biesheuvel <ard.biesheuvel@arm.com> Cc: Leif Lindholm <leif@nuviainc.com> Signed-off-by: Pranav Madhu <pranav.madhu@arm.com> diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc new file mode 100644 index 000000000000..9925aa790f20 --- /dev/null +++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc @@ -0,0 +1,245 @@ +# +# Copyright (c) 2018 - 2020, ARM Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = n1sdp + PLATFORM_GUID = 9af67d31-7de8-4a71-a9a8-a597a27659ce + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x0001001B + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Platform/ARM/N1Sdp/N1SdpPlatform.fdf + BUILD_NUMBER = 1 + +!include Platform/ARM/VExpressPkg/ArmVExpress.dsc.inc + +[LibraryClasses.common] + ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf + ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf + ArmPlatformLib|Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf + BasePathLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf + UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf + +[LibraryClasses.common.SEC] + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf + PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf + +[LibraryClasses.common.PEI_CORE, LibraryClasses.common.PEIM] + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf + PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf + ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibNull.inf + +[LibraryClasses.common.PEI_CORE] + PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf + +[LibraryClasses.common.PEIM] + PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf + +[LibraryClasses.common.DXE_CORE] + DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf + HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf + MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + +[LibraryClasses.common.DXE_DRIVER] + FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf + PciHostBridgeLib|Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf + PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf + PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf + PciExpressLib|Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/NeoverseN1SocPciExpressLib.inf + +[LibraryClasses.common.DXE_RUNTIME_DRIVER] + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + +[LibraryClasses.common.UEFI_DRIVER, LibraryClasses.common.UEFI_APPLICATION, LibraryClasses.common.DXE_RUNTIME_DRIVER, LibraryClasses.common.DXE_DRIVER] + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +################################################################################ + +[PcdsFeatureFlag.common] + gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE + +[PcdsFixedAtBuild.common] + gArmTokenSpaceGuid.PcdVFPEnabled|1 + + # Stacks for MPCores in Normal World + gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x80000000 + gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x40000 + gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x0 + + # System Memory (2GB) - Reserved Secure Memory (16MB) + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000 + gArmTokenSpaceGuid.PcdSystemMemorySize|(0x80000000 - 0x01000000) + + # Secondary DDR memory + gArmNeoverseN1SocTokenSpaceGuid.PcdDramBlock2Base|0x8080000000 + + # GIC Base Addresses + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x2C000000 + gArmTokenSpaceGuid.PcdGicDistributorBase|0x30000000 + gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x300C0000 + + # PCIe + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x70000000 + gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|24 + gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE + + # PL011 - Serial Terminal + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x2A400000 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0 + gArmPlatformTokenSpaceGuid.PL011UartClkInHz|50000000 + gArmPlatformTokenSpaceGuid.PL011UartInterrupt|95 + + # PL011 Serial Debug UART (DBG2) + gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + gArmPlatformTokenSpaceGuid.PcdSerialDbgUartBaudRate|gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate + gArmPlatformTokenSpaceGuid.PcdSerialDbgUartClkInHz|50000000 + + # SBSA Watchdog + gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|93 + + # PL031 RealTimeClock + gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x1C100000 + + # ARM OS Loader + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|0 + + # ARM Architectural Timer Frequency + gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|100000000 + gEmbeddedTokenSpaceGuid.PcdMetronomeTickPeriod|1000 + gEmbeddedTokenSpaceGuid.PcdTimerPeriod|1000 + + # ARM Cores and Clusters + gArmPlatformTokenSpaceGuid.PcdCoreCount|2 + gArmPlatformTokenSpaceGuid.PcdClusterCount|2 + + # Runtime Variable storage + gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxAuthVariableSize|0x2800 + +################################################################################ +# +# Components Section - list of all EDK II Modules needed by this Platform +# +################################################################################ +[Components.common] + # PEI Phase modules + ArmPkg/Drivers/CpuPei/CpuPei.inf + ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf + ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf + ArmPlatformPkg/PlatformPei/PlatformPeim.inf + MdeModulePkg/Core/Pei/PeiMain.inf + MdeModulePkg/Universal/PCD/Pei/Pcd.inf { + <LibraryClasses> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + } + MdeModulePkg/Universal/Variable/Pei/VariablePei.inf + MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf { + <LibraryClasses> + NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf + } + + # DXE + MdeModulePkg/Core/Dxe/DxeMain.inf { + <LibraryClasses> + NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf + <PcdsFixedAtBuild> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000000F + } + + # Architectural Protocols + ArmPkg/Drivers/CpuDxe/CpuDxe.inf + ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + ArmPkg/Drivers/TimerDxe/TimerDxe.inf + ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf + EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + MdeModulePkg/Universal/Metronome/Metronome.inf + MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { + <LibraryClasses> + NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + } + + # Human Interface Support + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + # FAT filesystem + GPT/MBR partitioning + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + FatPkg/EnhancedFatDxe/Fat.inf + + # Bds + MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + MdeModulePkg/Application/UiApp/UiApp.inf { + <LibraryClasses> + NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf + NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf + NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf + } + + # Required by PCI + ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf + + # PCI Support + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf { + <PcdsFixedAtBuild> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8010004F + } + + # AHCI Support + MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf + MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf + + # SATA Controller + MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf + + # Usb Support + MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf + MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf + MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf + MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf + MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.fdf b/Platform/ARM/N1Sdp/N1SdpPlatform.fdf new file mode 100644 index 000000000000..c4e1f7b4b8fc --- /dev/null +++ b/Platform/ARM/N1Sdp/N1SdpPlatform.fdf @@ -0,0 +1,294 @@ +# +# Copyright (c) 2018 - 2020, ARM Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +################################################################################ +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +################################################################################ + +[FD.BL33_AP_UEFI] +BaseAddress = 0xE0000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash. +Size = 0x00200000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device +ErasePolarity = 1 + +# This one is tricky, it must be: BlockSize * NumBlocks = Size +BlockSize = 0x00001000 +NumBlocks = 0x200 + +################################################################################ +# +# Following are lists of FD Region layout which correspond to the locations of +# different images within the flash device. +# +# Regions must be defined in ascending order and may not overlap. +# +# A Layout Region start with a eight digit hex offset (leading "0x" required) +# followed by the pipe "|" character, followed by the size of the region, also +# in hex with the leading "0x" characters. Like: +# Offset|Size +# PcdOffsetCName|PcdSizeCName +# RegionType <FV, DATA, or FILE> +# +################################################################################ + +0x00000000|0x00200000 +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize +FV = FVMAIN_COMPACT + + +################################################################################ +# +# FV Section +# +# [FV] section is used to define what components or modules are placed within a +# flash device file. This section also defines order the components and modules +# are positioned within the image. The [FV] section consists of define +# statements, set statements and module statements. +# +################################################################################ + +[FV.FvMain] +BlockSize = 0x40 +NumBlocks = 0 # This FV gets compressed so make it just big enough +FvAlignment = 8 # FV alignment and FV attributes setting. +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + + INF MdeModulePkg/Core/Dxe/DxeMain.inf + + # PI DXE Drivers producing Architectural Protocols (EFI Services) + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + INF MdeModulePkg/Universal/Metronome/Metronome.inf + INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf + + # Human Interface Support + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + # Required by PCI + INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf + + # PCI Support + INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf + + # AHCI Support + INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf + INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf + + # SATA Controller + INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf + + # Usb Support + INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf + INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf + INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf + INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf + INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + INF MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf + + # Multiple Console IO support + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + INF ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf + + INF Platform/ARM/Drivers/BootMonFs/BootMonFs.inf + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + + # FAT filesystem + GPT/MBR partitioning + INF FatPkg/EnhancedFatDxe/Fat.inf + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + + # FV FileSystem + INF MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf + + # UEFI applications + INF ShellPkg/Application/Shell/Shell.inf + + # Bds + INF MdeModulePkg/Application/UiApp/UiApp.inf + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + +[FV.FVMAIN_COMPACT] +FvAlignment = 8 +BlockSize = 0x1000 +NumBlocks = 0x200 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + + INF ArmPkg/Drivers/CpuPei/CpuPei.inf + INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf + INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf + INF ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf + INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf + INF MdeModulePkg/Core/Pei/PeiMain.inf + INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf + INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf + + FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FVMAIN + } + } + + +################################################################################ +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are the default +# rules for the different module type. User can add the customized rules to define the +# content of the FFS file. +# +################################################################################ + + +############################################################################ +# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section # +############################################################################ +# +#[Rule.Common.DXE_DRIVER] +# FILE DRIVER = $(NAMED_GUID) { +# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex +# COMPRESS PI_STD { +# GUIDED { +# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi +# UI STRING="$(MODULE_NAME)" Optional +# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) +# } +# } +# } +# +############################################################################ + +# +# These SEC rules are used for ArmPlatformPkg/PrePeiCore module. +# ArmPlatformPkg/PrePeiCore is declared as a SEC module to make GenFv patch +# the UEFI Firmware to jump to ArmPlatformPkg/PrePeiCore entrypoint +# + +[Rule.Common.SEC] + FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED FIXED { + TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi + } + +[Rule.Common.PEI_CORE] + FILE PEI_CORE = $(NAMED_GUID) FIXED { + TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING ="$(MODULE_NAME)" Optional + } + +[Rule.Common.PEIM] + FILE PEIM = $(NAMED_GUID) FIXED { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.PEIM.TIANOCOMPRESSED] + FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + } + +[Rule.Common.DXE_CORE] + FILE DXE_CORE = $(NAMED_GUID) { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.UEFI_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.DXE_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.DXE_RUNTIME_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.UEFI_APPLICATION] + FILE APPLICATION = $(NAMED_GUID) { + UI STRING ="$(MODULE_NAME)" Optional + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + } + +[Rule.Common.UEFI_DRIVER.BINARY] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional |.depex + PE32 PE32 |.efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.UEFI_APPLICATION.BINARY] + FILE APPLICATION = $(NAMED_GUID) { + PE32 PE32 |.efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } -- 2.7.4 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [edk2-platforms][PATCH v3 0/4] Platform: Add initial support for N1SDP board @ 2020-07-03 11:18 Pranav Madhu 2020-07-03 11:18 ` [edk2-platforms][PATCH v3 1/4] Silicon/ARM/N1SoC: Add platform library implementation Pranav Madhu 0 siblings, 1 reply; 9+ messages in thread From: Pranav Madhu @ 2020-07-03 11:18 UTC (permalink / raw) To: devel; +Cc: Ard Biesheuvel, Leif Lindholm Changes since v2: - Addressed comments from Thomas. - Renamed Silicon/ARM/N1SDP to Silicon/ARM/NeoverseN1Soc. Changes since v1: - Addressed comments from Ard. - Split the code between Silicon and Platform directories. Arm's N1SDP is a Arm v8.2-A Neoverse N1 CPU based reference design platform primariliy intended for development on Arm64 based platform. This patch series adds initial platform support for this board. The first patch in this series adds the platform libary implementation. The second patch adds a custom implementation of the PciExpressLib due to a PCIe integration issue which results in all config space accesses to non-existing BDFs resulting in a Serror (bus abort). To avoid this, the N1SDP specific PciExpressLib implementation provides a workaround for this issue. The third patch in this series adds the platform library for the PciHostBridge. The fourth patch adds the initial platform support for the N1SDP platform. Deepak Pandey (4): Silicon/ARM/N1SoC: Add platform library implementation Silicon/ARM/N1SoC: Implement Neoverse N1 Soc specific PciExpressLib Silicon/ARM/N1SoC: Implement the PciHostBridgeLib library Platform/ARM/N1SDP: Add initial N1SDP platform support Silicon/ARM/NeoverseN1Soc/NeoverseN1SocPlatform.dec | 46 + Platform/ARM/N1Sdp/N1SdpPlatform.dsc | 245 ++++ Platform/ARM/N1Sdp/N1SdpPlatform.fdf | 294 ++++ Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/NeoverseN1SocPciExpressLib.inf | 39 + Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf | 49 + Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf | 54 + Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1SocPlatform.h | 68 + Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/NeoverseN1SocPciExpressLib.c | 1545 ++++++++++++++++++++ Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c | 187 +++ Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c | 67 + Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c | 152 ++ Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S | 84 ++ 12 files changed, 2830 insertions(+) create mode 100644 Silicon/ARM/NeoverseN1Soc/NeoverseN1SocPlatform.dec create mode 100644 Platform/ARM/N1Sdp/N1SdpPlatform.dsc create mode 100644 Platform/ARM/N1Sdp/N1SdpPlatform.fdf create mode 100644 Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/NeoverseN1SocPciExpressLib.inf create mode 100644 Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf create mode 100644 Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf create mode 100644 Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1SocPlatform.h create mode 100644 Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/NeoverseN1SocPciExpressLib.c create mode 100644 Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c create mode 100644 Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c create mode 100644 Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c create mode 100644 Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S -- 2.7.4 ^ permalink raw reply [flat|nested] 9+ messages in thread
* [edk2-platforms][PATCH v3 1/4] Silicon/ARM/N1SoC: Add platform library implementation 2020-07-03 11:18 [edk2-platforms][PATCH v3 0/4] Platform: Add initial support for N1SDP board Pranav Madhu @ 2020-07-03 11:18 ` Pranav Madhu 2020-07-13 17:18 ` Leif Lindholm 0 siblings, 1 reply; 9+ messages in thread From: Pranav Madhu @ 2020-07-03 11:18 UTC (permalink / raw) To: devel; +Cc: Ard Biesheuvel, Leif Lindholm From: Deepak Pandey <Deepak.Pandey@arm.com> Add the initial Arm's Neoverse N1 System-on-Chip platform library support. This includes the virtual memory map and helper functions for platform initialization. Cc: Ard Biesheuvel <ard.biesheuvel@arm.com> Cc: Leif Lindholm <leif@nuviainc.com> Signed-off-by: Pranav Madhu <pranav.madhu@arm.com> --- Silicon/ARM/NeoverseN1Soc/NeoverseN1SocPlatform.dec | 27 +++++ Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf | 43 +++++++ Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1SocPlatform.h | 68 +++++++++++ Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c | 67 +++++++++++ Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c | 126 ++++++++++++++++++++ Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S | 84 +++++++++++++ 6 files changed, 415 insertions(+) diff --git a/Silicon/ARM/NeoverseN1Soc/NeoverseN1SocPlatform.dec b/Silicon/ARM/NeoverseN1Soc/NeoverseN1SocPlatform.dec new file mode 100644 index 000000000000..dba49e6489c0 --- /dev/null +++ b/Silicon/ARM/NeoverseN1Soc/NeoverseN1SocPlatform.dec @@ -0,0 +1,27 @@ +# +# Copyright (c) 2018 - 2020, ARM Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +[Defines] + DEC_SPECIFICATION = 0x0001001A + PACKAGE_NAME = NeoverseN1Soc + PACKAGE_GUID = b6d2d197-76d0-401f-a3e0-826a26f350c9 + PACKAGE_VERSION = 0.1 + +################################################################################ +# +# Include Section - list of Include Paths that are provided by this package. +# Comments are used for Keywords and Module Types. +# +################################################################################ +[Includes.common] + Include # Root include for the package + +[Guids.common] + gArmNeoverseN1SocTokenSpaceGuid = { 0xab93eb78, 0x60d7, 0x4099, { 0xac, 0xeb, 0x6d, 0xb5, 0x02, 0x58, 0x7c, 0x24 } } + +[PcdsFixedAtBuild] + # Secondary DDR memory + gArmNeoverseN1SocTokenSpaceGuid.PcdDramBlock2Base|0|UINT64|0x00000001 diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf new file mode 100644 index 000000000000..b2ea10756071 --- /dev/null +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf @@ -0,0 +1,43 @@ +## @file +# +# Copyright (c) 2018-2020, ARM Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = ArmNeoverseN1SocLib + FILE_GUID = 3d0eafcf-abc1-43d8-9269-709bb24f9d21 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = ArmPlatformLib + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/ARM/NeoverseN1Soc/NeoverseN1SocPlatform.dec + +[Sources.common] + PlatformLibMem.c + PlatformLib.c + +[Sources.AARCH64] + AArch64/Helper.S | GCC + +[FixedPcd] + gArmTokenSpaceGuid.PcdSystemMemoryBase + gArmTokenSpaceGuid.PcdSystemMemorySize + gArmTokenSpaceGuid.PcdArmPrimaryCore + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask + + gArmNeoverseN1SocTokenSpaceGuid.PcdDramBlock2Base + +[Guids] + gEfiHobListGuid ## CONSUMES ## SystemTable + +[Ppis] + gArmMpCoreInfoPpiGuid diff --git a/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1SocPlatform.h b/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1SocPlatform.h new file mode 100644 index 000000000000..c47039c24293 --- /dev/null +++ b/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1SocPlatform.h @@ -0,0 +1,68 @@ +/** @file +* +* Copyright (c) 2018 - 2020, ARM Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#ifndef __NEOVERSEN1SOC_PLATFORM_H__ +#define __NEOVERSEN1SOC_PLATFORM_H__ + +#define NEOVERSEN1SOC_DRAM_BLOCK1_SIZE SIZE_2GB + +//****************************************************************************** +// Platform Memory Map +//****************************************************************************** + +// SubSystem Peripherals - UART0 +#define NEOVERSEN1SOC_UART0_BASE 0x2A400000 +#define NEOVERSEN1SOC_UART0_SZ SIZE_64KB + +// SubSystem Peripherals - UART1 +#define NEOVERSEN1SOC_UART1_BASE 0x2A410000 +#define NEOVERSEN1SOC_UART1_SZ SIZE_64KB + +// SubSystem Peripherals - Generic Watchdog +#define NEOVERSEN1SOC_GENERIC_WDOG_BASE 0x2A440000 +#define NEOVERSEN1SOC_GENERIC_WDOG_SZ SIZE_128KB + +// SubSystem Peripherals - GIC(600) +#define NEOVERSEN1SOC_GIC_BASE 0x30000000 +#define NEOVERSEN1SOC_GICR_BASE 0x300C0000 +#define NEOVERSEN1SOC_GIC_SZ SIZE_256KB +#define NEOVERSEN1SOC_GICR_SZ SIZE_1MB + +// SubSystem non-secure SRAM +#define NEOVERSEN1SOC_NON_SECURE_SRAM_BASE 0x06000000 +#define NEOVERSEN1SOC_NON_SECURE_SRAM_SZ SIZE_64KB + +// AXI Expansion peripherals +#define NEOVERSEN1SOC_EXP_PERIPH_BASE0 0x1C000000 +#define NEOVERSEN1SOC_EXP_PERIPH_BASE0_SZ 0x1300000 + +// Base address to a structure of type NEOVERSEN1SOC_PLAT_INFO which is +// pre-populated by a earlier boot stage +#define NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE (NEOVERSEN1SOC_NON_SECURE_SRAM_BASE + \ + 0x00008000) + +/* + * Platform information structure stored in non secure SRAM. Platform + * information are passed from the trusted firmware with the below structure + * format. The elements of NEOVERSEN1SOC_PLAT_INFO should be always in sync + * with the lower level firmware. + */ +#pragma pack(1) +typedef struct { + /*! 0 - Single Chip, 1 - Chip to Chip (C2C) */ + BOOLEAN MultichipMode; + /*! Slave count in C2C mode */ + UINT8 SlaveCount; + /*! Local DDR memory size in GigaBytes */ + UINT8 LocalDdrSize; + /*! Remote DDR memory size in GigaBytes */ + UINT8 RemoteDdrSize; +} NEOVERSEN1SOC_PLAT_INFO; +#pragma pack() + +#endif diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c new file mode 100644 index 000000000000..6cb699b29716 --- /dev/null +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c @@ -0,0 +1,67 @@ +/** @file +* +* Copyright (c) 2018-2020, ARM Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include <Library/ArmPlatformLib.h> +#include <Library/BaseLib.h> +#include <Ppi/ArmMpCoreInfo.h> + +STATIC ARM_CORE_INFO mCoreInfoTable[] = { + { 0x0, 0x0 }, // Cluster 0, Core 0 + { 0x0, 0x1 }, // Cluster 0, Core 1 + { 0x1, 0x0 }, // Cluster 1, Core 0 + { 0x1, 0x1 } // Cluster 1, Core 1 +}; + +EFI_BOOT_MODE +ArmPlatformGetBootMode ( + VOID + ) +{ + return BOOT_WITH_FULL_CONFIGURATION; +} + +RETURN_STATUS +ArmPlatformInitialize ( + IN UINTN MpId + ) +{ + return RETURN_SUCCESS; +} + +EFI_STATUS +PrePeiCoreGetMpCoreInfo ( + OUT UINTN *CoreCount, + OUT ARM_CORE_INFO **ArmCoreTable + ) +{ + *CoreCount = sizeof (mCoreInfoTable) / sizeof (ARM_CORE_INFO); + *ArmCoreTable = mCoreInfoTable; + return EFI_SUCCESS; +} + +STATIC ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { + PrePeiCoreGetMpCoreInfo +}; + +EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = { + { + EFI_PEI_PPI_DESCRIPTOR_PPI, + &gArmMpCoreInfoPpiGuid, + &mMpCoreInfoPpi + } +}; + +VOID +ArmPlatformGetPlatformPpiList ( + OUT UINTN *PpiListSize, + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList + ) +{ + *PpiListSize = sizeof (gPlatformPpiTable); + *PpiList = gPlatformPpiTable; +} diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c new file mode 100644 index 000000000000..0234748fa72e --- /dev/null +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c @@ -0,0 +1,126 @@ +/** @file +* +* Copyright (c) 2018 - 2020, ARM Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include <Library/ArmPlatformLib.h> +#include <Library/DebugLib.h> +#include <Library/HobLib.h> +#include <Library/MemoryAllocationLib.h> +#include <NeoverseN1SocPlatform.h> + +// The total number of descriptors, including the final "end-of-table" descriptor. +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 9 + +/** + Returns the Virtual Memory Map of the platform. + + This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU + on your platform. + + @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing + a Physical-to-Virtual Memory mapping. This array + must be ended by a zero-filled entry. +**/ +VOID +ArmPlatformGetVirtualMemoryMap ( + IN ARM_MEMORY_REGION_DESCRIPTOR **VirtualMemoryMap + ) +{ + UINTN Index = 0; + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes; + NEOVERSEN1SOC_PLAT_INFO *PlatInfo; + UINT64 DramBlock2Size; + + PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE; + DramBlock2Size = ((UINT64)(PlatInfo->LocalDdrSize - + NEOVERSEN1SOC_DRAM_BLOCK1_SIZE / SIZE_1GB) * + (UINT64)SIZE_1GB); + + ResourceAttributes = + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED; + + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + ResourceAttributes, + FixedPcdGet64 (PcdDramBlock2Base), + DramBlock2Size); + + ASSERT (VirtualMemoryMap != NULL); + Index = 0; + + VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR *)AllocatePages + (EFI_SIZE_TO_PAGES (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) * + MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS)); + if (VirtualMemoryTable == NULL) { + return; + } + + // SubSystem Peripherals - Generic Watchdog + VirtualMemoryTable[Index].PhysicalBase = NEOVERSEN1SOC_GENERIC_WDOG_BASE; + VirtualMemoryTable[Index].VirtualBase = NEOVERSEN1SOC_GENERIC_WDOG_BASE; + VirtualMemoryTable[Index].Length = NEOVERSEN1SOC_GENERIC_WDOG_SZ; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + // SubSystem Peripherals - GIC-600 + VirtualMemoryTable[++Index].PhysicalBase = NEOVERSEN1SOC_GIC_BASE; + VirtualMemoryTable[Index].VirtualBase = NEOVERSEN1SOC_GIC_BASE; + VirtualMemoryTable[Index].Length = NEOVERSEN1SOC_GIC_SZ; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + // SubSystem Peripherals - GICR-600 + VirtualMemoryTable[++Index].PhysicalBase = NEOVERSEN1SOC_GICR_BASE; + VirtualMemoryTable[Index].VirtualBase = NEOVERSEN1SOC_GICR_BASE; + VirtualMemoryTable[Index].Length = NEOVERSEN1SOC_GICR_SZ; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + // OnChip non-secure SRAM + VirtualMemoryTable[++Index].PhysicalBase = NEOVERSEN1SOC_NON_SECURE_SRAM_BASE; + VirtualMemoryTable[Index].VirtualBase = NEOVERSEN1SOC_NON_SECURE_SRAM_BASE; + VirtualMemoryTable[Index].Length = NEOVERSEN1SOC_NON_SECURE_SRAM_SZ; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED; + + // SubSystem Pheripherals - UART0 + VirtualMemoryTable[++Index].PhysicalBase = NEOVERSEN1SOC_UART0_BASE; + VirtualMemoryTable[Index].VirtualBase = NEOVERSEN1SOC_UART0_BASE; + VirtualMemoryTable[Index].Length = NEOVERSEN1SOC_UART0_SZ; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + // DDR Primary (2GB) + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdSystemMemoryBase); + VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdSystemMemoryBase); + VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemMemorySize); + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK; + + // DDR Secondary + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdDramBlock2Base); + VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdDramBlock2Base); + VirtualMemoryTable[Index].Length = DramBlock2Size; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK; + + // Expansion Peripherals + VirtualMemoryTable[++Index].PhysicalBase = NEOVERSEN1SOC_EXP_PERIPH_BASE0; + VirtualMemoryTable[Index].VirtualBase = NEOVERSEN1SOC_EXP_PERIPH_BASE0; + VirtualMemoryTable[Index].Length = NEOVERSEN1SOC_EXP_PERIPH_BASE0_SZ; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + // End of Table + VirtualMemoryTable[++Index].PhysicalBase = 0; + VirtualMemoryTable[Index].VirtualBase = 0; + VirtualMemoryTable[Index].Length = 0; + VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0; + + ASSERT((Index) < MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); + DEBUG ((DEBUG_INIT, "Virtual Memory Table setup complete.\n")); + + *VirtualMemoryMap = VirtualMemoryTable; +} diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S new file mode 100644 index 000000000000..8d2069dea837 --- /dev/null +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S @@ -0,0 +1,84 @@ +/** @file +* +* Copyright (c) 2019 - 2020, ARM Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include <AsmMacroIoLibV8.h> +#include <Library/ArmLib.h> + +.text +.align 3 + +GCC_ASM_EXPORT(ArmPlatformPeiBootAction) +GCC_ASM_EXPORT(ArmPlatformGetCorePosition) +GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId) +GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore) + +// +// First platform specific function to be called in the PEI phase +// +// This function is actually the first function called by the PrePi +// or PrePeiCore modules. It allows to retrieve arguments passed to +// the UEFI firmware through the CPU registers. +// +ASM_PFX(ArmPlatformPeiBootAction): + ret + +// +// Return the core position from the value of its MpId register +// +// This function returns core position from the position 0 in the processor. +// This function might be called from assembler before any stack is set. +// +// @return Return the core position +// +//UINTN +//ArmPlatformGetCorePosition ( +// IN UINTN MpId +// ); +// With this function: CorePos = (ClusterId * 2) + CoreId +ASM_PFX(ArmPlatformGetCorePosition): + and x1, x0, #ARM_CORE_MASK + and x0, x0, #ARM_CLUSTER_MASK + add x0, x1, x0, LSR #7 + ret + +// +// Return the MpId of the primary core +// +// This function returns the MpId of the primary core. +// This function might be called from assembler before any stack is set. +// +// @return Return the MpId of the primary core +// +//UINTN +//ArmPlatformGetPrimaryCoreMpId ( +// VOID +// ); +ASM_PFX(ArmPlatformGetPrimaryCoreMpId): + MOV32 (w0, FixedPcdGet32(PcdArmPrimaryCore)) + ret + +// +// Return a non-zero value if the callee is the primary core +// +// This function returns a non-zero value if the callee is the primary core. +// Primary core is the core responsible to initialize hardware and run UEFI. +// This function might be called from assembler before any stack is set. +// +// @return Return a non-zero value if the callee is the primary core. +// +//UINTN +//ArmPlatformIsPrimaryCore ( +// IN UINTN MpId +// ); +ASM_PFX(ArmPlatformIsPrimaryCore): + MOV32 (w1, FixedPcdGet32(PcdArmPrimaryCoreMask)) + and x0, x0, x1 + MOV32 (w1, FixedPcdGet32(PcdArmPrimaryCore)) + cmp w0, w1 + cset x0, eq + ret -- 2.7.4 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [edk2-platforms][PATCH v3 1/4] Silicon/ARM/N1SoC: Add platform library implementation 2020-07-03 11:18 ` [edk2-platforms][PATCH v3 1/4] Silicon/ARM/N1SoC: Add platform library implementation Pranav Madhu @ 2020-07-13 17:18 ` Leif Lindholm 0 siblings, 0 replies; 9+ messages in thread From: Leif Lindholm @ 2020-07-13 17:18 UTC (permalink / raw) To: Pranav Madhu; +Cc: devel, Ard Biesheuvel On Fri, Jul 03, 2020 at 16:48:53 +0530, Pranav Madhu wrote: > From: Deepak Pandey <Deepak.Pandey@arm.com> > > Add the initial Arm's Neoverse N1 System-on-Chip platform library > support. This includes the virtual memory map and helper functions for > platform initialization. > > Cc: Ard Biesheuvel <ard.biesheuvel@arm.com> > Cc: Leif Lindholm <leif@nuviainc.com> > Signed-off-by: Pranav Madhu <pranav.madhu@arm.com> > --- > Silicon/ARM/NeoverseN1Soc/NeoverseN1SocPlatform.dec | 27 +++++ > Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf | 43 +++++++ > Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1SocPlatform.h | 68 +++++++++++ > Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c | 67 +++++++++++ > Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c | 126 ++++++++++++++++++++ > Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S | 84 +++++++++++++ > 6 files changed, 415 insertions(+) > > diff --git a/Silicon/ARM/NeoverseN1Soc/NeoverseN1SocPlatform.dec b/Silicon/ARM/NeoverseN1Soc/NeoverseN1SocPlatform.dec > new file mode 100644 > index 000000000000..dba49e6489c0 > --- /dev/null > +++ b/Silicon/ARM/NeoverseN1Soc/NeoverseN1SocPlatform.dec > @@ -0,0 +1,27 @@ > +# > +# Copyright (c) 2018 - 2020, ARM Limited. All rights reserved. > +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > + > +[Defines] > + DEC_SPECIFICATION = 0x0001001A > + PACKAGE_NAME = NeoverseN1Soc > + PACKAGE_GUID = b6d2d197-76d0-401f-a3e0-826a26f350c9 > + PACKAGE_VERSION = 0.1 > + > +################################################################################ > +# > +# Include Section - list of Include Paths that are provided by this package. > +# Comments are used for Keywords and Module Types. > +# > +################################################################################ > +[Includes.common] > + Include # Root include for the package > + > +[Guids.common] > + gArmNeoverseN1SocTokenSpaceGuid = { 0xab93eb78, 0x60d7, 0x4099, { 0xac, 0xeb, 0x6d, 0xb5, 0x02, 0x58, 0x7c, 0x24 } } > + > +[PcdsFixedAtBuild] > + # Secondary DDR memory > + gArmNeoverseN1SocTokenSpaceGuid.PcdDramBlock2Base|0|UINT64|0x00000001 > diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf > new file mode 100644 > index 000000000000..b2ea10756071 > --- /dev/null > +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf > @@ -0,0 +1,43 @@ > +## @file > +# > +# Copyright (c) 2018-2020, ARM Limited. All rights reserved. > +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +## > + > +[Defines] > + INF_VERSION = 0x0001001A > + BASE_NAME = ArmNeoverseN1SocLib > + FILE_GUID = 3d0eafcf-abc1-43d8-9269-709bb24f9d21 > + MODULE_TYPE = BASE > + VERSION_STRING = 1.0 > + LIBRARY_CLASS = ArmPlatformLib > + > +[Packages] > + ArmPkg/ArmPkg.dec > + ArmPlatformPkg/ArmPlatformPkg.dec > + MdeModulePkg/MdeModulePkg.dec > + MdePkg/MdePkg.dec > + Silicon/ARM/NeoverseN1Soc/NeoverseN1SocPlatform.dec > + > +[Sources.common] > + PlatformLibMem.c > + PlatformLib.c > + > +[Sources.AARCH64] > + AArch64/Helper.S | GCC > + > +[FixedPcd] > + gArmTokenSpaceGuid.PcdSystemMemoryBase > + gArmTokenSpaceGuid.PcdSystemMemorySize > + gArmTokenSpaceGuid.PcdArmPrimaryCore > + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask > + > + gArmNeoverseN1SocTokenSpaceGuid.PcdDramBlock2Base > + > +[Guids] > + gEfiHobListGuid ## CONSUMES ## SystemTable > + > +[Ppis] > + gArmMpCoreInfoPpiGuid > diff --git a/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1SocPlatform.h b/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1SocPlatform.h > new file mode 100644 > index 000000000000..c47039c24293 > --- /dev/null > +++ b/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1SocPlatform.h > @@ -0,0 +1,68 @@ > +/** @file > +* > +* Copyright (c) 2018 - 2020, ARM Limited. All rights reserved. > +* > +* SPDX-License-Identifier: BSD-2-Clause-Patent > +* > +**/ > + > +#ifndef __NEOVERSEN1SOC_PLATFORM_H__ > +#define __NEOVERSEN1SOC_PLATFORM_H__ Please drop leading __ from include guards, these are reserved for toolchain use. (This applies globally.) > + > +#define NEOVERSEN1SOC_DRAM_BLOCK1_SIZE SIZE_2GB > + > +//****************************************************************************** > +// Platform Memory Map > +//****************************************************************************** > + > +// SubSystem Peripherals - UART0 > +#define NEOVERSEN1SOC_UART0_BASE 0x2A400000 > +#define NEOVERSEN1SOC_UART0_SZ SIZE_64KB > + > +// SubSystem Peripherals - UART1 > +#define NEOVERSEN1SOC_UART1_BASE 0x2A410000 > +#define NEOVERSEN1SOC_UART1_SZ SIZE_64KB > + > +// SubSystem Peripherals - Generic Watchdog > +#define NEOVERSEN1SOC_GENERIC_WDOG_BASE 0x2A440000 > +#define NEOVERSEN1SOC_GENERIC_WDOG_SZ SIZE_128KB > + > +// SubSystem Peripherals - GIC(600) > +#define NEOVERSEN1SOC_GIC_BASE 0x30000000 > +#define NEOVERSEN1SOC_GICR_BASE 0x300C0000 > +#define NEOVERSEN1SOC_GIC_SZ SIZE_256KB > +#define NEOVERSEN1SOC_GICR_SZ SIZE_1MB > + > +// SubSystem non-secure SRAM > +#define NEOVERSEN1SOC_NON_SECURE_SRAM_BASE 0x06000000 > +#define NEOVERSEN1SOC_NON_SECURE_SRAM_SZ SIZE_64KB > + > +// AXI Expansion peripherals > +#define NEOVERSEN1SOC_EXP_PERIPH_BASE0 0x1C000000 > +#define NEOVERSEN1SOC_EXP_PERIPH_BASE0_SZ 0x1300000 > + > +// Base address to a structure of type NEOVERSEN1SOC_PLAT_INFO which is > +// pre-populated by a earlier boot stage > +#define NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE (NEOVERSEN1SOC_NON_SECURE_SRAM_BASE + \ > + 0x00008000) > + > +/* > + * Platform information structure stored in non secure SRAM. Platform This refers to the architectural term, so should be "Non-secure". > + * information are passed from the trusted firmware with the below structure > + * format. The elements of NEOVERSEN1SOC_PLAT_INFO should be always in sync > + * with the lower level firmware. > + */ > +#pragma pack(1) > +typedef struct { > + /*! 0 - Single Chip, 1 - Chip to Chip (C2C) */ > + BOOLEAN MultichipMode; Is this defined as a boolean in whatever specifies the other end of this protocol? If not, please keep it as a UINT8, which is what it will always be equal to for AARCH64 in EDK2. This also helps make it clearer that the #pragma pack statement here is completely spurious. Please delete the pragma. > + /*! Slave count in C2C mode */ > + UINT8 SlaveCount; > + /*! Local DDR memory size in GigaBytes */ > + UINT8 LocalDdrSize; > + /*! Remote DDR memory size in GigaBytes */ > + UINT8 RemoteDdrSize; > +} NEOVERSEN1SOC_PLAT_INFO; > +#pragma pack() > + > +#endif > diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c > new file mode 100644 > index 000000000000..6cb699b29716 > --- /dev/null > +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c > @@ -0,0 +1,67 @@ > +/** @file > +* > +* Copyright (c) 2018-2020, ARM Limited. All rights reserved. > +* > +* SPDX-License-Identifier: BSD-2-Clause-Patent > +* > +**/ > + > +#include <Library/ArmPlatformLib.h> > +#include <Library/BaseLib.h> > +#include <Ppi/ArmMpCoreInfo.h> > + > +STATIC ARM_CORE_INFO mCoreInfoTable[] = { > + { 0x0, 0x0 }, // Cluster 0, Core 0 > + { 0x0, 0x1 }, // Cluster 0, Core 1 > + { 0x1, 0x0 }, // Cluster 1, Core 0 > + { 0x1, 0x1 } // Cluster 1, Core 1 > +}; > + > +EFI_BOOT_MODE > +ArmPlatformGetBootMode ( > + VOID > + ) > +{ > + return BOOT_WITH_FULL_CONFIGURATION; > +} > + > +RETURN_STATUS > +ArmPlatformInitialize ( > + IN UINTN MpId > + ) > +{ > + return RETURN_SUCCESS; > +} > + > +EFI_STATUS > +PrePeiCoreGetMpCoreInfo ( > + OUT UINTN *CoreCount, > + OUT ARM_CORE_INFO **ArmCoreTable > + ) > +{ > + *CoreCount = sizeof (mCoreInfoTable) / sizeof (ARM_CORE_INFO); > + *ArmCoreTable = mCoreInfoTable; > + return EFI_SUCCESS; > +} > + > +STATIC ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { > + PrePeiCoreGetMpCoreInfo > +}; > + > +EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = { > + { > + EFI_PEI_PPI_DESCRIPTOR_PPI, > + &gArmMpCoreInfoPpiGuid, > + &mMpCoreInfoPpi > + } > +}; > + > +VOID > +ArmPlatformGetPlatformPpiList ( > + OUT UINTN *PpiListSize, > + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList > + ) > +{ > + *PpiListSize = sizeof (gPlatformPpiTable); > + *PpiList = gPlatformPpiTable; > +} > diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c > new file mode 100644 > index 000000000000..0234748fa72e > --- /dev/null > +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c > @@ -0,0 +1,126 @@ > +/** @file > +* > +* Copyright (c) 2018 - 2020, ARM Limited. All rights reserved. > +* > +* SPDX-License-Identifier: BSD-2-Clause-Patent > +* > +**/ > + > +#include <Library/ArmPlatformLib.h> > +#include <Library/DebugLib.h> > +#include <Library/HobLib.h> > +#include <Library/MemoryAllocationLib.h> > +#include <NeoverseN1SocPlatform.h> > + > +// The total number of descriptors, including the final "end-of-table" descriptor. > +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 9 > + > +/** > + Returns the Virtual Memory Map of the platform. > + > + This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU > + on your platform. > + > + @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing > + a Physical-to-Virtual Memory mapping. This array > + must be ended by a zero-filled entry. > +**/ > +VOID > +ArmPlatformGetVirtualMemoryMap ( > + IN ARM_MEMORY_REGION_DESCRIPTOR **VirtualMemoryMap > + ) > +{ > + UINTN Index = 0; > + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; > + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes; > + NEOVERSEN1SOC_PLAT_INFO *PlatInfo; > + UINT64 DramBlock2Size; > + > + PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE; > + DramBlock2Size = ((UINT64)(PlatInfo->LocalDdrSize - > + NEOVERSEN1SOC_DRAM_BLOCK1_SIZE / SIZE_1GB) * > + (UINT64)SIZE_1GB); > + > + ResourceAttributes = > + EFI_RESOURCE_ATTRIBUTE_PRESENT | > + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | > + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | > + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | > + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | > + EFI_RESOURCE_ATTRIBUTE_TESTED; > + > + BuildResourceDescriptorHob ( > + EFI_RESOURCE_SYSTEM_MEMORY, > + ResourceAttributes, > + FixedPcdGet64 (PcdDramBlock2Base), > + DramBlock2Size); > + > + ASSERT (VirtualMemoryMap != NULL); > + Index = 0; > + > + VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR *)AllocatePages Drop the cast, it conveys no useful information and clutters things up. > + (EFI_SIZE_TO_PAGES (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) * > + MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS)); For clarity, this line should align with the 's' in 'sizeof'. It cleans things up even more if using AllocatePool instead of having to convert the required space. If you prefer using AllocatePages, please use a temporary variable for the size. / Leif > + if (VirtualMemoryTable == NULL) { > + return; > + } > + > + // SubSystem Peripherals - Generic Watchdog > + VirtualMemoryTable[Index].PhysicalBase = NEOVERSEN1SOC_GENERIC_WDOG_BASE; > + VirtualMemoryTable[Index].VirtualBase = NEOVERSEN1SOC_GENERIC_WDOG_BASE; > + VirtualMemoryTable[Index].Length = NEOVERSEN1SOC_GENERIC_WDOG_SZ; > + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; > + > + // SubSystem Peripherals - GIC-600 > + VirtualMemoryTable[++Index].PhysicalBase = NEOVERSEN1SOC_GIC_BASE; > + VirtualMemoryTable[Index].VirtualBase = NEOVERSEN1SOC_GIC_BASE; > + VirtualMemoryTable[Index].Length = NEOVERSEN1SOC_GIC_SZ; > + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; > + > + // SubSystem Peripherals - GICR-600 > + VirtualMemoryTable[++Index].PhysicalBase = NEOVERSEN1SOC_GICR_BASE; > + VirtualMemoryTable[Index].VirtualBase = NEOVERSEN1SOC_GICR_BASE; > + VirtualMemoryTable[Index].Length = NEOVERSEN1SOC_GICR_SZ; > + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; > + > + // OnChip non-secure SRAM > + VirtualMemoryTable[++Index].PhysicalBase = NEOVERSEN1SOC_NON_SECURE_SRAM_BASE; > + VirtualMemoryTable[Index].VirtualBase = NEOVERSEN1SOC_NON_SECURE_SRAM_BASE; > + VirtualMemoryTable[Index].Length = NEOVERSEN1SOC_NON_SECURE_SRAM_SZ; > + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED; > + > + // SubSystem Pheripherals - UART0 > + VirtualMemoryTable[++Index].PhysicalBase = NEOVERSEN1SOC_UART0_BASE; > + VirtualMemoryTable[Index].VirtualBase = NEOVERSEN1SOC_UART0_BASE; > + VirtualMemoryTable[Index].Length = NEOVERSEN1SOC_UART0_SZ; > + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; > + > + // DDR Primary (2GB) > + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdSystemMemoryBase); > + VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdSystemMemoryBase); > + VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemMemorySize); > + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK; > + > + // DDR Secondary > + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdDramBlock2Base); > + VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdDramBlock2Base); > + VirtualMemoryTable[Index].Length = DramBlock2Size; > + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK; > + > + // Expansion Peripherals > + VirtualMemoryTable[++Index].PhysicalBase = NEOVERSEN1SOC_EXP_PERIPH_BASE0; > + VirtualMemoryTable[Index].VirtualBase = NEOVERSEN1SOC_EXP_PERIPH_BASE0; > + VirtualMemoryTable[Index].Length = NEOVERSEN1SOC_EXP_PERIPH_BASE0_SZ; > + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; > + > + // End of Table > + VirtualMemoryTable[++Index].PhysicalBase = 0; > + VirtualMemoryTable[Index].VirtualBase = 0; > + VirtualMemoryTable[Index].Length = 0; > + VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0; > + > + ASSERT((Index) < MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); > + DEBUG ((DEBUG_INIT, "Virtual Memory Table setup complete.\n")); > + > + *VirtualMemoryMap = VirtualMemoryTable; > +} > diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S > new file mode 100644 > index 000000000000..8d2069dea837 > --- /dev/null > +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S > @@ -0,0 +1,84 @@ > +/** @file > +* > +* Copyright (c) 2019 - 2020, ARM Limited. All rights reserved. > +* > +* SPDX-License-Identifier: BSD-2-Clause-Patent > +* > +**/ > + > +#include <AsmMacroIoLibV8.h> > +#include <Library/ArmLib.h> > + > +.text > +.align 3 > + > +GCC_ASM_EXPORT(ArmPlatformPeiBootAction) > +GCC_ASM_EXPORT(ArmPlatformGetCorePosition) > +GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId) > +GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore) > + > +// > +// First platform specific function to be called in the PEI phase > +// > +// This function is actually the first function called by the PrePi > +// or PrePeiCore modules. It allows to retrieve arguments passed to > +// the UEFI firmware through the CPU registers. > +// > +ASM_PFX(ArmPlatformPeiBootAction): > + ret > + > +// > +// Return the core position from the value of its MpId register > +// > +// This function returns core position from the position 0 in the processor. > +// This function might be called from assembler before any stack is set. > +// > +// @return Return the core position > +// > +//UINTN > +//ArmPlatformGetCorePosition ( > +// IN UINTN MpId > +// ); > +// With this function: CorePos = (ClusterId * 2) + CoreId > +ASM_PFX(ArmPlatformGetCorePosition): > + and x1, x0, #ARM_CORE_MASK > + and x0, x0, #ARM_CLUSTER_MASK > + add x0, x1, x0, LSR #7 > + ret > + > +// > +// Return the MpId of the primary core > +// > +// This function returns the MpId of the primary core. > +// This function might be called from assembler before any stack is set. > +// > +// @return Return the MpId of the primary core > +// > +//UINTN > +//ArmPlatformGetPrimaryCoreMpId ( > +// VOID > +// ); > +ASM_PFX(ArmPlatformGetPrimaryCoreMpId): > + MOV32 (w0, FixedPcdGet32(PcdArmPrimaryCore)) > + ret > + > +// > +// Return a non-zero value if the callee is the primary core > +// > +// This function returns a non-zero value if the callee is the primary core. > +// Primary core is the core responsible to initialize hardware and run UEFI. > +// This function might be called from assembler before any stack is set. > +// > +// @return Return a non-zero value if the callee is the primary core. > +// > +//UINTN > +//ArmPlatformIsPrimaryCore ( > +// IN UINTN MpId > +// ); > +ASM_PFX(ArmPlatformIsPrimaryCore): > + MOV32 (w1, FixedPcdGet32(PcdArmPrimaryCoreMask)) > + and x0, x0, x1 > + MOV32 (w1, FixedPcdGet32(PcdArmPrimaryCore)) > + cmp w0, w1 > + cset x0, eq > + ret > -- > 2.7.4 > ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2020-07-13 17:18 UTC | newest] Thread overview: 9+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2020-07-03 7:02 [edk2-platforms][PATCH v3 0/4] Platform: Add initial support for N1SDP board Pranav Madhu 2020-07-03 7:02 ` [edk2-platforms][PATCH v3 1/4] Silicon/ARM/N1SoC: Add platform library implementation Pranav Madhu 2020-07-03 10:35 ` Ard Biesheuvel 2020-07-03 11:23 ` Pranav Madhu 2020-07-03 7:02 ` [edk2-platforms][PATCH v3 2/4] Silicon/ARM/N1SoC: Implement Neoverse N1 Soc specific PciExpressLib Pranav Madhu 2020-07-03 7:02 ` [edk2-platforms][PATCH v3 3/4] Silicon/ARM/N1SoC: Implement the PciHostBridgeLib library Pranav Madhu 2020-07-03 7:02 ` [edk2-platforms][PATCH v3 4/4] Platform/ARM/N1SDP: Add initial N1SDP platform support Pranav Madhu -- strict thread matches above, loose matches on Subject: below -- 2020-07-03 11:18 [edk2-platforms][PATCH v3 0/4] Platform: Add initial support for N1SDP board Pranav Madhu 2020-07-03 11:18 ` [edk2-platforms][PATCH v3 1/4] Silicon/ARM/N1SoC: Add platform library implementation Pranav Madhu 2020-07-13 17:18 ` Leif Lindholm
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