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From: "Sunil V L" <sunilvl@ventanamicro.com>
To: Andrei Warkentin <andrei.warkentin@intel.com>
Cc: devel@edk2.groups.io, Daniel Schaefer <git@danielschaefer.me>
Subject: Re: [PATCH 7/7] [PATCH v2] UefiCpuPkg: BaseRiscV64CpuExceptionHandlerLib: clean up exception handling
Date: Fri, 24 Feb 2023 16:14:35 +0530	[thread overview]
Message-ID: <Y/iVE0rG0TE05YeQ@sunil-laptop> (raw)
In-Reply-To: <20230223235454.23556-8-andrei.warkentin@intel.com>

On Thu, Feb 23, 2023 at 05:54:54PM -0600, Andrei Warkentin wrote:
> RegisterCpuInterruptHandler did not allow setting
> exception handlers for anything beyond the timer IRQ.
> Beyond that, it didn't meet the spec around handling
> of inputs.
> 
> RiscVSupervisorModeTrapHandler now will invoke
> set handlers for both exceptions and interrupts.
> Two arrays of handlers are maintained - one for exceptions
> and one for interrupts.
> 
> For unhandled traps, RiscVSupervisorModeTrapHandler dumps
> state using the now implemented DumpCpuContext.
> 
> For EFI_SYSTEM_CONTEXT_RISCV64, extend this with the trapped
> PC address (SEPC), just like on AArch64 (ELR). This is
> necessary for X86EmulatorPkg to work as it allows a trap
> handler to return execution to a different place. Add
> SSTATUS/STVAL as well, at least for debugging purposes. There
> is no value in hiding this.
> 
> Fix nested exception handling. Handler code should not
> be saving SIE (the value is saved in SSTATUS.SPIE) or
> directly restored (that's done by SRET). Save and
> restore the entire SSTATUS and STVAL, too.
> 
> Cc: Sunil V L <sunilvl@ventanamicro.com>
> Cc: Daniel Schaefer <git@danielschaefer.me>
> Signed-off-by: Andrei Warkentin <andrei.warkentin@intel.com>
> ---
>  MdePkg/Include/Protocol/DebugSupport.h        |  32 ++-
>  .../CpuExceptionHandlerLib.h                  |  11 +-
>  UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c         |   6 +-
>  .../CpuExceptionHandlerLib.c                  | 232 ++++++++++++++++--
>  .../SupervisorTrapHandler.S                   |  17 +-
>  5 files changed, 254 insertions(+), 44 deletions(-)
> 
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>

  reply	other threads:[~2023-02-24 10:44 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-02-23 23:54 [PATCH 0/7] Assorted fixes to core RISC-V and RiscVVirt Andrei Warkentin
2023-02-23 23:54 ` [PATCH 1/7] OvmfPkg: RiscVVirt: add SATA support Andrei Warkentin
2023-02-24 10:00   ` [edk2-devel] " Sunil V L
2023-02-23 23:54 ` [PATCH 2/7] MdePkg: BasePeCoffLib: Allow AArch64 and x64 images in ImageFormatSupported Andrei Warkentin
2023-02-24 10:02   ` Sunil V L
2023-02-23 23:54 ` [PATCH 3/7] MdePkg: BaseLib: don't log in RISCV InternalSwitchStack Andrei Warkentin
2023-02-23 23:54 ` [PATCH 4/7] MdePkg: BaseCpuLib: Fix RISCV CpuSleep symbol name Andrei Warkentin
2023-02-23 23:54 ` [PATCH 5/7] MdeModulePkg: Dxe: add RISCV64 to mMachineTypeInfo Andrei Warkentin
2023-02-23 23:54 ` [PATCH 6/7] [PATCH v2] UefiCpuPkg: CpuTimerDxeRiscV64: fix tick duration accounting Andrei Warkentin
2023-02-24 10:45   ` Sunil V L
2023-02-23 23:54 ` [PATCH 7/7] [PATCH v2] UefiCpuPkg: BaseRiscV64CpuExceptionHandlerLib: clean up exception handling Andrei Warkentin
2023-02-24 10:44   ` Sunil V L [this message]
2023-03-02  4:59   ` [edk2-devel] " Tuan Phan
     [not found]   ` <17488173C4DD581F.9697@groups.io>
2023-03-02  5:17     ` Tuan Phan
2023-03-02  5:26       ` Andrei Warkentin

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