Re: [edk2-staging/RiscV64QemuVirt PATCH V7 02/20] MdePkg/BaseLib: RISC-V: Add few more helper functions

["Sunil V L" <sunilvl@ventanamicro.com>]

Hi Mike,

On Thu, Feb 09, 2023 at 01:43:57AM +0000, Kinney, Michael D wrote:
> Hi Sunil,
> 
> Just a formatting comment below.
> 
> Mike
> 
> > -----Original Message-----
> > From: Sunil V L <sunilvl@ventanamicro.com>
> > Sent: Saturday, January 28, 2023 11:18 AM
> > To: devel@edk2.groups.io
> > Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Gao, Liming <gaoliming@byosoft.com.cn>; Liu, Zhiguang <zhiguang.liu@intel.com>;
> > Daniel Schaefer <git@danielschaefer.me>; Abner Chang <abner.chang@amd.com>
> > Subject: [edk2-staging/RiscV64QemuVirt PATCH V7 02/20] MdePkg/BaseLib: RISC-V: Add few more helper functions
> > 
> > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
> > 
> > Few of the basic helper functions required for any
> > RISC-V CPU were added in edk2-platforms. To support
> > qemu virt, they need to be added in BaseLib.
> > 
> > Cc: Michael D Kinney <michael.d.kinney@intel.com>
> > Cc: Liming Gao <gaoliming@byosoft.com.cn>
> > Cc: Zhiguang Liu <zhiguang.liu@intel.com>
> > Cc: Daniel Schaefer <git@danielschaefer.me>
> > Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> > Acked-by: Abner Chang <abner.chang@amd.com>
> > ---
> >  MdePkg/Library/BaseLib/BaseLib.inf              |  3 ++
> >  MdePkg/Include/Library/BaseLib.h                | 50 ++++++++++++++++++
> >  MdePkg/Library/BaseLib/RiscV64/CpuScratch.S     | 31 ++++++++++++
> >  MdePkg/Library/BaseLib/RiscV64/ReadTimer.S      | 23 +++++++++
> >  MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S | 53 ++++++++++++++++++--
> >  MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S       | 23 +++++++++
> >  6 files changed, 179 insertions(+), 4 deletions(-)
> > 
> > diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf
> > index 9ed46a584a14..3a48492b1a01 100644
> > --- a/MdePkg/Library/BaseLib/BaseLib.inf
> > +++ b/MdePkg/Library/BaseLib/BaseLib.inf
> > @@ -401,6 +401,9 @@ [Sources.RISCV64]
> >    RiscV64/RiscVCpuPause.S           | GCC
> >    RiscV64/RiscVInterrupt.S          | GCC
> >    RiscV64/FlushCache.S              | GCC
> > +  RiscV64/CpuScratch.S              | GCC
> > +  RiscV64/ReadTimer.S               | GCC
> > +  RiscV64/RiscVMmu.S                | GCC
> > 
> >  [Sources.LOONGARCH64]
> >    Math64.c
> > diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
> > index f3f59f21c2ea..b4f4e45a1486 100644
> > --- a/MdePkg/Include/Library/BaseLib.h
> > +++ b/MdePkg/Include/Library/BaseLib.h
> > @@ -151,6 +151,56 @@ typedef struct {
> > 
> >  #define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT  8
> > 
> > +VOID
> > +  RiscVSetSupervisorScratch (
> > +                             UINT64
> > +                             );
> > +
> > +UINT64
> > +RiscVGetSupervisorScratch (
> > +  VOID
> > +  );
> > +
> > +VOID
> > +  RiscVSetSupervisorStvec (
> > +                           UINT64
> > +                           );
> > +
> > +UINT64
> > +RiscVGetSupervisorStvec (
> > +  VOID
> > +  );
> > +
> > +UINT64
> > +RiscVGetSupervisorTrapCause (
> > +  VOID
> > +  );
> > +
> > +VOID
> > +  RiscVSetSupervisorAddressTranslationRegister (
> > +                                                UINT64
> > +                                                );
> 
> Formatting does not look right.
> 
> Have you run EDK II uncrustify on this patch series.
> 
Interesting. I ran both offline CI and CI through PR for these changes.
Anyway, thanks for catching this. Let me fix it in the next revision.

Thanks!
Sunil