From mboxrd@z Thu Jan 1 00:00:00 1970
Received: from mail-pj1-f48.google.com (mail-pj1-f48.google.com [209.85.216.48])
by mx.groups.io with SMTP id smtpd.web11.8693.1675927304510315604
for <devel@edk2.groups.io>;
Wed, 08 Feb 2023 23:21:44 -0800
Authentication-Results: mx.groups.io;
dkim=pass header.i=@ventanamicro.com header.s=google header.b=WvYgCbJi;
spf=pass (domain: ventanamicro.com, ip: 209.85.216.48, mailfrom: sunilvl@ventanamicro.com)
Received: by mail-pj1-f48.google.com with SMTP id v18-20020a17090ae99200b00230f079dcd9so5213869pjy.1
for <devel@edk2.groups.io>; Wed, 08 Feb 2023 23:21:44 -0800 (PST)
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
d=ventanamicro.com; s=google;
h=in-reply-to:content-disposition:mime-version:references:message-id
:subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to;
bh=9nrmQU9GkpSz8BA1qf1X2TLLg2Zt9z0+jPCbWLfTlDQ=;
b=WvYgCbJiSBhll3u4dAM5ORcS3wWM3pu2Rt6u/yJrIH5TS5rP7JdjbhLkUg4j1XOgO2
8DtLuehT+gYOir0C/Wq98jHAuHn+JZ1mxjh6uw9g9AUd03oTWOKnqbIawayj9xBQvw0V
vyXCRN/rQ6pW8zUufQh0HVq9E5YHkkOMmnqCagt2c/EuEmz4Sfhew3zRMKOt720+B2Yi
imIZjB1798OiErFEMDozz7bk8my5n3aaS/muS9GsE+XyjE3Gx6xskgBWb+FUnyd0KY8h
Mw0ANpA1StiafBQIA3raDv/yf5F0jOl0haYt4qVTTs0yfRoEIlCOl00h502ocfiNwiBU
iRsg==
X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
d=1e100.net; s=20210112;
h=in-reply-to:content-disposition:mime-version:references:message-id
:subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date
:message-id:reply-to;
bh=9nrmQU9GkpSz8BA1qf1X2TLLg2Zt9z0+jPCbWLfTlDQ=;
b=uXjJdhLLRBBnQr2ltZX3gBDD4KV0/DczZngQelk2a4Ux7EUs2oxTUShlSizKMwC9zm
hyGx8xZL3B5gwtR0Z+1wFBvUhsVOBB+0gsAMjgz7P+srXP+OhwitJW2uKfXj3WtyLL/S
SXmcO6ZaYS902H70R2iuTmOVHQFURe8jaYDzvXE7yt7ZB8UgM8TMW0YX3lm66r2iX2Dh
y0pFQqDn3Q3ni0y7Rw8+lbZ0vGmA8+VzkXh4CacFdu6RoTrxL8kOWSknDYyXokcMQUbu
JlVCoOXgL+gcCJdfd40r4qZ7PNSq/ZIULvbBYs7iVEuigvYUG+sSUHqidyLLrDCK3mYY
SaWQ==
X-Gm-Message-State: AO0yUKUMGxzHy8goF5tU1RcVSwPODJfpIGvqxPYIESjDNmX3FoQg+Aj7
0oB18gurmblBTGM/Q5IvIh1R3A==
X-Google-Smtp-Source: AK7set8DFAZZTFbvbB5t7nNe17CrrGrJKgp1EbNocUIUcFLBVX2L7opc8BuA/59Ux4kL+gkfB7bwGg==
X-Received: by 2002:a17:90b:4b4e:b0:22c:92:15db with SMTP id mi14-20020a17090b4b4e00b0022c009215dbmr4830590pjb.25.1675927303960;
Wed, 08 Feb 2023 23:21:43 -0800 (PST)
Return-Path: <sunilvl@ventanamicro.com>
Received: from sunil-laptop ([49.206.14.226])
by smtp.gmail.com with ESMTPSA id bj2-20020a17090b088200b0020b21019086sm5698921pjb.3.2023.02.08.23.21.41
(version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);
Wed, 08 Feb 2023 23:21:43 -0800 (PST)
Date: Thu, 9 Feb 2023 12:51:38 +0530
From: "Sunil V L" <sunilvl@ventanamicro.com>
To: "Kinney, Michael D" <michael.d.kinney@intel.com>
Cc: "devel@edk2.groups.io" <devel@edk2.groups.io>,
"Gao, Liming" <gaoliming@byosoft.com.cn>,
"Liu, Zhiguang" <zhiguang.liu@intel.com>,
Daniel Schaefer <git@danielschaefer.me>,
Abner Chang <abner.chang@amd.com>
Subject: Re: [edk2-staging/RiscV64QemuVirt PATCH V7 02/20] MdePkg/BaseLib: RISC-V: Add few more helper functions
Message-ID: <Y+SfAkK8qqGykGTq@sunil-laptop>
References: <20230128191807.2080547-1-sunilvl@ventanamicro.com>
<20230128191807.2080547-3-sunilvl@ventanamicro.com>
<CO1PR11MB4929D5C04693CA4D78657FBBD2D99@CO1PR11MB4929.namprd11.prod.outlook.com>
MIME-Version: 1.0
In-Reply-To: <CO1PR11MB4929D5C04693CA4D78657FBBD2D99@CO1PR11MB4929.namprd11.prod.outlook.com>
Content-Type: text/plain; charset=us-ascii
Content-Disposition: inline
Hi Mike,
On Thu, Feb 09, 2023 at 01:43:57AM +0000, Kinney, Michael D wrote:
> Hi Sunil,
>
> Just a formatting comment below.
>
> Mike
>
> > -----Original Message-----
> > From: Sunil V L <sunilvl@ventanamicro.com>
> > Sent: Saturday, January 28, 2023 11:18 AM
> > To: devel@edk2.groups.io
> > Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Gao, Liming <gaoliming@byosoft.com.cn>; Liu, Zhiguang <zhiguang.liu@intel.com>;
> > Daniel Schaefer <git@danielschaefer.me>; Abner Chang <abner.chang@amd.com>
> > Subject: [edk2-staging/RiscV64QemuVirt PATCH V7 02/20] MdePkg/BaseLib: RISC-V: Add few more helper functions
> >
> > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
> >
> > Few of the basic helper functions required for any
> > RISC-V CPU were added in edk2-platforms. To support
> > qemu virt, they need to be added in BaseLib.
> >
> > Cc: Michael D Kinney <michael.d.kinney@intel.com>
> > Cc: Liming Gao <gaoliming@byosoft.com.cn>
> > Cc: Zhiguang Liu <zhiguang.liu@intel.com>
> > Cc: Daniel Schaefer <git@danielschaefer.me>
> > Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> > Acked-by: Abner Chang <abner.chang@amd.com>
> > ---
> > MdePkg/Library/BaseLib/BaseLib.inf | 3 ++
> > MdePkg/Include/Library/BaseLib.h | 50 ++++++++++++++++++
> > MdePkg/Library/BaseLib/RiscV64/CpuScratch.S | 31 ++++++++++++
> > MdePkg/Library/BaseLib/RiscV64/ReadTimer.S | 23 +++++++++
> > MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S | 53 ++++++++++++++++++--
> > MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S | 23 +++++++++
> > 6 files changed, 179 insertions(+), 4 deletions(-)
> >
> > diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf
> > index 9ed46a584a14..3a48492b1a01 100644
> > --- a/MdePkg/Library/BaseLib/BaseLib.inf
> > +++ b/MdePkg/Library/BaseLib/BaseLib.inf
> > @@ -401,6 +401,9 @@ [Sources.RISCV64]
> > RiscV64/RiscVCpuPause.S | GCC
> > RiscV64/RiscVInterrupt.S | GCC
> > RiscV64/FlushCache.S | GCC
> > + RiscV64/CpuScratch.S | GCC
> > + RiscV64/ReadTimer.S | GCC
> > + RiscV64/RiscVMmu.S | GCC
> >
> > [Sources.LOONGARCH64]
> > Math64.c
> > diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
> > index f3f59f21c2ea..b4f4e45a1486 100644
> > --- a/MdePkg/Include/Library/BaseLib.h
> > +++ b/MdePkg/Include/Library/BaseLib.h
> > @@ -151,6 +151,56 @@ typedef struct {
> >
> > #define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8
> >
> > +VOID
> > + RiscVSetSupervisorScratch (
> > + UINT64
> > + );
> > +
> > +UINT64
> > +RiscVGetSupervisorScratch (
> > + VOID
> > + );
> > +
> > +VOID
> > + RiscVSetSupervisorStvec (
> > + UINT64
> > + );
> > +
> > +UINT64
> > +RiscVGetSupervisorStvec (
> > + VOID
> > + );
> > +
> > +UINT64
> > +RiscVGetSupervisorTrapCause (
> > + VOID
> > + );
> > +
> > +VOID
> > + RiscVSetSupervisorAddressTranslationRegister (
> > + UINT64
> > + );
>
> Formatting does not look right.
>
> Have you run EDK II uncrustify on this patch series.
>
Interesting. I ran both offline CI and CI through PR for these changes.
Anyway, thanks for catching this. Let me fix it in the next revision.
Thanks!
Sunil