From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by mx.groups.io with SMTP id smtpd.web11.12747.1676460531449997557 for ; Wed, 15 Feb 2023 03:28:51 -0800 Authentication-Results: mx.groups.io; dkim=fail reason="body hash did not verify" header.i=@quicinc.com header.s=qcppdkim1 header.b=KFH/hLpu; spf=permerror, err=parse error for token &{10 18 %{ir}.%{v}.%{d}.spf.has.pphosted.com}: invalid domain name (domain: quicinc.com, ip: 205.220.180.131, mailfrom: quic_llindhol@quicinc.com) Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 31F8Kxi5024398; Wed, 15 Feb 2023 11:28:47 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=date : from : to : cc : subject : message-id : references : mime-version : content-type : content-transfer-encoding : in-reply-to; s=qcppdkim1; bh=5B0oTX0On9ONevoFb75WHY+CHdryDREO8/s+0+GT7PE=; b=KFH/hLpuHphyYxgqlYoQ2pKHsgyshNGTUVO9V5pwY9OF3K78ot0vN9XuCPgOXZ3J1mio WOp8y+gPMpoLVDrgFgpnfBIaja3xueaQHsy8IAqGOjYS1szhRgr5iFNr9x/zu8fVY8OK hKfDUMDrQhBpav6rzIIOOcVIBXxoAyfZ3ERTUdDpKgfRAN6M3SUbeHAU9KzVpQZ35P7Y oHRMNx6qb8L/Xx3i2BwMBxyGAVSV24Zvqc1szMBnpVkP9qTK3Nc+rUj4C2PhGnt6joam hDmeNKfNBYKEeDit7fVw5bv0QG/FHkDFfASawPzEopMoljULmFUa24SKecuj+y/h39hz uA== Received: from nasanppmta03.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3nruta0ffr-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 15 Feb 2023 11:28:47 +0000 Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 31FBSk9H027037 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 15 Feb 2023 11:28:46 GMT Received: from qc-i7.hemma.eciton.net (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Wed, 15 Feb 2023 03:28:43 -0800 Date: Wed, 15 Feb 2023 11:28:40 +0000 From: "Leif Lindholm" To: , CC: Rebecca Cran , , Rebecca Cran , , , Tinh Nguyen , Subject: Re: [edk2-devel] [edk2-platforms][PATCH 1/1] AmpereAltraPkg: Update ArmPlatformLib to work with changed ARM_CORE_INFO Message-ID: References: <20230113042126.3107135-1-nhi@os.amperecomputing.com> <7d401f29-56d9-d754-88a6-684ce329a727@quicinc.com> <25ee195f-85ee-d783-7e5c-f0da8b9972b4@quicinc.com> <923d3222-775c-f0e8-b4c1-4c10f122ad0a@bsdio.com> <3b16465b-6f2a-8bda-98b5-ddfbef68aa41@amperemail.onmicrosoft.com> MIME-Version: 1.0 In-Reply-To: <3b16465b-6f2a-8bda-98b5-ddfbef68aa41@amperemail.onmicrosoft.com> X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: HCdNyhwtnDvr2kC6rFR7RTLMtpZrmezD X-Proofpoint-GUID: HCdNyhwtnDvr2kC6rFR7RTLMtpZrmezD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.170.22 definitions=2023-02-15_06,2023-02-15_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 priorityscore=1501 malwarescore=0 bulkscore=0 impostorscore=0 mlxlogscore=539 spamscore=0 clxscore=1011 adultscore=0 phishscore=0 mlxscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2302150103 X-MIME-Autoconverted: from 8bit to quoted-printable by mx0a-0031df01.pphosted.com id 31F8Kxi5024398 Content-Type: text/plain; charset="iso-8859-1" Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Tue, Jan 31, 2023 at 13:35:50 +0700, Nhi Pham via groups.io wrote: > Hi Rebecca, >=20 > ++ Harb who can give more insights on this. FYI, the original concern i= s > https://edk2.groups.io/g/devel/message/98482 >=20 > On 1/18/2023 1:21 AM, Rebecca Cran wrote: > > On 1/17/23 09:40, Ard Biesheuvel wrote: > > > On Tue, 17 Jan 2023 at 13:55, Rebecca Cran wr= ote: > > > > I was under the impression that this is becoming a more standard = format? > > > >=20 > > > If this is not defined in an ARM spec somewhere, we shouldn't add i= t > > > to ArmPkg at this point. > >=20 > > From what I've found, the ARM specs such as the Arm Architecture > > Reference Manual for A-profile architecture don't define the meaning = of > > the affinity fields? That appears to be left up to the individual Arm > > core TRMs. >=20 > I think so. This might be silicon specific implementation. >=20 > Per Arm Armv8-A Architecture Registers (https://developer.arm.com/docum= entation/ddi0595/2021-12/AArch64-Registers/MPIDR-EL1--Multiprocessor-Affi= nity-Register), > if I interpret correctly, the AFF0 will give core ID or thread ID based= on > the MT bit in the MPIDR register. >=20 > I think we should remove the following definitions particularly for get= ting > core id and cluster in ArmPkg/Include/Library/ArmLib.h to avoid the > confusion to others >=20 > #define ARM_CORE_MASK=A0=A0=A0=A0=A0=A0=A0=A0 ARM_CORE_AFF0 > #define ARM_CLUSTER_MASK=A0=A0=A0=A0=A0 ARM_CORE_AFF1 > #define GET_CORE_ID(MpId)=A0=A0=A0=A0 ((MpId) & ARM_CORE_MASK) > #define GET_CLUSTER_ID(MpId)=A0 (((MpId) & ARM_CLUSTER_MASK) >> 8) > #define GET_MPID(ClusterId, CoreId)=A0=A0 (((ClusterId) << 8) | (CoreId= )) > #define PRIMARY_CORE_ID=A0=A0=A0=A0=A0=A0 (PcdGet32(PcdArmPrimaryCore) = & ARM_CORE_MASK) >=20 > And, should support GET_AFFx like >=20 > #define ARM_MPIDR_GET_AFF0(Mpid) ((Mpid) & ARM_CORE_AFF0) >=20 > For silicon specific usage, it can abstract them to proper IDs like >=20 > #define XXX_GET_CORE_ID(Mpid) ARM_MPIDR_GET_AFF0(Mpid) And we could hide that selection behind a Pcd. Then we'd not need anything platform-specific other than overriding the default Pcd value. / Leif