From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pg1-f169.google.com (mail-pg1-f169.google.com [209.85.215.169]) by mx.groups.io with SMTP id smtpd.web11.22.1665678652406654974 for ; Thu, 13 Oct 2022 09:30:52 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@ventanamicro.com header.s=google header.b=I7tIGyJp; spf=pass (domain: ventanamicro.com, ip: 209.85.215.169, mailfrom: sunilvl@ventanamicro.com) Received: by mail-pg1-f169.google.com with SMTP id s196so695931pgs.3 for ; Thu, 13 Oct 2022 09:30:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=673syvHn6S427To/GpcLyfBadvt0GLOlvEEyXS6ztGE=; b=I7tIGyJphPeo/2fm/uVUnEcFO0M5czb/3fYSWcx2jzS1HfPClmj3ZW1ReKK6HUwgi4 tDXYrKLOAwzIkX9cFUdR/5g58yItfbE/dtI6VlIckHzalkYPr6viHr1kYHXUEdAG9gBs Vt4MpZfJH2XBUeqXS9UhZMazQ51T0Wi+7s8Fl6vMCy+ZTIjpAAdUpStqPdgdi4+huJcO u51sTn01A+9OroUitsgJoFSENiyjcDgKM9bVVrG4MnmkZ4o0u4D8Q6yimMUhklMhHUlq SBzm6GzcwEfhMQA1ssdftjFvt4cw5ksblKQ6TVE1iHheAHbLJ4OBHJL5+6L7vSMRDbmJ Oo4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=673syvHn6S427To/GpcLyfBadvt0GLOlvEEyXS6ztGE=; b=adS6NWnER+dWX+An1/SX0W46fSHhqwt66goGhxl8cbvtWbkaZa7RDIgcGTfx2Vy+A/ r02zT64qMBjmdP9Lpsmwwm7PCOwoNg3VlLyXycWpg9H6CQYx6oCw8m6vzgIIz30SegY6 21ZjwGrPGaFIJ7+R6Q5qzoBJoztwuuT8KQ0eQ6owpF13p7SxyNMRtyluy9kWRFvm0jbP fOTx+hEFOxRNRRb186i7Y46PqJ6ZjxLFT4C2qdWYSj+9YbhBylQ/mjbhRieSLAYz53cs 8j/O+y4W/LbAG1AxqxcRj7DXuWKzDwn1l6M2H1xgZO+yBL6fSUWOOu90hsiUFDS6avtn yFAQ== X-Gm-Message-State: ACrzQf1UT469bqWJWXlIcMcl/BgKvOQkGXJdcVxf9Vz+1RydNzWlRQJm LWWPcyAjVgdDr3rEcJ4NtxO3Vw== X-Google-Smtp-Source: AMsMyM61LyO1bB6jk1tAa0bQMulNJFUZro+ad2Ol442pkyR49Y4jjLFmna8DfixDT0YUfNqoxpMcxw== X-Received: by 2002:a63:43c2:0:b0:46a:eec8:9430 with SMTP id q185-20020a6343c2000000b0046aeec89430mr644923pga.6.1665678651808; Thu, 13 Oct 2022 09:30:51 -0700 (PDT) Return-Path: Received: from sunil-laptop ([49.206.13.138]) by smtp.gmail.com with ESMTPSA id p9-20020a1709027ec900b00176ab6a0d5fsm91134plb.54.2022.10.13.09.30.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Oct 2022 09:30:51 -0700 (PDT) Date: Thu, 13 Oct 2022 22:00:46 +0530 From: "Sunil V L" To: "Chang, Abner" Cc: "devel@edk2.groups.io" , Daniel Schaefer , Michael D Kinney , Liming Gao , Zhiguang Liu Subject: Re: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 01/34] MdePkg/Register: Add register definition header files for RISC-V Message-ID: References: <20221013095829.1454581-1-sunilvl@ventanamicro.com> <20221013095829.1454581-2-sunilvl@ventanamicro.com> MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Thu, Oct 13, 2022 at 12:59:32PM +0000, Chang, Abner wrote: > [AMD Official Use Only - General] > > > > > -----Original Message----- > > From: devel@edk2.groups.io On Behalf Of Sunil V L > > via groups.io > > Sent: Thursday, October 13, 2022 5:58 PM > > To: devel@edk2.groups.io > > Cc: Daniel Schaefer ; Michael D Kinney > > ; Liming Gao ; > > Zhiguang Liu > > Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 01/34] > > MdePkg/Register: Add register definition header files for RISC-V > > > > Caution: This message originated from an External Source. Use proper > > caution when opening attachments, clicking links, or responding. > > > > > > REF: > > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugz > > illa.tianocore.org%2Fshow_bug.cgi%3Fid%3D4076&data=05%7C01%7Ca > > bner.chang%40amd.com%7C7e426705a0a5494fddb608daad0188ff%7C3dd89 > > 61fe4884e608e11a82d994e183d%7C0%7C0%7C638012519360901317%7CUnkn > > own%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik > > 1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=brw9id8sl20kW > > gKGn0ltbrgPxdRwNZvA2nOCX3CAidU%3D&reserved=0 > > > > Add register definitions and access routines for RISC-V. These headers are > > leveraged from opensbi repo. > > > > Cc: Daniel Schaefer > > Cc: Michael D Kinney > > Cc: Liming Gao > > Cc: Zhiguang Liu > > Signed-off-by: Sunil V L > > --- > > .../Include/Register/RiscV64/RiscVEncoding.h | 125 ++++++++++++++++++ > > MdePkg/Include/Register/RiscV64/RiscVImpl.h | 25 ++++ > > 2 files changed, 150 insertions(+) > > create mode 100644 MdePkg/Include/Register/RiscV64/RiscVEncoding.h > > create mode 100644 MdePkg/Include/Register/RiscV64/RiscVImpl.h > > > > diff --git a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h > > b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h > > new file mode 100644 > > index 000000000000..434436b37fcf > > --- /dev/null > > +++ b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h > > @@ -0,0 +1,125 @@ > > +/** @file > > + RISC-V CSR encodings > > + > > + Copyright (c) 2019, Western Digital Corporation or its affiliates. > > + All rights reserved.
Copyright (c) 2022, Ventana Micro Systems > > + Inc. All rights reserved.
> > + SPDX-License-Identifier: BSD-2-Clause-Patent > > + > > +**/ > > + > > +#ifndef RISCV_ENCODING_H_ > > +#define RISCV_ENCODING_H_ > > + > > +/* clang-format off */ > > +#define MSTATUS_SIE 0x00000002UL > > +#define MSTATUS_MIE 0x00000008UL > > +#define MSTATUS_SPIE_SHIFT 5 > > +#define MSTATUS_SPIE (1UL << MSTATUS_SPIE_SHIFT) > > +#define MSTATUS_UBE 0x00000040UL > > +#define MSTATUS_MPIE 0x00000080UL > > +#define MSTATUS_SPP_SHIFT 8 > > +#define MSTATUS_SPP (1UL << MSTATUS_SPP_SHIFT) > > +#define MSTATUS_MPP_SHIFT 11 > > +#define MSTATUS_MPP (3UL << MSTATUS_MPP_SHIFT) > > + > > +#define SSTATUS_SIE MSTATUS_SIE > > +#define SSTATUS_SPIE_SHIFT MSTATUS_SPIE_SHIFT > > +#define SSTATUS_SPIE MSTATUS_SPIE > > +#define SSTATUS_SPP_SHIFT MSTATUS_SPP_SHIFT > > +#define SSTATUS_SPP MSTATUS_SPP > > + > > +#define IRQ_S_SOFT 1 > > +#define IRQ_VS_SOFT 2 > > +#define IRQ_M_SOFT 3 > > +#define IRQ_S_TIMER 5 > > +#define IRQ_VS_TIMER 6 > > +#define IRQ_M_TIMER 7 > > +#define IRQ_S_EXT 9 > > +#define IRQ_VS_EXT 10 > > +#define IRQ_M_EXT 11 > > +#define IRQ_S_GEXT 12 > > +#define IRQ_PMU_OVF 13 > > + > > +#define MIP_SSIP (1UL << IRQ_S_SOFT) > > +#define MIP_VSSIP (1UL << IRQ_VS_SOFT) > > +#define MIP_MSIP (1UL << IRQ_M_SOFT) > > +#define MIP_STIP (1UL << IRQ_S_TIMER) > > +#define MIP_VSTIP (1UL << IRQ_VS_TIMER) > > +#define MIP_MTIP (1UL << IRQ_M_TIMER) > > +#define MIP_SEIP (1UL << IRQ_S_EXT) > > +#define MIP_VSEIP (1UL << IRQ_VS_EXT) > > +#define MIP_MEIP (1UL << IRQ_M_EXT) > > +#define MIP_SGEIP (1UL << IRQ_S_GEXT) > > +#define MIP_LCOFIP (1UL << IRQ_PMU_OVF) > > + > > +#define SIP_SSIP MIP_SSIP > > +#define SIP_STIP MIP_STIP > > + > > +#define PRV_U 0UL > > +#define PRV_S 1UL > > +#define PRV_M 3UL > > + > > +#define SATP64_MODE 0xF000000000000000ULL #define SATP64_ASID > > +0x0FFFF00000000000ULL > > +#define SATP64_PPN 0x00000FFFFFFFFFFFULL > > + > > +#define SATP_MODE_OFF 0UL > > +#define SATP_MODE_SV32 1UL > > +#define SATP_MODE_SV39 8UL > > +#define SATP_MODE_SV48 9UL > > +#define SATP_MODE_SV57 10UL > > +#define SATP_MODE_SV64 11UL > > + > > +#define SATP_MODE SATP64_MODE > > + > > +/* ===== User-level CSRs ===== */ > Would you like to have the consistent comment style as /* Supervisor Configuration */ in below (without the equal signs)? Thus the comments are in the same style in this file. > You can fix this in the next version. Sure. Will update the comments. Thanks! > > Not the reviewer or maintainer, however Acked-by: Abner Chang > Thanks > Abner