From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pj1-f49.google.com (mail-pj1-f49.google.com [209.85.216.49]) by mx.groups.io with SMTP id smtpd.web08.42.1665678774196739448 for ; Thu, 13 Oct 2022 09:32:54 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@ventanamicro.com header.s=google header.b=eZ29nkBZ; spf=pass (domain: ventanamicro.com, ip: 209.85.216.49, mailfrom: sunilvl@ventanamicro.com) Received: by mail-pj1-f49.google.com with SMTP id h12so2512085pjk.0 for ; Thu, 13 Oct 2022 09:32:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=GYCUVZFEVehuf56ycLAWaaGxY4k/8JbT9VHwtC0+DBc=; b=eZ29nkBZgweQ0JkS2HDnutRFhzlfarc8n6SXXMPpksCYN3indw8ZLAirmjjyOMWUNy 82UKwq6Of98B8qrG7D5JpDWDvXs4e6GNJA1+0boneS9GIUBCfd/3xQvEAnzaTBXUKb3G 32DUqpt0e5CAuti7lAWGAsLp7L2JlB//IbQx9O0a7aumhQCnnzmCiL3OV1ica8aINab3 BujnQHvEA4JW9ZPYG5zeBL9blaxqVreNWVA39C/2h41CCVvXRbqTSxcj8/KFwQp9/4+2 hVmiHsoYFHDXm6C+Am9BVQoS9aVFQDmO43e4e/hwYExEtomIdbdR+/Trsn2ieo85I3EN R/kQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=GYCUVZFEVehuf56ycLAWaaGxY4k/8JbT9VHwtC0+DBc=; b=0NB9iqESsOvGtRWwc6jfxPQ2QPf8pupXu1cPJ9uYSHwrD5+Yy/jYLcbIQ26BcCTeKm P50I50ZOz97/vuEKi7GZRKjogIKVECfLH7GZbXmALB+SI43nqui/gSH0E/vPZ4EnDpZf r1bRB4oPA5xec8q6uUKsJCeTEdeorRk71z3VaI3Ug1FmLaJRDxqtByl1bjr1ETI3Shlj Z98X6ei8adEAnyD9CWblsVzux/4lNsqsvMTSZITs63u7qEgFDbDpKlvQ+TcfiPd0e9Rw 6rSyxwSPLWhwazav352aoSbjHyCBhGyRqdQcXCamuR8+AzynvRGTxlEjBhMMf4ldyAJa Pjcw== X-Gm-Message-State: ACrzQf3qEmRg6ci9RmFwHvYiMl7T5ktZjUWPsKL6rx1y4rJXie+EPGsG SlPopxA+cPYATw1GrHxhURN+PA== X-Google-Smtp-Source: AMsMyM5A+p2csnljyvrRUxW0E6j5GSvsh7V7ROGvCJAccJyX0dvnmWtfWO1IAHqTMEIqN3g8FaCP3Q== X-Received: by 2002:a17:902:efd4:b0:180:fd88:1255 with SMTP id ja20-20020a170902efd400b00180fd881255mr535652plb.111.1665678773709; Thu, 13 Oct 2022 09:32:53 -0700 (PDT) Return-Path: Received: from sunil-laptop ([49.206.13.138]) by smtp.gmail.com with ESMTPSA id w25-20020aa79559000000b00563176d1701sm2246256pfq.3.2022.10.13.09.32.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Oct 2022 09:32:53 -0700 (PDT) Date: Thu, 13 Oct 2022 22:02:48 +0530 From: "Sunil V L" To: "Chang, Abner" Cc: "devel@edk2.groups.io" , Michael D Kinney , Liming Gao , Zhiguang Liu , Daniel Schaefer Subject: Re: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 03/34] MdePkg/BaseLib: RISC-V: Add few more helper functions Message-ID: References: <20221013095829.1454581-1-sunilvl@ventanamicro.com> <20221013095829.1454581-4-sunilvl@ventanamicro.com> MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Thu, Oct 13, 2022 at 02:10:49PM +0000, Chang, Abner wrote: > [AMD Official Use Only - General] > > > > > -----Original Message----- > > From: devel@edk2.groups.io On Behalf Of Sunil V L > > via groups.io > > Sent: Thursday, October 13, 2022 5:58 PM > > To: devel@edk2.groups.io > > Cc: Michael D Kinney ; Liming Gao > > ; Zhiguang Liu ; Daniel > > Schaefer > > Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 03/34] > > MdePkg/BaseLib: RISC-V: Add few more helper functions > > > > Caution: This message originated from an External Source. Use proper > > caution when opening attachments, clicking links, or responding. > > > > > > REF: > > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugz > > illa.tianocore.org%2Fshow_bug.cgi%3Fid%3D4076&data=05%7C01%7Ca > > bner.chang%40amd.com%7Cb23d246aae8843c15cd108daad018f1b%7C3dd89 > > 61fe4884e608e11a82d994e183d%7C0%7C0%7C638012519458082377%7CUnkn > > own%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik > > 1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=Kflz7rvGivG00Ij > > 6thrbhdf%2Bd1hVU7wBxEi45P6Ti0k%3D&reserved=0 > > > > Few of the basic helper functions required for any RISC-V CPU were added in > > edk2-platforms. To support qemu virt, they need to be added in BaseLib. > > > > Cc: Michael D Kinney > > Cc: Liming Gao > > Cc: Zhiguang Liu > > Cc: Daniel Schaefer > > Signed-off-by: Sunil V L > > --- > > MdePkg/Library/BaseLib/BaseLib.inf | 2 + > > MdePkg/Include/Library/BaseLib.h | 50 +++++++++++++++++ > > MdePkg/Library/BaseLib/RiscV64/CpuScratch.S | 31 +++++++++++ > > MdePkg/Library/BaseLib/RiscV64/ReadTimer.S | 24 +++++++++ > > .../Library/BaseLib/RiscV64/RiscVInterrupt.S | 53 +++++++++++++++++-- > > 5 files changed, 156 insertions(+), 4 deletions(-) create mode 100644 > > MdePkg/Library/BaseLib/RiscV64/CpuScratch.S > > create mode 100644 MdePkg/Library/BaseLib/RiscV64/ReadTimer.S > > > > diff --git a/MdePkg/Library/BaseLib/BaseLib.inf > > b/MdePkg/Library/BaseLib/BaseLib.inf > > index 6be5be9428f2..86d7bb080971 100644 > > --- a/MdePkg/Library/BaseLib/BaseLib.inf > > +++ b/MdePkg/Library/BaseLib/BaseLib.inf > > @@ -401,6 +401,8 @@ [Sources.RISCV64] > > RiscV64/RiscVCpuPause.S | GCC > > RiscV64/RiscVInterrupt.S | GCC > > RiscV64/FlushCache.S | GCC > > + RiscV64/CpuScratch.S | GCC > > + RiscV64/ReadTimer.S | GCC > > > > [Packages] > > MdePkg/MdePkg.dec > > diff --git a/MdePkg/Include/Library/BaseLib.h > > b/MdePkg/Include/Library/BaseLib.h > > index a6f9a194ef1c..9724b84eef89 100644 > > --- a/MdePkg/Include/Library/BaseLib.h > > +++ b/MdePkg/Include/Library/BaseLib.h > > @@ -150,6 +150,56 @@ typedef struct { > > > > #define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8 > > > > +VOID > > + RiscVSetSupervisorScratch ( > > + UINT64 > > + ); > > + > > +UINT64 > > +RiscVGetSupervisorScratch ( > > + VOID > > + ); > > + > > +VOID > > + RiscVSetSupervisorStvec ( > > + UINT64 > > + ); > > + > > +UINT64 > > +RiscVGetSupervisorStvec ( > > + VOID > > + ); > > + > > +UINT64 > > +RiscVGetSupervisorTrapCause ( > > + VOID > > + ); > > + > > +VOID > > + RiscVSetSupervisorAddressTranslationRegister ( > > + UINT64 > > + ); > > + > > +UINT64 > > +RiscVReadTimer ( > > + VOID > > + ); > > + > > +VOID > > +RiscVEnableTimerInterrupt ( > > + VOID > > + ); > > + > > +VOID > > +RiscVDisableTimerInterrupt ( > > + VOID > > + ); > > + > > +VOID > > +RiscVClearPendingTimerInterrupt ( > > + VOID > > + ); > > + > > #endif // defined (MDE_CPU_RISCV64) > > > > // > > diff --git a/MdePkg/Library/BaseLib/RiscV64/CpuScratch.S > > b/MdePkg/Library/BaseLib/RiscV64/CpuScratch.S > > new file mode 100644 > > index 000000000000..dd7adc21eb07 > > --- /dev/null > > +++ b/MdePkg/Library/BaseLib/RiscV64/CpuScratch.S > > @@ -0,0 +1,31 @@ > > +//--------------------------------------------------------------------- > > +--------- > > +// > > +// CPU scratch register related functions for RISC-V // // Copyright > > +(c) 2020, Hewlett Packard Enterprise Development LP. All rights > > +reserved.
// // SPDX-License-Identifier: BSD-2-Clause-Patent // > > +//--------------------------------------------------------------------- > > +--------- > > + > > +#include > > + > > +.data > > +.align 3 > > +.section .text > > + > > +// > > +// Set Supervisor mode scratch. > > +// @param a0 : Value set to Supervisor mode scratch // ASM_FUNC > > +(RiscVSetSupervisorScratch) > > + csrrw a1, CSR_SSCRATCH, a0 > > + ret > > + > > +// > > +// Get Supervisor mode scratch. > > +// @retval a0 : Value in Supervisor mode scratch // ASM_FUNC > > +(RiscVGetSupervisorScratch) > > + csrr a0, CSR_SSCRATCH > > + ret > > diff --git a/MdePkg/Library/BaseLib/RiscV64/ReadTimer.S > > b/MdePkg/Library/BaseLib/RiscV64/ReadTimer.S > > new file mode 100644 > > index 000000000000..bdddb67618ab > > --- /dev/null > > +++ b/MdePkg/Library/BaseLib/RiscV64/ReadTimer.S > Hi Sunil, > Where is this code comes from? Was it written by HPE? If not then you can remove HPE copyright, otherwise please remove Ventana. > Thanks > Abner Yes, I think I missed some of these files after your recommendation last time. Will remove Ventana. This is existing code in edk2-platforms repo just with different name. Thanks! Sunil