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From: "Sunil V L" <sunilvl@ventanamicro.com>
To: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Cc: Jian J Wang <jian.j.wang@intel.com>,
	Liming Gao <gaoliming@byosoft.com.cn>,
	Eric Dong <eric.dong@intel.com>, Ray Ni <ray.ni@intel.com>,
	Rahul Kumar <rahul1.kumar@intel.com>,
	Debkumar De <debkumar.de@intel.com>,
	Catharine West <catharine.west@intel.com>,
	Daniel Schaefer <git@danielschaefer.me>,
	Abner Chang <Abner.Chang@amd.com>,
	Leif Lindholm <quic_llindhol@quicinc.com>,
	Andrew Fish <afish@apple.com>, Ard Biesheuvel <ardb@kernel.org>,
	Anup Patel <apatel@ventanamicro.com>,
	devel@edk2.groups.io
Subject: Re: [RFC PATCH V2 06/19] MdePkg/BaseLib: RISC-V: Add generic CPU related functions
Date: Thu, 8 Dec 2022 10:34:05 +0530	[thread overview]
Message-ID: <Y5FwRQ7Vh2TfnYGz@sunil-laptop> (raw)
In-Reply-To: <6b7b1657-822f-2407-911c-c372d8f6d0e3@canonical.com>

On Thu, Dec 08, 2022 at 02:43:56AM +0100, Heinrich Schuchardt wrote:
> 
> 
> On 9/7/22 13:36, Sunil V L wrote:
> > EDK2 in S-mode needs to use SSCRATCH register. Implement functions
> > to set/get the SSCRATCH register.
> > 
> > Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> > ---
> >   MdePkg/Library/BaseLib/BaseLib.inf      |  1 +
> >   MdePkg/Include/Library/BaseLib.h        | 10 ++++++
> >   MdePkg/Library/BaseLib/RiscV64/CpuGen.S | 33 ++++++++++++++++++++
> >   3 files changed, 44 insertions(+)
> > 
> > diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf
> > index 6be5be9428f2..5429329e39b0 100644
> > --- a/MdePkg/Library/BaseLib/BaseLib.inf
> > +++ b/MdePkg/Library/BaseLib/BaseLib.inf
> > @@ -401,6 +401,7 @@ [Sources.RISCV64]
> >     RiscV64/RiscVCpuPause.S           | GCC
> >     RiscV64/RiscVInterrupt.S          | GCC
> >     RiscV64/FlushCache.S              | GCC
> > +  RiscV64/CpuGen.S                  | GCC
> >   [Packages]
> >     MdePkg/MdePkg.dec
> > diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
> > index a6f9a194ef1c..a742de61a442 100644
> > --- a/MdePkg/Include/Library/BaseLib.h
> > +++ b/MdePkg/Include/Library/BaseLib.h
> > @@ -150,6 +150,16 @@ typedef struct {
> >   #define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT  8
> > +VOID
> > +RiscVSetSupervisorScratch (
> > +  UINT64
> > +  );
> > +
> > +UINT64
> > +RiscVGetSupervisorScratch (
> > +  VOID
> > +  );
> > +
> >   #endif // defined (MDE_CPU_RISCV64)
> >   //
> > diff --git a/MdePkg/Library/BaseLib/RiscV64/CpuGen.S b/MdePkg/Library/BaseLib/RiscV64/CpuGen.S
> > new file mode 100644
> > index 000000000000..d11929cf3233
> > --- /dev/null
> > +++ b/MdePkg/Library/BaseLib/RiscV64/CpuGen.S
> > @@ -0,0 +1,33 @@
> > +//------------------------------------------------------------------------------
> > +//
> > +// Generic CPU related functions for RISC-V
> > +//
> > +// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> > +// Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR>
> > +//
> > +// SPDX-License-Identifier: BSD-2-Clause-Patent
> > +//
> > +//------------------------------------------------------------------------------
> > +
> > +#include <Register/RiscV64/RiscVAsm.h>
> > +#include <Register/RiscV64/RiscVImpl.h>
> > +
> > +.data
> > +.align 3
> > +.section .text
> > +
> > +//
> > +// Set Supervisor mode scratch.
> > +// @param a0 : Value set to Supervisor mode scratch
> > +//
> > +ASM_FUNC (RiscVSetSupervisorScratch)
> > +    csrrw a1, CSR_SSCRATCH, a0
> > +    ret
> 
> I am wondering why you are reading the old value into a1 while the function
> has a VOID return value.
> 
> If you are not interested in reading the old value, the "RISC-V Unprivileged
> ISA Specification" suggests to use the x0 (zero) register as read register
> or just use the CSRW pseudo code.
> 

Hi Heinrich,

Many thanks!. I agree. Will fix this and your inputs for other patches.

BTW, https://edk2.groups.io/g/devel/message/95726 was the latest series
after couple of design discussions. But your comments are still valid.
Will update this series and send the next version.

Thanks!
Sunil

  reply	other threads:[~2022-12-08  5:04 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-07 11:36 [RFC PATCH V2 00/19] Refactor and add RISC-V support in edk2 repo Sunil V L
2022-09-07 11:36 ` [RFC PATCH V2 01/19] MdePkg/Register: Add register definition header files for RISC-V Sunil V L
2022-09-07 11:36 ` [RFC PATCH V2 02/19] MdePkg/MdePkg.dec: Add RISCV_EFI_BOOT_PROTOCOL GUID Sunil V L
2022-12-08  1:21   ` Heinrich Schuchardt
2022-09-07 11:36 ` [RFC PATCH V2 03/19] MdePkg/Protocol: Add RiscVBootProtocol.h Sunil V L
2022-12-08  1:24   ` Heinrich Schuchardt
2022-09-07 11:36 ` [RFC PATCH V2 04/19] MdeModulePkg/MdeModulePkg.dec: Add PCD variables for RISC-V Sunil V L
2022-09-07 11:36 ` [RFC PATCH V2 05/19] UefiCpuPkg.dec: Add PCD variable " Sunil V L
2022-09-07 11:36 ` [RFC PATCH V2 06/19] MdePkg/BaseLib: RISC-V: Add generic CPU related functions Sunil V L
2022-12-08  1:43   ` Heinrich Schuchardt
2022-12-08  5:04     ` Sunil V L [this message]
2022-09-07 11:36 ` [RFC PATCH V2 07/19] MdePkg: Add ArchTimerLib library Sunil V L
2022-12-08  1:59   ` Heinrich Schuchardt
2022-09-07 11:36 ` [RFC PATCH V2 08/19] MdePkg: Add RiscVSbiLib Library for RISC-V Sunil V L
2022-12-08  2:22   ` Heinrich Schuchardt
2022-09-07 11:36 ` [RFC PATCH V2 09/19] UefiCpuPkg: Update Sources in DxeCpuExceptionHandlerLib.inf Sunil V L
2022-09-07 11:36 ` [RFC PATCH V2 10/19] UefiCpuPkg: Add RISC-V support in DxeCpuExceptionHandlerLib Sunil V L
2022-12-08  0:30   ` [edk2-devel] " Ni, Ray
2022-12-08  4:58     ` Sunil V L
2022-12-08  8:32       ` Ni, Ray
2022-12-14  9:38         ` Leif Lindholm
2022-12-14 12:37           ` Ni, Ray
2022-12-16  5:22             ` Sunil V L
2022-09-07 11:36 ` [RFC PATCH V2 11/19] MdePkg/Library: Add ResetSystemLib library Sunil V L
2022-09-07 11:36 ` [RFC PATCH V2 12/19] UefiCpuPkg/SecCore: Add SEC startup code for RISC-V Sunil V L
2022-09-07 11:36 ` [RFC PATCH V2 13/19] MdePkg: Add PlatformPeiLib library Sunil V L
2022-09-07 11:36 ` [RFC PATCH V2 14/19] MdeModulePkg/Universal: Add PlatformPei module for RISC-V Sunil V L
2022-09-07 11:36 ` [RFC PATCH V2 15/19] UefiCpuPkg/CpuDxe: Refactor to allow other CPU architectures Sunil V L
2022-09-07 11:36 ` [RFC PATCH V2 16/19] UefiCpuPkg/CpuDxe: Add RISC-V support in CpuDxe module Sunil V L
2022-09-07 11:36 ` [RFC PATCH V2 17/19] MdeModulePkg/Universal: Add TimerDxe module Sunil V L
2022-09-07 11:36 ` [RFC PATCH V2 18/19] RISC-V: Add Qemu Virt platform support Sunil V L
2022-12-08  2:33   ` Heinrich Schuchardt
  -- strict thread matches above, loose matches on Subject: below --
2022-09-07 11:11 [RFC PATCH V2 00/19] Refactor and add RISC-V support in edk2 repo Sunil V L
2022-09-07 11:11 ` [RFC PATCH V2 06/19] MdePkg/BaseLib: RISC-V: Add generic CPU related functions Sunil V L

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