From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-oi1-f175.google.com (mail-oi1-f175.google.com [209.85.167.175]) by mx.groups.io with SMTP id smtpd.web11.6149.1670475856102707568 for ; Wed, 07 Dec 2022 21:04:16 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@ventanamicro.com header.s=google header.b=ZlImQuPO; spf=pass (domain: ventanamicro.com, ip: 209.85.167.175, mailfrom: sunilvl@ventanamicro.com) Received: by mail-oi1-f175.google.com with SMTP id m204so307290oib.6 for ; Wed, 07 Dec 2022 21:04:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=Fl7hAHhSyOxNK4g67SH9MpMiZVIzn+ZpIhaQXR6SzEk=; b=ZlImQuPObOdzQLneadNGV4Wt757kahFDZ3tTKowIj0m3goHSs3cSs82MYDy3CIjhDH Di9W460pbFrjq3Yeht9IPVBtJrHkvm5ij0mvcyDSbiL+zgYQ7Kf2oV2UY0kDqnSoBw46 +Fb1dWH1uy+TrzY65OFvoNq7UMCpzVttXo+jZKcammkH+QqvdNbeYC2dzZO917bgahcK 5l/C4VpGEsgY0pQQKTs/Xe9MG6wB20Wq7+KxRpuigVXJOd53Iab7QPb9X7R3idIM4RHy 8vpiuXW1CdwKwn7bzHp2+cCgqSrpu4wq6b9AM9+rHreJBQMbPmTui/0gr/XqzCtO7lXe zGnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=Fl7hAHhSyOxNK4g67SH9MpMiZVIzn+ZpIhaQXR6SzEk=; b=KlXH1EBWewKTQNM44XBYld/uEHPQCPGl8aZQT8PoSttWT2pRuSbdXx3Y5S1I/UQgfp cAhkmpdXiLxYwK3ojsxe4dn98HhgIbHZ/T2CUQ6YNAHY8nZs8ekw+TqOM/TfYDiacRT4 5YRkhJz5II32aL6prZtkr+4WisTVvj8qb1ifXHZwQr1vT14QqmWSMrmhyqbRAm+BYXW3 2ruicWUVtvuK+njro6xVtQyOmh4oV0bBrlYW4uzbSAKut9jFIYa2VSJ6+opkzapkUSEP FOG+ui/WzCMuO630p5mlZD0Vz8eOnU0vfH1PYzaUfgFMz/x7WX/RpRLSBbdkBCUJ6fZm e2gg== X-Gm-Message-State: ANoB5plU3GzOcp+fFOUhwJeypEa2uTixwXnqFawqcYI3J6ZpFh2+3RtF hdg27I4WFNwAyTp4z/sXi2fL/A== X-Google-Smtp-Source: AA0mqf6DAQpoGi3MtoG1WvzAliXpXtea30ib0tKG6VD59tCHAWzCE2illA83PxaI8z1COsl3rB0hYg== X-Received: by 2002:a05:6808:170b:b0:355:1de9:653f with SMTP id bc11-20020a056808170b00b003551de9653fmr772145oib.33.1670475855434; Wed, 07 Dec 2022 21:04:15 -0800 (PST) Return-Path: Received: from sunil-laptop ([49.206.14.51]) by smtp.gmail.com with ESMTPSA id s131-20020acac289000000b003539686cb7bsm10143513oif.53.2022.12.07.21.04.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Dec 2022 21:04:14 -0800 (PST) Date: Thu, 8 Dec 2022 10:34:05 +0530 From: "Sunil V L" To: Heinrich Schuchardt Cc: Jian J Wang , Liming Gao , Eric Dong , Ray Ni , Rahul Kumar , Debkumar De , Catharine West , Daniel Schaefer , Abner Chang , Leif Lindholm , Andrew Fish , Ard Biesheuvel , Anup Patel , devel@edk2.groups.io Subject: Re: [RFC PATCH V2 06/19] MdePkg/BaseLib: RISC-V: Add generic CPU related functions Message-ID: References: <20220907113626.540065-1-sunilvl@ventanamicro.com> <20220907113626.540065-7-sunilvl@ventanamicro.com> <6b7b1657-822f-2407-911c-c372d8f6d0e3@canonical.com> MIME-Version: 1.0 In-Reply-To: <6b7b1657-822f-2407-911c-c372d8f6d0e3@canonical.com> Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Thu, Dec 08, 2022 at 02:43:56AM +0100, Heinrich Schuchardt wrote: > > > On 9/7/22 13:36, Sunil V L wrote: > > EDK2 in S-mode needs to use SSCRATCH register. Implement functions > > to set/get the SSCRATCH register. > > > > Signed-off-by: Sunil V L > > --- > > MdePkg/Library/BaseLib/BaseLib.inf | 1 + > > MdePkg/Include/Library/BaseLib.h | 10 ++++++ > > MdePkg/Library/BaseLib/RiscV64/CpuGen.S | 33 ++++++++++++++++++++ > > 3 files changed, 44 insertions(+) > > > > diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf > > index 6be5be9428f2..5429329e39b0 100644 > > --- a/MdePkg/Library/BaseLib/BaseLib.inf > > +++ b/MdePkg/Library/BaseLib/BaseLib.inf > > @@ -401,6 +401,7 @@ [Sources.RISCV64] > > RiscV64/RiscVCpuPause.S | GCC > > RiscV64/RiscVInterrupt.S | GCC > > RiscV64/FlushCache.S | GCC > > + RiscV64/CpuGen.S | GCC > > [Packages] > > MdePkg/MdePkg.dec > > diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h > > index a6f9a194ef1c..a742de61a442 100644 > > --- a/MdePkg/Include/Library/BaseLib.h > > +++ b/MdePkg/Include/Library/BaseLib.h > > @@ -150,6 +150,16 @@ typedef struct { > > #define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8 > > +VOID > > +RiscVSetSupervisorScratch ( > > + UINT64 > > + ); > > + > > +UINT64 > > +RiscVGetSupervisorScratch ( > > + VOID > > + ); > > + > > #endif // defined (MDE_CPU_RISCV64) > > // > > diff --git a/MdePkg/Library/BaseLib/RiscV64/CpuGen.S b/MdePkg/Library/BaseLib/RiscV64/CpuGen.S > > new file mode 100644 > > index 000000000000..d11929cf3233 > > --- /dev/null > > +++ b/MdePkg/Library/BaseLib/RiscV64/CpuGen.S > > @@ -0,0 +1,33 @@ > > +//------------------------------------------------------------------------------ > > +// > > +// Generic CPU related functions for RISC-V > > +// > > +// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
> > +// Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
> > +// > > +// SPDX-License-Identifier: BSD-2-Clause-Patent > > +// > > +//------------------------------------------------------------------------------ > > + > > +#include > > +#include > > + > > +.data > > +.align 3 > > +.section .text > > + > > +// > > +// Set Supervisor mode scratch. > > +// @param a0 : Value set to Supervisor mode scratch > > +// > > +ASM_FUNC (RiscVSetSupervisorScratch) > > + csrrw a1, CSR_SSCRATCH, a0 > > + ret > > I am wondering why you are reading the old value into a1 while the function > has a VOID return value. > > If you are not interested in reading the old value, the "RISC-V Unprivileged > ISA Specification" suggests to use the x0 (zero) register as read register > or just use the CSRW pseudo code. > Hi Heinrich, Many thanks!. I agree. Will fix this and your inputs for other patches. BTW, https://edk2.groups.io/g/devel/message/95726 was the latest series after couple of design discussions. But your comments are still valid. Will update this series and send the next version. Thanks! Sunil