From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp-relay-internal-1.canonical.com (smtp-relay-internal-1.canonical.com [185.125.188.123]) by mx.groups.io with SMTP id smtpd.web11.4305.1672348241869416970 for ; Thu, 29 Dec 2022 13:10:42 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@canonical.com header.s=20210705 header.b=o2ip7/0g; spf=pass (domain: canonical.com, ip: 185.125.188.123, mailfrom: dann.frazier@canonical.com) Received: from mail-io1-f72.google.com (mail-io1-f72.google.com [209.85.166.72]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by smtp-relay-internal-1.canonical.com (Postfix) with ESMTPS id 64D1B418CF for ; Thu, 29 Dec 2022 21:10:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=canonical.com; s=20210705; t=1672348238; bh=RR3HdI6M45c17iC9n0ronT4K0medilIQ5xmHJFNm1zY=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:In-Reply-To; b=o2ip7/0gKj7EXtwd/gbTaNJ34EUAFosj05koju6JPYUVJy5/qLkfhrk+231ycs+Rb hP28VbliZu7Hd+mcyJSIBVLSraA82MU9unVlmDTl4cCZUP6q4ti8Ji3EE8BsH+nb6P gxZlzoSa5Ii0uObqMayci40/TZEj2jrzG+4xFP4sy4jWlhKCg8Qv/0lx3HeWl8gYAY iSkYw+KnoSJ7vgb/69W5VU9FfhpVT3NXyyfrgQPpFSbptr27Q0ZgKyYLlrpwF7eJtX zIxfWwAX8oJOlIiiMe6+kOXvFRs9l15+GoVpQ9wZ1sElIApwuyJQA1/mAk0lI94U6q IVtiitjVOaRog== Received: by mail-io1-f72.google.com with SMTP id o16-20020a056602225000b006e032e361ccso6223584ioo.13 for ; Thu, 29 Dec 2022 13:10:38 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=RR3HdI6M45c17iC9n0ronT4K0medilIQ5xmHJFNm1zY=; b=bPIwkEv7E/+g0yYuF0S+4hrnSF9tRmmgPUrF5ApYtq/IwzPyddCnf+NkyVJnyqHjJd vZcJ9MT+t7vhuhKyGVI1RLQ2YGWkakwHPEWYYAkGEJ4XZuU5iXqeU9mGoRvYWT9xhUjh VQaz0/yy915+RmyYbY3e0S8wMlWUGJQHJh7rQNUYgJzFS7UD64eppiHEgeUcHezbA2F/ k65TT0aWWm+sIasYOSExfhHEu03BOirRyAhYmA3E3vMjVVPB2UEunHJQNQDTDnluCua+ ZNcAIeRfUEfI9IdYqxOoMWmD3IQsT+PsHRkWwGU5puCdLQaweMBVc0Eyg1WG5JGsi52N NvLA== X-Gm-Message-State: AFqh2koeJtp06Vu2HLSldDP+YAnRAvtFyWKGmKSuy/e+iABr+kGsZAl2 7GP6cBJ3+pqUDRqBwhFNxiI2Ig5FevPxv+i3O/InD096BgZn+i50/cW+FRZMamky1EA9w1zrnjn wWGGytdiqdDGmo4m74BfptvThvXLHRBc= X-Received: by 2002:a05:6e02:1a4b:b0:303:1fe8:e22 with SMTP id u11-20020a056e021a4b00b003031fe80e22mr23210406ilv.21.1672348236657; Thu, 29 Dec 2022 13:10:36 -0800 (PST) X-Google-Smtp-Source: AMrXdXvuMzZOY5Xv9sT19/YT6ucYTeHtYyzyoFyJdiZxXa/ukz3U5kKFV9eH9tv0OaglsKQsTqmRfg== X-Received: by 2002:a05:6e02:1a4b:b0:303:1fe8:e22 with SMTP id u11-20020a056e021a4b00b003031fe80e22mr23210399ilv.21.1672348236386; Thu, 29 Dec 2022 13:10:36 -0800 (PST) Received: from xps13.dannf ([38.15.56.166]) by smtp.gmail.com with ESMTPSA id o8-20020a056e0214c800b0030c048e60bbsm3383697ilk.34.2022.12.29.13.10.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Dec 2022 13:10:35 -0800 (PST) Date: Thu, 29 Dec 2022 14:10:33 -0700 From: "dann frazier" To: devel@edk2.groups.io, ardb@kernel.org Cc: Leif Lindholm , Alexander Graf Subject: Re: [edk2-devel] [PATCH v3 12/16] ArmVirtPkg/ArmVirtQemu: enable initial ID map at early boot Message-ID: References: <20220926082511.2110797-1-ardb@kernel.org> <20220926082511.2110797-13-ardb@kernel.org> MIME-Version: 1.0 In-Reply-To: <20220926082511.2110797-13-ardb@kernel.org> Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Mon, Sep 26, 2022 at 10:25:07AM +0200, Ard Biesheuvel wrote: > Now that we have all the pieces in place, switch the AArch64 version of > ArmVirtQemu to a mode where the first thing it does out of reset is > enable a preliminary ID map that covers the NOR flash and sufficient > DRAM to create the UEFI page tables as usual. > > The advantage of this is that no manipulation of memory occurs any > longer before the MMU is enabled, which removes the need for explicit > coherency management, which is cumbersome and bad for performance. > > It also means we no longer need to build all components that may execute > with the MMU off (including BASE libraries) with strict alignment. After this switch, I'm seeing a Synchronous Exception when launching a VM, though only on old Cavium ThunderX (CN88XX) systems. I used print debugging to narrow it down to ArmSetTTBR0(). Initially I thought it might be related to Cavium Erratum 27456, but that doesn't seem to make sense because the instruction cache isn't enabled until later. I tried implementing the same workaround as Linux does anyway (flush caches after the setting ttbr0) without any luck. Any idea what is going on there? -dann > > Signed-off-by: Ard Biesheuvel > --- > ArmVirtPkg/ArmVirtQemu.dsc | 17 ++++++++++++++--- > ArmVirtPkg/ArmVirtQemu.fdf | 2 +- > 2 files changed, 15 insertions(+), 4 deletions(-) > > diff --git a/ArmVirtPkg/ArmVirtQemu.dsc b/ArmVirtPkg/ArmVirtQemu.dsc > index 302c0d2a4e29..21a321e35794 100644 > --- a/ArmVirtPkg/ArmVirtQemu.dsc > +++ b/ArmVirtPkg/ArmVirtQemu.dsc > @@ -63,8 +63,6 @@ [LibraryClasses.common] > QemuFwCfgSimpleParserLib|OvmfPkg/Library/QemuFwCfgSimpleParserLib/QemuFwCfgSimpleParserLib.inf > QemuLoadImageLib|OvmfPkg/Library/GenericQemuLoadImageLib/GenericQemuLoadImageLib.inf > > - ArmPlatformLib|ArmPlatformPkg/Library/ArmPlatformLibNull/ArmPlatformLibNull.inf > - > TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf > NorFlashPlatformLib|ArmVirtPkg/Library/NorFlashQemuLib/NorFlashQemuLib.inf > > @@ -92,6 +90,12 @@ [LibraryClasses.common] > TpmPlatformHierarchyLib|SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLibNull/PeiDxeTpmPlatformHierarchyLib.inf > !endif > > +[LibraryClasses.AARCH64] > + ArmPlatformLib|ArmVirtPkg/Library/ArmPlatformLibQemu/ArmPlatformLibQemu.inf > + > +[LibraryClasses.ARM] > + ArmPlatformLib|ArmPlatformPkg/Library/ArmPlatformLibNull/ArmPlatformLibNull.inf > + > [LibraryClasses.common.PEIM] > ArmVirtMemInfoLib|ArmVirtPkg/Library/QemuVirtMemInfoLib/QemuVirtMemInfoPeiLib.inf > > @@ -112,6 +116,8 @@ [LibraryClasses.common.UEFI_DRIVER] > UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf > > [BuildOptions] > + GCC:*_*_AARCH64_CC_XIPFLAGS = -mno-strict-align > + > !include NetworkPkg/NetworkBuildOptions.dsc.inc > > ################################################################################ > @@ -310,7 +316,12 @@ [Components.common] > PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf > } > ArmPlatformPkg/PlatformPei/PlatformPeim.inf > - ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf > + ArmVirtPkg/MemoryInitPei/MemoryInitPeim.inf { > + > +!if $(ARCH) == AARCH64 > + ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuPeiLib.inf > +!endif > + } > ArmPkg/Drivers/CpuPei/CpuPei.inf > > MdeModulePkg/Universal/Variable/Pei/VariablePei.inf > diff --git a/ArmVirtPkg/ArmVirtQemu.fdf b/ArmVirtPkg/ArmVirtQemu.fdf > index b5e2253295fe..7f17aeb3ad0d 100644 > --- a/ArmVirtPkg/ArmVirtQemu.fdf > +++ b/ArmVirtPkg/ArmVirtQemu.fdf > @@ -107,7 +107,7 @@ [FV.FVMAIN_COMPACT] > INF ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf > INF MdeModulePkg/Core/Pei/PeiMain.inf > INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf > - INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf > + INF ArmVirtPkg/MemoryInitPei/MemoryInitPeim.inf > INF ArmPkg/Drivers/CpuPei/CpuPei.inf > INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf > INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf