From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pj1-f44.google.com (mail-pj1-f44.google.com [209.85.216.44]) by mx.groups.io with SMTP id smtpd.web10.4149.1672805300660509911 for ; Tue, 03 Jan 2023 20:08:20 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@ventanamicro.com header.s=google header.b=BBRlKwya; spf=pass (domain: ventanamicro.com, ip: 209.85.216.44, mailfrom: sunilvl@ventanamicro.com) Received: by mail-pj1-f44.google.com with SMTP id o2so29447632pjh.4 for ; Tue, 03 Jan 2023 20:08:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=3tmpLWGABJO4eK3QBLO9VV+Sm6zweLTUm0j5srFQ4fc=; b=BBRlKwyazN8JJPFyx4wkuerfBkMCsYwAby4Hzc1TVlxP/Kxj4u3dVxHxN43iTVPoQy maGOTgb7smiiq6l376SwIcfeZOHKK6bjqYvbzoODWP/jPcZbc9+9OgLSGg+1mIr+w+1g wSCQ9eLVE/aL1zqNc8TsMMVcIe1z9K3SaHBYeTu5EeEef8DmeKeVdtrDa/BxwcmdYwPZ neA9R7LFL+psJMkqzIxuUwo+Egd9/pFFiPA1lckw+okLgPcwhaEpYQVOh9en/DPvF1OL kJkMqWoSyH85wGBOEhXwRT0lsJ0fQFNVc8bS2nV5G8DHUdVj1nXKBnr8miybnRhDswV1 /6tw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=3tmpLWGABJO4eK3QBLO9VV+Sm6zweLTUm0j5srFQ4fc=; b=PrKt2tWxZHjB8o/h4SXbbVLz8fGCs6/F+++X3wDz/94a8OU4QdikTrajYTWO2HsfIZ eUVnK8F5Eev1DwlUHK5Xhiqhv0kGzH+aOBBtmnnKpEPhoza7BfUekzBXeodCdJd/mJb1 RJra2ZC2rBViVgomcVmLUqoJeXT51xOp/spBFSvZftO38ZL13oCQOwYnNkgB0XOyypoL kdvXR+OumdiWuLD9IITLjtWB3uhtGnqJ6a2MmIXZW72JW+WO8RJG494iqSwksLideedo Ct/U0vH1hwgRKyHvVzZ4dQm+WkjKZhlrbJcM5dMkzPbh/F1+zmOyaJhIWB/KhqCUYCC1 +pwQ== X-Gm-Message-State: AFqh2kr1DO9u9Q7AcCe3YjHYPbDP65hgacjnTguZDfEvBrG/WKzOvg1J F4KIxMAQhsl7BYrlUR4fAPfLj6eemk8P5nMB X-Google-Smtp-Source: AMrXdXt6nY/sXGA9rFZG2tVCOkhTMA12OL7nmiOBvQIPW+pUVM2Kkvofd/sFznPpcdgnWtten/PK9w== X-Received: by 2002:a17:90a:64c6:b0:225:c04f:e418 with SMTP id i6-20020a17090a64c600b00225c04fe418mr26903545pjm.42.1672805299966; Tue, 03 Jan 2023 20:08:19 -0800 (PST) Return-Path: Received: from sunil-laptop ([49.206.11.246]) by smtp.gmail.com with ESMTPSA id b19-20020a17090a489300b00218bedf8739sm19860937pjh.17.2023.01.03.20.08.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Jan 2023 20:08:19 -0800 (PST) Date: Wed, 4 Jan 2023 09:38:12 +0530 From: "Sunil V L" To: devel@edk2.groups.io Cc: Daniel Schaefer , Michael D Kinney , Liming Gao , Zhiguang Liu , Abner Chang Subject: Re: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V6 01/23] MdePkg/Register: Add register definition header files for RISC-V Message-ID: References: <20221215125626.545372-1-sunilvl@ventanamicro.com> <1730F8C7E4A0D05E.9432@groups.io> MIME-Version: 1.0 In-Reply-To: <1730F8C7E4A0D05E.9432@groups.io> Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Hi MdePkg maintainers, Sorry to bother, but need your attention on PATCH1-PATCH4 of this series. These 4 patches are required by other patches in the series. So, appreciate your help to review and merge if no issues. Thanks! Sunil On Thu, Dec 15, 2022 at 06:26:04PM +0530, Sunil V L via groups.io wrote: > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 > > Add register definitions and access routines for RISC-V. These > headers are leveraged from opensbi repo. > > Cc: Daniel Schaefer > Cc: Michael D Kinney > Cc: Liming Gao > Cc: Zhiguang Liu > Signed-off-by: Sunil V L > Acked-by: Abner Chang > --- > MdePkg/Include/Register/RiscV64/RiscVEncoding.h | 119 ++++++++++++++++++++ > MdePkg/Include/Register/RiscV64/RiscVImpl.h | 25 ++++ > 2 files changed, 144 insertions(+) > > diff --git a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h > new file mode 100644 > index 000000000000..5c2989b797bf > --- /dev/null > +++ b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h > @@ -0,0 +1,119 @@ > +/** @file > + RISC-V CSR encodings > + > + Copyright (c) 2019, Western Digital Corporation or its affiliates. All rights reserved.
> + Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#ifndef RISCV_ENCODING_H_ > +#define RISCV_ENCODING_H_ > + > +#define MSTATUS_SIE 0x00000002UL > +#define MSTATUS_MIE 0x00000008UL > +#define MSTATUS_SPIE_SHIFT 5 > +#define MSTATUS_SPIE (1UL << MSTATUS_SPIE_SHIFT) > +#define MSTATUS_UBE 0x00000040UL > +#define MSTATUS_MPIE 0x00000080UL > +#define MSTATUS_SPP_SHIFT 8 > +#define MSTATUS_SPP (1UL << MSTATUS_SPP_SHIFT) > +#define MSTATUS_MPP_SHIFT 11 > +#define MSTATUS_MPP (3UL << MSTATUS_MPP_SHIFT) > + > +#define SSTATUS_SIE MSTATUS_SIE > +#define SSTATUS_SPIE_SHIFT MSTATUS_SPIE_SHIFT > +#define SSTATUS_SPIE MSTATUS_SPIE > +#define SSTATUS_SPP_SHIFT MSTATUS_SPP_SHIFT > +#define SSTATUS_SPP MSTATUS_SPP > + > +#define IRQ_S_SOFT 1 > +#define IRQ_VS_SOFT 2 > +#define IRQ_M_SOFT 3 > +#define IRQ_S_TIMER 5 > +#define IRQ_VS_TIMER 6 > +#define IRQ_M_TIMER 7 > +#define IRQ_S_EXT 9 > +#define IRQ_VS_EXT 10 > +#define IRQ_M_EXT 11 > +#define IRQ_S_GEXT 12 > +#define IRQ_PMU_OVF 13 > + > +#define MIP_SSIP (1UL << IRQ_S_SOFT) > +#define MIP_VSSIP (1UL << IRQ_VS_SOFT) > +#define MIP_MSIP (1UL << IRQ_M_SOFT) > +#define MIP_STIP (1UL << IRQ_S_TIMER) > +#define MIP_VSTIP (1UL << IRQ_VS_TIMER) > +#define MIP_MTIP (1UL << IRQ_M_TIMER) > +#define MIP_SEIP (1UL << IRQ_S_EXT) > +#define MIP_VSEIP (1UL << IRQ_VS_EXT) > +#define MIP_MEIP (1UL << IRQ_M_EXT) > +#define MIP_SGEIP (1UL << IRQ_S_GEXT) > +#define MIP_LCOFIP (1UL << IRQ_PMU_OVF) > + > +#define SIP_SSIP MIP_SSIP > +#define SIP_STIP MIP_STIP > + > +#define PRV_U 0UL > +#define PRV_S 1UL > +#define PRV_M 3UL > + > +#define SATP64_MODE 0xF000000000000000ULL > +#define SATP64_ASID 0x0FFFF00000000000ULL > +#define SATP64_PPN 0x00000FFFFFFFFFFFULL > + > +#define SATP_MODE_OFF 0UL > +#define SATP_MODE_SV32 1UL > +#define SATP_MODE_SV39 8UL > +#define SATP_MODE_SV48 9UL > +#define SATP_MODE_SV57 10UL > +#define SATP_MODE_SV64 11UL > + > +#define SATP_MODE SATP64_MODE > + > +/* User Counters/Timers */ > +#define CSR_CYCLE 0xc00 > +#define CSR_TIME 0xc01 > + > +/* Supervisor Trap Setup */ > +#define CSR_SSTATUS 0x100 > +#define CSR_SEDELEG 0x102 > +#define CSR_SIDELEG 0x103 > +#define CSR_SIE 0x104 > +#define CSR_STVEC 0x105 > + > +/* Supervisor Configuration */ > +#define CSR_SENVCFG 0x10a > + > +/* Supervisor Trap Handling */ > +#define CSR_SSCRATCH 0x140 > +#define CSR_SEPC 0x141 > +#define CSR_SCAUSE 0x142 > +#define CSR_STVAL 0x143 > +#define CSR_SIP 0x144 > + > +/* Supervisor Protection and Translation */ > +#define CSR_SATP 0x180 > + > +/* Trap/Exception Causes */ > +#define CAUSE_MISALIGNED_FETCH 0x0 > +#define CAUSE_FETCH_ACCESS 0x1 > +#define CAUSE_ILLEGAL_INSTRUCTION 0x2 > +#define CAUSE_BREAKPOINT 0x3 > +#define CAUSE_MISALIGNED_LOAD 0x4 > +#define CAUSE_LOAD_ACCESS 0x5 > +#define CAUSE_MISALIGNED_STORE 0x6 > +#define CAUSE_STORE_ACCESS 0x7 > +#define CAUSE_USER_ECALL 0x8 > +#define CAUSE_SUPERVISOR_ECALL 0x9 > +#define CAUSE_VIRTUAL_SUPERVISOR_ECALL 0xa > +#define CAUSE_MACHINE_ECALL 0xb > +#define CAUSE_FETCH_PAGE_FAULT 0xc > +#define CAUSE_LOAD_PAGE_FAULT 0xd > +#define CAUSE_STORE_PAGE_FAULT 0xf > +#define CAUSE_FETCH_GUEST_PAGE_FAULT 0x14 > +#define CAUSE_LOAD_GUEST_PAGE_FAULT 0x15 > +#define CAUSE_VIRTUAL_INST_FAULT 0x16 > +#define CAUSE_STORE_GUEST_PAGE_FAULT 0x17 > + > +#endif > diff --git a/MdePkg/Include/Register/RiscV64/RiscVImpl.h b/MdePkg/Include/Register/RiscV64/RiscVImpl.h > new file mode 100644 > index 000000000000..ee5c2ba60377 > --- /dev/null > +++ b/MdePkg/Include/Register/RiscV64/RiscVImpl.h > @@ -0,0 +1,25 @@ > +/** @file > + RISC-V package definitions. > + > + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#ifndef RISCV_IMPL_H_ > +#define RISCV_IMPL_H_ > + > +#include > + > +#define _ASM_FUNC(Name, Section) \ > + .global Name ; \ > + .section #Section, "ax" ; \ > + .type Name, %function ; \ > + .p2align 2 ; \ > + Name: > + > +#define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name) > +#define RISCV_TIMER_COMPARE_BITS 32 > + > +#endif > -- > 2.38.0 > > > > > >