From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp-relay-internal-0.canonical.com (smtp-relay-internal-0.canonical.com [185.125.188.122]) by mx.groups.io with SMTP id smtpd.web10.1056.1672943115569695102 for ; Thu, 05 Jan 2023 10:25:16 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@canonical.com header.s=20210705 header.b=TM0/zzlL; spf=pass (domain: canonical.com, ip: 185.125.188.122, mailfrom: dann.frazier@canonical.com) Received: from mail-il1-f198.google.com (mail-il1-f198.google.com [209.85.166.198]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by smtp-relay-internal-0.canonical.com (Postfix) with ESMTPS id 87743445C6 for ; Thu, 5 Jan 2023 18:25:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=canonical.com; s=20210705; t=1672943112; bh=IVIH5BrL0D0iZCCLm440Nz814ArWVZLxhBVFnJqfK/Q=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:In-Reply-To; b=TM0/zzlLjfnFC2I3Yp5Z88Az1UenH1y7xBwPfQ360aTIKqNABPyJ1l+O9fy62BkTw //KxAmQughj1R0ExaGd8MM2IK+zyqAke6GW4nLKsnEG8bzFQqITnBGnHVkt/ph7bvG eWjncJmbWp51IQ8jhyLzZSArJX0BKEFWDUqUKwNut/dqEKHTy4rH4ZEwu86cQ6C7Ib q+UuICAlX10yhNjhb7vkT2NlaL+7VqW2jORaCkLiqLCo7Pmm4/GrlmOBr3YNb+jWSZ 60eMPrn5M4MvOjLcydWhj6DM/M3/te0SOwf+m+88CxHCPx9GSBiUrColQzIToMHbJ6 yra0Zq+d8Lt4Q== Received: by mail-il1-f198.google.com with SMTP id b13-20020a92c56d000000b0030c4d05f3e4so7255595ilj.6 for ; Thu, 05 Jan 2023 10:25:12 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=IVIH5BrL0D0iZCCLm440Nz814ArWVZLxhBVFnJqfK/Q=; b=7P3jcwbZHG23Kq4XlmK1B3g9Khu0mouI3mY3TMIKlO/GfhjVPQcVd51bWkRJZgrHNZ xhiRnyX78fNkoLmVz0/G1eT/PPsWzqFwLgrZz1Zv0rI0zgO4Mof+ZdIGOMDkiPZnzftZ TfoZ7KykIg7uweJL5EIXv+hWZnZo7pAMjiS1LhK7fhMW9PvEKXEnb0oUj7HQL2sQGqUv 84yqKg1BZ6U/y/Bp7PwVB4fb1QSkFGO6dtUAJUxcSl0iHrAVRbWiIcz8i2JickXS1HTJ /n3LAt2y2g/OwuG3ru7DwfOEAARJZBlkjq/iwHnjn3l+8nkjjRIrdhzCKsiMuVFI/Zdo 4aNA== X-Gm-Message-State: AFqh2koGaygByzHVVwxuhPeOS1HtMoiIXqJQmBkqKG5BcYOBv+w71KJQ Bh9fZ/2ll8eP06/SSn68pUaCHuTqHmo6Cj48sRZPwVwiHONabQBdGFt6jwVrN+1e1Xx4qxcuCW4 MnmW6ZWES0SPSf82fPA2iIzAZzqIgyxQ= X-Received: by 2002:a05:6e02:18cd:b0:30b:fb78:6f0 with SMTP id s13-20020a056e0218cd00b0030bfb7806f0mr37494191ilu.5.1672943111086; Thu, 05 Jan 2023 10:25:11 -0800 (PST) X-Google-Smtp-Source: AMrXdXuCVDCof9tJ3JJ/ZUUi3jjPzWrBsm82EsTJbtq/OXCV008NgoxJ3513wl/6ND5zlTSfSye72Q== X-Received: by 2002:a05:6e02:18cd:b0:30b:fb78:6f0 with SMTP id s13-20020a056e0218cd00b0030bfb7806f0mr37494173ilu.5.1672943110692; Thu, 05 Jan 2023 10:25:10 -0800 (PST) Received: from xps13.dannf ([38.15.56.166]) by smtp.gmail.com with ESMTPSA id b4-20020a92c144000000b00302bcbad239sm11641814ilh.77.2023.01.05.10.25.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Jan 2023 10:25:10 -0800 (PST) Date: Thu, 5 Jan 2023 11:25:08 -0700 From: "dann frazier" To: Ard Biesheuvel Cc: devel@edk2.groups.io Subject: Re: [PATCH] ArmVirtPkg/ArmVirtQemu: Avoid early ID map on ThunderX Message-ID: References: <20230104172255.1211768-1-ardb@kernel.org> MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Thu, Jan 05, 2023 at 12:46:19PM +0100, Ard Biesheuvel wrote: > On Wed, 4 Jan 2023 at 18:23, Ard Biesheuvel wrote: > > > > The early ID map used by ArmVirtQemu uses ASID scoped non-global > > mappings, as this allows us to switch to the permanent ID map seamlessly > > without the need for explicit TLB maintenance. > > > > However, this triggers a known erratum on ThunderX, which does not > > tolerate non-global mappings that are executable at EL1, as this appears > > to result in I-cache corruption. (Linux disables the KPTI based Meltdown > > mitigation on ThunderX for the same reason) > > > > So work around this, by detecting the CPU implementor and part number, > > and proceeding without the early ID map if a ThunderX CPU is detected. > > > > Note that this requires the C code to be built with strict alignment > > again, as we may end up executing it with the MMU and caches off. > > > > Signed-off-by: Ard Biesheuvel > > --- > > ArmVirtPkg/ArmVirtQemu.dsc | 6 ++++++ > > ArmVirtPkg/Library/ArmPlatformLibQemu/AArch64/ArmPlatformHelper.S | 18 ++++++++++++++++++ > > 2 files changed, 24 insertions(+) > > > > diff --git a/ArmVirtPkg/ArmVirtQemu.dsc b/ArmVirtPkg/ArmVirtQemu.dsc > > index f77443229e8e..340b36f69c2c 100644 > > --- a/ArmVirtPkg/ArmVirtQemu.dsc > > +++ b/ArmVirtPkg/ArmVirtQemu.dsc > > @@ -31,6 +31,7 @@ [Defines] > > DEFINE SECURE_BOOT_ENABLE = FALSE > > DEFINE TPM2_ENABLE = FALSE > > DEFINE TPM2_CONFIG_ENABLE = FALSE > > + DEFINE CAVIUM_ERRATUM_27456 = FALSE > > > > # > > # Network definition > > @@ -117,7 +118,12 @@ [LibraryClasses.common.UEFI_DRIVER] > > UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf > > > > [BuildOptions] > > +!if $(CAVIUM_ERRATUM_27456) == TRUE > > + GCC:*_*_AARCH64_CC_XIPFLAGS = -mno-strict-align > > This is wrong - this should be '-mstrict-align' Ah, I wondered :) With that adjustment, the patch works for me on a Cavium ThunderX. Thanks Ard! -dann > > + GCC:*_*_AARCH64_PP_FLAGS = -DCAVIUM_ERRATUM_27456 > > +!else > > GCC:*_*_AARCH64_CC_XIPFLAGS == > > +!endif > > > > !include NetworkPkg/NetworkBuildOptions.dsc.inc > > > > diff --git a/ArmVirtPkg/Library/ArmPlatformLibQemu/AArch64/ArmPlatformHelper.S b/ArmVirtPkg/Library/ArmPlatformLibQemu/AArch64/ArmPlatformHelper.S > > index 05ccc7f9f043..962f1ba3a4d7 100644 > > --- a/ArmVirtPkg/Library/ArmPlatformLibQemu/AArch64/ArmPlatformHelper.S > > +++ b/ArmVirtPkg/Library/ArmPlatformLibQemu/AArch64/ArmPlatformHelper.S > > @@ -44,8 +44,26 @@ > > > > > > ASM_FUNC(ArmPlatformPeiBootAction) > > +#ifdef CAVIUM_ERRATUM_27456 > > + /* > > + * On Cavium ThunderX, using non-global mappings that are executable at EL1 > > + * results in I-cache corruption. So just avoid the early ID mapping there. > > + * > > + * MIDR implementor 0x43 > > + * MIDR part numbers 0xA1 0xA2 > > + */ > > + mrs x0, midr_el1 // read the MIDR into X0 > > + ubfx x1, x0, #6, #10 // grab part number bits [11:2] > > + ubfx x0, x0, #24, #8 // grab implementor id > > + mov x2, #0xA0 >> 2 > > + cmp x0, #0x43 // compare implementor id > > + ccmp x1, x2, #0, eq // compare part# bits [11:2] > > + b.eq .Lreturn > > +#endif > > + > > mrs x0, CurrentEL // check current exception level > > tbz x0, #3, 0f // bail if above EL1 > > +.Lreturn: > > ret > > > > 0:mov_i x0, mairval > >