From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from alexa-out-sd-01.qualcomm.com (alexa-out-sd-01.qualcomm.com [199.106.114.38]) by mx.groups.io with SMTP id smtpd.web09.7840.1648225832451363450 for ; Fri, 25 Mar 2022 09:30:32 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@quicinc.com header.s=qcdkim header.b=txUW2xld; spf=pass (domain: quicinc.com, ip: 199.106.114.38, mailfrom: quic_llindhol@quicinc.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1648225832; x=1679761832; h=date:from:to:cc:subject:message-id:references: mime-version:content-transfer-encoding:in-reply-to; bh=yyf8sVM0qNsNZ5yVqw8qQzxqNh+RTRyFMZ6YlMOLrtU=; b=txUW2xldegGW0/ew9rIPj6zpDQky2Td335Orcr41HjwJoeYk08Yn4ODZ nW1DpMdnPLJ9/n35GbT1hjzsSzNYoJLW2iYnsU2i35AedIL7xLfDFAWGk zWPKac8VrM40tyyMT12Zmq4VGtTQRbZ/QX8RQoPsiQVYS/iTvGhszn7TN k=; Received: from unknown (HELO ironmsg05-sd.qualcomm.com) ([10.53.140.145]) by alexa-out-sd-01.qualcomm.com with ESMTP; 25 Mar 2022 09:30:31 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg05-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Mar 2022 09:30:29 -0700 Received: from qc-i7.hemma.eciton.net (10.80.80.8) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Fri, 25 Mar 2022 09:30:25 -0700 Date: Fri, 25 Mar 2022 16:30:22 +0000 From: "Leif Lindholm" To: , CC: Rebecca Cran , Ard Biesheuvel , Samer El-Haj-Mahmoud , Leif Lindholm , Sami Mujawar , Wenyi Xie , Peng Xie , Ling Jia , Yiqi Shu , Vu Nguyen , Thang Nguyen , Chuong Tran , Pete Batard , Masami Hiramatsu , Graeme Gregory , Radoslaw Biernacki , Marcin Wojtas Subject: Re: [edk2-devel] [PATCH v2 14/17] Silicon/Ampere: Update ArmPlatformLib to work with changed ARM_CORE_INFO Message-ID: References: <20211216220800.9628-1-rebecca@nuviainc.com> <20211216220800.9628-15-rebecca@nuviainc.com> MIME-Version: 1.0 In-Reply-To: Return-Path: quic_llindhol@quicinc.com X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01c.na.qualcomm.com (10.47.97.222) Content-Type: text/plain; charset="iso-8859-1" Content-Disposition: inline Content-Transfer-Encoding: 8bit Hi Nhi, On Sun, Dec 19, 2021 at 10:35:41 +0700, Nhi Pham via groups.io wrote: > Hi Rebecca, > > Leif is merging the rest of Altra port to the edk2-platforms which has SRAT > ACPI table consuming the CPU Core Info table. Therefore, we will need to fix > the SRAT too. I would defer the fix until the Altra port is fully merged. > > On 17/12/2021 05:07, Rebecca Cran wrote: > > The ARM_CORE_INFO struct has been updated so the MPIDR is now a single > > field instead of separate cluster/core fields. Update ArmPlatformLib. > > > > Signed-off-by: Rebecca Cran > > --- > > Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatformLib.c | 5 ++--- > > 1 file changed, 2 insertions(+), 3 deletions(-) > > > > diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatformLib.c b/Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatformLib.c > > index 5b4be0e55516..f2ec923d6f8d 100644 > > --- a/Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatformLib.c > > +++ b/Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatformLib.c > > @@ -108,9 +108,8 @@ PrePeiCoreGetMpCoreInfo ( > > } > > SocketId = SOCKET_ID (Index); > > ClusterId = CLUSTER_ID (Index); > > - mArmPlatformMpCoreInfoTable[mArmPlatformCoreCount].ClusterId = SocketId; > > - mArmPlatformMpCoreInfoTable[mArmPlatformCoreCount].CoreId = > > - (ClusterId << 8) | (Index % PLATFORM_CPU_NUM_CORES_PER_CPM); > > + mArmPlatformMpCoreInfoTable[mArmPlatformCoreCount].Mpidr = GET_MPID ( > > + SocketId, (ClusterId << 8) | (Index % PLATFORM_CPU_NUM_CORES_PER_CPM)); > > For Ampere Altra, the correct MPIDR encoding is SocketId << 32 | ClusterId > << 16 | (Index % PLATFORM_CPU_NUM_CORES_PER_CPM) << 8 > > It would be the same what > Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiMadt.c (not available > yet - being merged in) is describing. This patch already got merged, so if you feel it is wrong, could you submit a fix please? The next patch for me to push from your set otherwise also requires some changes. My naïve attempt would look something like: diff --git a/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiSrat.c b/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiSrat.c index 906b771a250c..d5bc732b08bb 100644 --- a/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiSrat.c +++ b/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiSrat.c @@ -7,6 +7,7 @@ **/ #include +#include #include "AcpiPlatform.h" EFI_ACPI_6_3_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER SRATTableHeaderTemplate = { @@ -119,6 +120,7 @@ SratAddGiccAffinity ( UINTN Count, NumNode, Idx; UINT32 AcpiProcessorUid; UINT8 Socket; + UINT8 Core; UINT8 Cpm; for (Idx = 0; Idx < gST->NumberOfTableEntries; Idx++) { @@ -137,14 +139,14 @@ SratAddGiccAffinity ( NumNode = 0; while (Count != ArmProcessorTable->NumberOfEntries) { for (Idx = 0; Idx < ArmProcessorTable->NumberOfEntries; Idx++ ) { - Socket = ArmCoreInfoTable[Idx].ClusterId; - Cpm = (ArmCoreInfoTable[Idx].CoreId >> PLATFORM_CPM_UID_BIT_OFFSET); + Socket = GET_MPIDR_AFF1 (ArmCoreInfoTable[Idx].Mpidr); + Core = GET_MPIDR_AFF0 (ArmCoreInfoTable[Idx].Mpidr); + Cpm = Core >> PLATFORM_CPM_UID_BIT_OFFSET; if (CpuGetSubNumNode (Socket, Cpm) != NumNode) { /* We add nodes based on ProximityDomain order */ continue; } - AcpiProcessorUid = (ArmCoreInfoTable[Idx].ClusterId << PLATFORM_SOCKET_UID_BIT_OFFSET) + - ArmCoreInfoTable[Idx].CoreId; + AcpiProcessorUid = (Socket << PLATFORM_SOCKET_UID_BIT_OFFSET) + Core; ZeroMem ((VOID *)&SratGiccAffinity[Count], sizeof (SratGiccAffinity[Count])); SratGiccAffinity[Count].AcpiProcessorUid = AcpiProcessorUid; SratGiccAffinity[Count].Flags = 1; Would you be happy for me to fold that into "AmpereAltraPkg, JadePkg: Add ACPI support", or would you be able to submit a v6 of that patch only? Best Regards, Leif