From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pj1-f49.google.com (mail-pj1-f49.google.com [209.85.216.49]) by mx.groups.io with SMTP id smtpd.web10.13558.1678429621283794978 for ; Thu, 09 Mar 2023 22:27:01 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@ventanamicro.com header.s=google header.b=JQHcmlYP; spf=pass (domain: ventanamicro.com, ip: 209.85.216.49, mailfrom: sunilvl@ventanamicro.com) Received: by mail-pj1-f49.google.com with SMTP id ce8-20020a17090aff0800b0023a61cff2c6so7537017pjb.0 for ; Thu, 09 Mar 2023 22:27:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1678429620; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=Ibhqi4X2JpmVOpzyTRkQ/8pMNN/MYqiatL97gP7wSEQ=; b=JQHcmlYPQYk5VDXHzcCr8ywtjj3U1kSSzXluZZfunU77uVabgi6XDTXXfAxegOkX0b q2/sQcCzPp5dLlgBliHp5JPflUnMIDbN8NCkrAPvmfICjYkqesm7IyDiTz+N/QEOmWdM 4WktN93ikaZNdH1QszBvggboowQr7n4UP6tTQJRHBapeV9OUX20r7GNjt6I6mcixHth9 oJlkIIgH24uXO74Xf0fibIbcvUGbLDFKGi/YzcBSz+Ug1nrrblmg+Cp1nmClwNqhUNkF QbcZC09u3EiOmHgPTCcGoL2R/vMiK9I4mtuTJr3H7nGoF9ccPKlyTJXCZ/XIgMhZwmxe 71BQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678429620; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=Ibhqi4X2JpmVOpzyTRkQ/8pMNN/MYqiatL97gP7wSEQ=; b=lv/JnYr4iA8fSX1vUPsXYjOY7/MSnyK4B3o+DKUVllYTWlFw81iam3En2MRdyIYTZX FlLJMug3txUqZHqWAKhrzEI22ebbD+jazWMYalCGl3KGRTk8jryXIb3NOD2lo+lYLMko nmyxcb9y/eWi4PGh64dqGk8dtIi8xUbvU9M1I91Zu42rdYq1xnm6PZya9FzwKckWlCLf 0T9BrXqO1SbYc0wOPaX4djcKR1a3J/ILKq6I0Hslu03HezQZMbLJZ4mN+dL6g9sPFRsy jDVh26V6vtH/AXPTpmXm1Hx8m/7/JYcnysjGeThKiSVaXZ1Kjfoj5f7ic/kt4illHthO VBHw== X-Gm-Message-State: AO0yUKV1WXNzqljz8QmStf/bVinjhWLFFbuoaMh6NWDdxZ7jP4BqNvZx 9drhX+WN8exxDShRKmBgZZljE6goNKUGbQkCXtE= X-Google-Smtp-Source: AK7set/g971gVWze3+2TekIKeyq6DiFXL0n96RZVLwGmOkMtj9ls7FhbQWbfycPH9iahAzR2EMC4IQ== X-Received: by 2002:a17:902:6a83:b0:19e:866c:3547 with SMTP id n3-20020a1709026a8300b0019e866c3547mr20872099plk.65.1678429620601; Thu, 09 Mar 2023 22:27:00 -0800 (PST) Return-Path: Received: from sunil-laptop ([49.206.8.117]) by smtp.gmail.com with ESMTPSA id g7-20020a1709026b4700b001898ee9f723sm637687plt.2.2023.03.09.22.26.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Mar 2023 22:27:00 -0800 (PST) Date: Fri, 10 Mar 2023 11:56:55 +0530 From: "Sunil V L" To: devel@edk2.groups.io, andrei.warkentin@intel.com Cc: Daniel Schaefer Subject: Re: [edk2-devel] [edk2 3/3] OvmfPkg: RiscVVirt: Add missing SerialPortInitialize to Sec Message-ID: References: <20230303180410.6344-1-andrei.warkentin@intel.com> <20230303180410.6344-4-andrei.warkentin@intel.com> MIME-Version: 1.0 In-Reply-To: <20230303180410.6344-4-andrei.warkentin@intel.com> Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Fri, Mar 03, 2023 at 12:04:10PM -0600, Andrei Warkentin wrote: > If the SerialPortLib had any initialization needed, this > would be skipped in the RiscVVirt Sec. Follow the example > seen elsewhere (ArmVirtPkg PrePi). > > Seen with BaseSerialPortLibRiscVSbi not using DBCN in Sec, yet > using DBCN elsewhere. > > Cc: Daniel Schaefer > Cc: Sunil V L > Signed-off-by: Andrei Warkentin > --- > OvmfPkg/RiscVVirt/Sec/SecMain.inf | 1 + > OvmfPkg/RiscVVirt/Sec/SecMain.h | 1 + > OvmfPkg/RiscVVirt/Sec/SecMain.c | 4 +++- > 3 files changed, 5 insertions(+), 1 deletion(-) > > diff --git a/OvmfPkg/RiscVVirt/Sec/SecMain.inf b/OvmfPkg/RiscVVirt/Sec/SecMain.inf > index aed35d3af596..0e2a5785e8a4 100644 > --- a/OvmfPkg/RiscVVirt/Sec/SecMain.inf > +++ b/OvmfPkg/RiscVVirt/Sec/SecMain.inf > @@ -48,6 +48,7 @@ [LibraryClasses] > FdtLib > MemoryAllocationLib > HobLib > + SerialPortLib > > [Ppis] > gEfiTemporaryRamSupportPpiGuid # PPI ALWAYS_PRODUCED > diff --git a/OvmfPkg/RiscVVirt/Sec/SecMain.h b/OvmfPkg/RiscVVirt/Sec/SecMain.h > index 83a8058efe40..7c7650f0d298 100644 > --- a/OvmfPkg/RiscVVirt/Sec/SecMain.h > +++ b/OvmfPkg/RiscVVirt/Sec/SecMain.h > @@ -29,6 +29,7 @@ > #include > #include > #include > +#include > #include > > /** > diff --git a/OvmfPkg/RiscVVirt/Sec/SecMain.c b/OvmfPkg/RiscVVirt/Sec/SecMain.c > index adf73f2eb66c..db309ebdf1a3 100644 > --- a/OvmfPkg/RiscVVirt/Sec/SecMain.c > +++ b/OvmfPkg/RiscVVirt/Sec/SecMain.c > @@ -1,7 +1,7 @@ > /** @file > RISC-V SEC phase module for Qemu Virt. > > - Copyright (c) 2008 - 2015, Intel Corporation. All rights reserved.
> + Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.
Should be 2008 - 2023 Otherwise, LGTM. Reviewed-by: Sunil V L