From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by mx.groups.io with SMTP id smtpd.web11.23387.1679068529312869636 for ; Fri, 17 Mar 2023 08:55:29 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=oG9jZmFA; spf=permerror, err=parse error for token &{10 18 %{ir}.%{v}.%{d}.spf.has.pphosted.com}: invalid domain name (domain: quicinc.com, ip: 205.220.180.131, mailfrom: quic_llindhol@quicinc.com) Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 32H7Z0wD016424; Fri, 17 Mar 2023 15:55:26 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=date : from : to : cc : subject : message-id : references : mime-version : content-type : in-reply-to; s=qcppdkim1; bh=8SU8SgSSHi1oG19Eg3N4GnAuz9jp6C8EHAoR//09XUo=; b=oG9jZmFAXXdfJJS7EqHOuFcY50Ah8SQxNRcl2enz56oZFaCjlQs+xLUkQMenuY8mRZEJ qIB6pRFuELsOLCQjAK04cYSSKq4MFuQJCycVY/9UFA1TTbbVX++c4hwtA7j7lv/01VpP vWtbYpK4e1mTkAIzSVH/0dWna/37t3XAKBivho+JetvphaO6j8by43EHajn6MwSQiaRz xDg7ltKWdJ29RR4KtRAytUNZBAa+/F9C3M9EH7D1K/4KUAkqye+SQSeVsPbZ6I9Xc62D eFIy8NaOPQdQmL5PeXEuWDZm7/pK0vaTMXSP8tnfXOo5tbRHPUXoDRhF+FgmcLLwWNfn Zw== Received: from nasanppmta02.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3pce6njedf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 17 Mar 2023 15:55:25 +0000 Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 32HFtOIo020930 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 17 Mar 2023 15:55:24 GMT Received: from qc-i7.hemma.eciton.net (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Fri, 17 Mar 2023 08:55:22 -0700 Date: Fri, 17 Mar 2023 15:55:19 +0000 From: "Leif Lindholm" To: , CC: Ard Biesheuvel , Abner Chang , Michael D Kinney Subject: Re: [edk2-devel] [PATCH v2 RESEND 2/4] Platform/AMD/PlatformPkg: Adds PciHotPlug init protocol implementation Message-ID: References: <3eb1b035c0ffc64045065beae4c0adebf88a38cf.1679035605.git.abdattar@amd.com> MIME-Version: 1.0 In-Reply-To: <3eb1b035c0ffc64045065beae4c0adebf88a38cf.1679035605.git.abdattar@amd.com> X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: aKgexgmYLpcddCecm9u8PC-NhBwMgO6Q X-Proofpoint-GUID: aKgexgmYLpcddCecm9u8PC-NhBwMgO6Q X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-17_10,2023-03-16_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 adultscore=0 priorityscore=1501 spamscore=0 mlxlogscore=999 malwarescore=0 suspectscore=0 bulkscore=0 phishscore=0 impostorscore=0 clxscore=1015 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303150002 definitions=main-2303170106 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline On Fri, Mar 17, 2023 at 12:20:05 +0530, Abdul Lateef Attar via groups.io wrote: > Adds PCI hotplug init protocol implementation. What are some notable aspects of this initial implementation? What groups of platforms is it intended to cover? > Signed-off-by: Abdul Lateef Attar > Cc: Ard Biesheuvel > Cc: Leif Lindholm > Cc: Abner Chang > Cc: Michael D Kinney > --- > Platform/AMD/PlatformPkg/PlatformPkg.dec | 16 + > Platform/AMD/PlatformPkg/PlatformPkg.dsc | 23 ++ > .../PlatformPkg/PciHotPlug/PciHotPlugInit.inf | 41 +++ > .../PlatformPkg/PciHotPlug/PciHotPlugInit.c | 340 ++++++++++++++++++ > 4 files changed, 420 insertions(+) > create mode 100644 Platform/AMD/PlatformPkg/PciHotPlug/PciHotPlugInit.inf > create mode 100644 Platform/AMD/PlatformPkg/PciHotPlug/PciHotPlugInit.c > > diff --git a/Platform/AMD/PlatformPkg/PlatformPkg.dec b/Platform/AMD/PlatformPkg/PlatformPkg.dec > index 6155860979cb..1bc38d6025c3 100644 > --- a/Platform/AMD/PlatformPkg/PlatformPkg.dec > +++ b/Platform/AMD/PlatformPkg/PlatformPkg.dec > @@ -13,3 +13,19 @@ [Defines] > PACKAGE_NAME = PlatformPkg > PACKAGE_GUID = 38FBA311-E2AA-4620-9A90-9A23753D1878 > PACKAGE_VERSION = 0.1 > + > +[Guids] > + gPlatformPkgTokenSpaceGuid = { 0x95ECA58D, 0x09B6, 0x4420, { 0xB4, 0xE7, 0x01, 0x7F, 0x6A, 0x5B, 0x26, 0x0F }} > + > +[PcdsDynamic, PcdsDynamicEx] > + # > + # PCI HotPlug Resource Padding > + # > + # IO Resource padding in bytes, default 4KB > + gPlatformPkgTokenSpaceGuid.PcdPciHotPlugResourcePadIO|0x00001000|UINT64|0x10000000 > + # PreFetch Memory padding in bytes, default 2MB > + gPlatformPkgTokenSpaceGuid.PcdPciHotPlugResourcePadPMem|0x00200000|UINT64|0x10000001 > + # Non-PreFetch Memory padding in bytes, default 1MB > + gPlatformPkgTokenSpaceGuid.PcdPciHotPlugResourcePadMem|0x00100000|UINT64|0x10000002 > + # PCI bus padding, number of bus to reserve, default 2 bus > + gPlatformPkgTokenSpaceGuid.PcdPciHotPlugResourcePadBus|2|UINT8|0x10000003 > diff --git a/Platform/AMD/PlatformPkg/PlatformPkg.dsc b/Platform/AMD/PlatformPkg/PlatformPkg.dsc > index 704566b9ea73..9a693070ab3f 100644 > --- a/Platform/AMD/PlatformPkg/PlatformPkg.dsc > +++ b/Platform/AMD/PlatformPkg/PlatformPkg.dsc > @@ -16,5 +16,28 @@ [Defines] > BUILD_TARGETS = DEBUG | RELEASE | NOOPT > SUPPORTED_ARCHITECTURES = IA32 | X64 > > + Please don't add spurious whitespaces. > [Packages] > PlatformPkg/PlatformPkg.dec > + MdeModulePkg/MdeModulePkg.dec > + MdePkg/MdePkg.dec I won't be maintaining this code, but I generally advocate sorting these types of enumerations alphabetically in order to speed up reading. (That's not really possible for the block below.) > + > +[LibraryClasses.Common] > + UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf > + UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf > + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf > + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf > + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf > + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf > + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf > + RegisterFilterLib|MdePkg/Library/RegisterFilterLibNull/RegisterFilterLibNull.inf > + SerialPortLib|MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf > + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf > + DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf > + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf > + PlatformHookLib|MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf > + PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf > + PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf > + > +[Components.X64] > + PlatformPkg/PciHotPlug/PciHotPlugInit.inf > diff --git a/Platform/AMD/PlatformPkg/PciHotPlug/PciHotPlugInit.inf b/Platform/AMD/PlatformPkg/PciHotPlug/PciHotPlugInit.inf > new file mode 100644 > index 000000000000..0079c4acf14e > --- /dev/null > +++ b/Platform/AMD/PlatformPkg/PciHotPlug/PciHotPlugInit.inf > @@ -0,0 +1,41 @@ > +## @file > +# This driver implements EFI_PCI_HOT_PLUG_INIT_PROTOCOL. > +# Adds resource padding information, for PCIe hotplug purposes. > +# > +# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +## > + > +[Defines] > + INF_VERSION = 1.29 > + BASE_NAME = PciHotPlugInit > + FILE_GUID = 8B67D95F-78B7-484F-8F16-5F22AB388B0C > + MODULE_TYPE = DXE_DRIVER > + VERSION_STRING = 0.1 > + ENTRY_POINT = PciHotPlugInitialize > + > +[Sources] > + PciHotPlugInit.c > + > +[Packages] > + MdeModulePkg/MdeModulePkg.dec > + MdePkg/MdePkg.dec > + PlatformPkg/PlatformPkg.dec But these would benefit from sorting > + > +[LibraryClasses] > + UefiDriverEntryPoint > + UefiBootServicesTableLib > + DebugLib > + MemoryAllocationLib And these > + > +[Protocols] > + gEfiPciHotPlugInitProtocolGuid > + > +[Pcd] > + gPlatformPkgTokenSpaceGuid.PcdPciHotPlugResourcePadIO > + gPlatformPkgTokenSpaceGuid.PcdPciHotPlugResourcePadPMem > + gPlatformPkgTokenSpaceGuid.PcdPciHotPlugResourcePadMem > + gPlatformPkgTokenSpaceGuid.PcdPciHotPlugResourcePadBus > + > +[Depex] > + TRUE > diff --git a/Platform/AMD/PlatformPkg/PciHotPlug/PciHotPlugInit.c b/Platform/AMD/PlatformPkg/PciHotPlug/PciHotPlugInit.c > new file mode 100644 > index 000000000000..b977406bbcae > --- /dev/null > +++ b/Platform/AMD/PlatformPkg/PciHotPlug/PciHotPlugInit.c > @@ -0,0 +1,340 @@ > +/** @file > + This file declares EFI PCI Hot Plug Init Protocol. > + > + This protocol provides the necessary functionality to initialize the Hot Plug > + Controllers (HPCs) and the buses that they control. This protocol also provides > + information regarding resource padding. > + > + @par Note: > + This source has the reference of OVMF PciHotPluginit.c and Intel platform PciHotPlug.c. > + > + This protocol is required only on platforms that support one or more PCI Hot > + Plug* slots or CardBus sockets. > + > + The EFI_PCI_HOT_PLUG_INIT_PROTOCOL provides a mechanism for the PCI bus enumerator > + to properly initialize the HPCs and CardBus sockets that require initialization. > + The HPC initialization takes place before the PCI enumeration process is complete. > + There cannot be more than one instance of this protocol in a system. This protocol > + is installed on its own separate handle. > + > + Because the system may include multiple HPCs, one instance of this protocol > + should represent all of them. The protocol functions use the device path of > + the HPC to identify the HPC. When the PCI bus enumerator finds a root HPC, it > + will call EFI_PCI_HOT_PLUG_INIT_PROTOCOL.InitializeRootHpc(). If InitializeRootHpc() > + is unable to initialize a root HPC, the PCI enumerator will ignore that root HPC > + and continue the enumeration process. If the HPC is not initialized, the devices > + that it controls may not be initialized, and no resource padding will be provided. > + > + From the standpoint of the PCI bus enumerator, HPCs are divided into the following > + two classes: > + > + - Root HPC: > + These HPCs must be initialized by calling InitializeRootHpc() during the > + enumeration process. These HPCs will also require resource padding. The > + platform code must have a priori knowledge of these devices and must know > + how to initialize them. There may not be any way to access their PCI > + configuration space before the PCI enumerator programs all the upstream > + bridges and thus enables the path to these devices. The PCI bus enumerator > + is responsible for determining the PCI bus address of the HPC before it > + calls InitializeRootHpc(). > + - Nonroot HPC: > + These HPCs will not need explicit initialization during enumeration process. > + These HPCs will require resource padding. The platform code does not have > + to have a priori knowledge of these devices. > + > + Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
> + Copyright (C) 2016, Red Hat, Inc.
> + Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > + > + @par Revision Reference: > + This Protocol is defined in UEFI Platform Initialization Specification 1.2 I know you say above that this is based on existing code, but 1.2 is ancient. Latest version is 1.7 - is there anything missing from being compliant with that version? > + Volume 5: Standards > + > +**/ > + > +#include > +#include > +#include > +#include > +#include I (personally) also like to sort include files within each Uefi/Library/Protocol group alphabetically. / Leif > +#include > + > +// > +// The protocol interface this driver produces. > +// > +STATIC EFI_PCI_HOT_PLUG_INIT_PROTOCOL mPciHotPlugInit; > + > +/** > + Returns a list of root Hot Plug Controllers (HPCs) that require initialization > + during the boot process. > + > + This procedure returns a list of root HPCs. The PCI bus driver must initialize > + these controllers during the boot process. The PCI bus driver may or may not be > + able to detect these HPCs. If the platform includes a PCI-to-CardBus bridge, it > + can be included in this list if it requires initialization. The HpcList must be > + self consistent. An HPC cannot control any of its parent buses. Only one HPC can > + control a PCI bus. Because this list includes only root HPCs, no HPC in the list > + can be a child of another HPC. This policy must be enforced by the > + EFI_PCI_HOT_PLUG_INIT_PROTOCOL. The PCI bus driver may not check for such > + invalid conditions. The callee allocates the buffer HpcList > + > + @param[in] This Pointer to the EFI_PCI_HOT_PLUG_INIT_PROTOCOL instance. > + @param[out] HpcCount The number of root HPCs that were returned. > + @param[out] HpcList The list of root HPCs. HpcCount defines the number of > + elements in this list. > + > + @retval EFI_SUCCESS HpcList was returned. > + @retval EFI_OUT_OF_RESOURCES HpcList was not returned due to insufficient > + resources. > + @retval EFI_INVALID_PARAMETER HpcCount is NULL or HpcList is NULL. > + > +**/ > +EFI_STATUS > +EFIAPI > +GetRootHpcList ( > + IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This, > + OUT UINTN *HpcCount, > + OUT EFI_HPC_LOCATION **HpcList > + ) > +{ > + if ((HpcCount == NULL) || (HpcList == NULL)) { > + return EFI_INVALID_PARAMETER; > + } > + > + // > + // Platform BIOS not doing any extra/special HPC initialization > + // Hence returning the HpcCount as zero and HpcList as NULL > + // > + *HpcCount = 0; > + *HpcList = NULL; > + > + return EFI_SUCCESS; > +} > + > +/** > + Initializes one root Hot Plug Controller (HPC). This process may causes > + initialization of its subordinate buses. > + > + This function initializes the specified HPC. At the end of initialization, > + the hot-plug slots or sockets (controlled by this HPC) are powered and are > + connected to the bus. All the necessary registers in the HPC are set up. For > + a Standard (PCI) Hot Plug Controller (SHPC), the registers that must be set > + up are defined in the PCI Standard Hot Plug Controller and Subsystem > + Specification. > + > + @param[in] This Pointer to the EFI_PCI_HOT_PLUG_INIT_PROTOCOL instance. > + @param[in] HpcDevicePath The device path to the HPC that is being initialized. > + @param[in] HpcPciAddress The address of the HPC function on the PCI bus. > + @param[in] Event The event that should be signaled when the HPC > + initialization is complete. Set to NULL if the > + caller wants to wait until the entire initialization > + process is complete. > + @param[out] HpcState The state of the HPC hardware. The state is > + EFI_HPC_STATE_INITIALIZED or EFI_HPC_STATE_ENABLED. > + > + @retval EFI_SUCCESS If Event is NULL, the specific HPC was successfully > + initialized. If Event is not NULL, Event will be > + signaled at a later time when initialization is complete. > + @retval EFI_UNSUPPORTED This instance of EFI_PCI_HOT_PLUG_INIT_PROTOCOL > + does not support the specified HPC. > + @retval EFI_OUT_OF_RESOURCES Initialization failed due to insufficient > + resources. > + @retval EFI_INVALID_PARAMETER HpcState is NULL. > + > +**/ > +EFI_STATUS > +EFIAPI > +InitializeRootHpc ( > + IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This, > + IN EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath, > + IN UINT64 HpcPciAddress, > + IN EFI_EVENT Event, OPTIONAL > + OUT EFI_HPC_STATE *HpcState > + ) > +{ > + if (HpcState == NULL) { > + return EFI_INVALID_PARAMETER; > + } > + > + // > + // This Platform doesnt have any non-enumerated HPC. > + // Hence no extra initialization required from Platform BIOS. > + // > + return EFI_UNSUPPORTED; > +} > + > +/** > + Returns the resource padding that is required by the PCI bus that is controlled > + by the specified Hot Plug Controller (HPC). > + > + This function returns the resource padding that is required by the PCI bus that > + is controlled by the specified HPC. This member function is called for all the > + root HPCs and nonroot HPCs that are detected by the PCI bus enumerator. This > + function will be called before PCI resource allocation is completed. This function > + must be called after all the root HPCs, with the possible exception of a > + PCI-to-CardBus bridge, have completed initialization. > + > + @param[in] This Pointer to the EFI_PCI_HOT_PLUG_INIT_PROTOCOL instance. > + @param[in] HpcDevicePath The device path to the HPC. > + @param[in] HpcPciAddress The address of the HPC function on the PCI bus. > + @param[out] HpcState The state of the HPC hardware. > + @param[out] Padding The amount of resource padding that is required by the > + PCI bus under the control of the specified HPC. > + @param[out] Attributes Describes how padding is accounted for. The padding > + is returned in the form of ACPI 2.0 resource descriptors. > + > + @retval EFI_SUCCESS The resource padding was successfully returned. > + @retval EFI_UNSUPPORTED This instance of the EFI_PCI_HOT_PLUG_INIT_PROTOCOL > + does not support the specified HPC. > + @retval EFI_NOT_READY This function was called before HPC initialization > + is complete. > + @retval EFI_INVALID_PARAMETER HpcState or Padding or Attributes is NULL. > + @retval EFI_OUT_OF_RESOURCES ACPI 2.0 resource descriptors for Padding > + cannot be allocated due to insufficient resources. > + > +**/ > +EFI_STATUS > +EFIAPI > +GetResourcePadding ( > + IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This, > + IN EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath, > + IN UINT64 HpcPciAddress, > + OUT EFI_HPC_STATE *HpcState, > + OUT VOID **Padding, > + OUT EFI_HPC_PADDING_ATTRIBUTES *Attributes > + ) > +{ > + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *PaddingResource; > + > + // > + // Need total 5 resources > + // 1 - IO resource > + // 2 - Mem resource > + // 3 - PMem resource > + // 4 - Bus resource > + // 5 - end tag resource > + PaddingResource = AllocateZeroPool (4 * sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)); > + if (PaddingResource == NULL) { > + return EFI_OUT_OF_RESOURCES; > + } > + > + *Padding = (VOID *)PaddingResource; > + > + // > + // Padding for bus > + // > + *Attributes = EfiPaddingPciBus; > + > + PaddingResource->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR; > + PaddingResource->Len = (UINT16)( > + sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - > + OFFSET_OF ( > + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR, > + ResType > + ) > + ); > + PaddingResource->ResType = ACPI_ADDRESS_SPACE_TYPE_BUS; > + PaddingResource->GenFlag = 0x0; > + PaddingResource->SpecificFlag = 0; > + PaddingResource->AddrRangeMin = 0; > + PaddingResource->AddrRangeMax = 0; > + PaddingResource->AddrLen = PcdGet8 (PcdPciHotPlugResourcePadBus); > + > + // > + // Padding for non-prefetchable memory > + // > + PaddingResource++; > + PaddingResource->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR; > + PaddingResource->Len = (UINT16)( > + sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - > + OFFSET_OF ( > + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR, > + ResType > + ) > + ); > + PaddingResource->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM; > + PaddingResource->GenFlag = 0x0; > + PaddingResource->AddrSpaceGranularity = 32; > + PaddingResource->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_NON_CACHEABLE; > + PaddingResource->AddrRangeMin = 0; > + PaddingResource->AddrLen = PcdGet64 (PcdPciHotPlugResourcePadMem); > + PaddingResource->AddrRangeMax = PaddingResource->AddrLen - 1; > + > + // > + // Padding for prefetchable memory > + // > + PaddingResource++; > + PaddingResource->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR; > + PaddingResource->Len = (UINT16)( > + sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - > + OFFSET_OF ( > + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR, > + ResType > + ) > + ); > + PaddingResource->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM; > + PaddingResource->GenFlag = 0x0; > + PaddingResource->AddrSpaceGranularity = 32; > + PaddingResource->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE; > + PaddingResource->AddrLen = PcdGet64 (PcdPciHotPlugResourcePadPMem); > + PaddingResource->AddrRangeMax = PaddingResource->AddrLen - 1; > + > + // > + // Padding for I/O > + // > + PaddingResource++; > + PaddingResource->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR; > + PaddingResource->Len = (UINT16)( > + sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - > + OFFSET_OF ( > + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR, > + ResType > + ) > + ); > + PaddingResource->ResType = ACPI_ADDRESS_SPACE_TYPE_IO; > + PaddingResource->GenFlag = 0x0; > + PaddingResource->SpecificFlag = 0; > + PaddingResource->AddrRangeMin = 0; > + PaddingResource->AddrLen = PcdGet64 (PcdPciHotPlugResourcePadIO); > + PaddingResource->AddrRangeMax = PaddingResource->AddrLen - 1; > + > + // > + // Terminate the entries. > + // > + PaddingResource++; > + ((EFI_ACPI_END_TAG_DESCRIPTOR *)PaddingResource)->Desc = ACPI_END_TAG_DESCRIPTOR; > + ((EFI_ACPI_END_TAG_DESCRIPTOR *)PaddingResource)->Checksum = 0x0; > + > + *HpcState = EFI_HPC_STATE_INITIALIZED | EFI_HPC_STATE_ENABLED; > + > + return EFI_SUCCESS; > +} > + > +/** > + Entry point for this driver. > + > + @param[in] ImageHandle Image handle of this driver. > + @param[in] SystemTable Pointer to SystemTable. > + > + @retval EFI_SUCESS Driver has loaded successfully. > + @return Error codes from lower level functions. > + > +**/ > +EFI_STATUS > +EFIAPI > +PciHotPlugInitialize ( > + IN EFI_HANDLE ImageHandle, > + IN EFI_SYSTEM_TABLE *SystemTable > + ) > +{ > + mPciHotPlugInit.GetRootHpcList = GetRootHpcList; > + mPciHotPlugInit.InitializeRootHpc = InitializeRootHpc; > + mPciHotPlugInit.GetResourcePadding = GetResourcePadding; > + return gBS->InstallMultipleProtocolInterfaces ( > + &ImageHandle, > + &gEfiPciHotPlugInitProtocolGuid, > + &mPciHotPlugInit, > + NULL > + ); > +} > -- > 2.25.1 > > > > > >