From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by mx.groups.io with SMTP id smtpd.web10.23581.1679068789722327741 for ; Fri, 17 Mar 2023 08:59:49 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=KNf5ykmO; spf=permerror, err=parse error for token &{10 18 %{ir}.%{v}.%{d}.spf.has.pphosted.com}: invalid domain name (domain: quicinc.com, ip: 205.220.168.131, mailfrom: quic_llindhol@quicinc.com) Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 32HEPRoo027492; Fri, 17 Mar 2023 15:59:48 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=date : from : to : cc : subject : message-id : references : mime-version : content-type : in-reply-to; s=qcppdkim1; bh=mR15zjKc01eb+PH5B5pZWNiR/V1Ksc0WOVCA81VDAdM=; b=KNf5ykmOBTpTFimceImSjRM5Tul1xlFBB4zfac8mEd3QsYQrCqqGJGuFdhwC7z2RkuUD DbiPX9ic5VBvkORx1oS/UrFDKIn2R7D3OpOojKYnuDjLFN8kBFbcO7J2zLsfVcSWAm7S omAZd46OC9kNFVDnUGalyywbQG6bJ1Hlb5vjq47Qheo6pbx7u7FJCLHziT4JQq3rpIHz DhL0PbgnqnRVGUDRE5BPf3MFpGwysn47HhUcWgrDzkdCap/WXttw829+D54iEz3HpF0A wuyNLqt7ia5zGiOyVR2GoCa0hP0saxFDNS/es8JH0gKwgYip6/WNrSxLpl39ZrjQxnLB pg== Received: from nasanppmta04.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3pckcfstrf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 17 Mar 2023 15:59:48 +0000 Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 32HFxlgo010570 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 17 Mar 2023 15:59:47 GMT Received: from qc-i7.hemma.eciton.net (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Fri, 17 Mar 2023 08:59:46 -0700 Date: Fri, 17 Mar 2023 15:59:43 +0000 From: "Leif Lindholm" To: Abdul Lateef Attar CC: , Ard Biesheuvel , Abner Chang , Michael D Kinney Subject: Re: [PATCH v2 RESEND 3/4] Platform/AMD/BoarkPkg: Adds SetCacheMtrrLib library Message-ID: References: <60ddb8be3b32bc6ff9745a51eef1f857c428a0f4.1679035605.git.abdattar@amd.com> MIME-Version: 1.0 In-Reply-To: <60ddb8be3b32bc6ff9745a51eef1f857c428a0f4.1679035605.git.abdattar@amd.com> X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: UfvGj7j5pWnpLnH210hyAhYhCVj8q4m6 X-Proofpoint-GUID: UfvGj7j5pWnpLnH210hyAhYhCVj8q4m6 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-17_10,2023-03-16_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 mlxlogscore=865 lowpriorityscore=0 phishscore=0 priorityscore=1501 bulkscore=0 mlxscore=0 clxscore=1015 spamscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303150002 definitions=main-2303170107 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline Typo in subject: BoarkPkg On Fri, Mar 17, 2023 at 12:20:06 +0530, Abdul Lateef Attar wrote: > Adds SetCacheMtrrLib library for AMD processor based boards. > This library sets MTRR value or various memory ranges. > > Signed-off-by: Abdul Lateef Attar > Cc: Ard Biesheuvel > Cc: Leif Lindholm > Cc: Abner Chang > Cc: Michael D Kinney > --- > Platform/AMD/BoardPkg/BoardPkg.dsc | 10 ++ > .../SetCacheMtrrLib/SetCacheMtrrLib.inf | 37 +++++ > .../Library/SetCacheMtrrLib/SetCacheMtrrLib.c | 132 ++++++++++++++++++ > 3 files changed, 179 insertions(+) > create mode 100644 Platform/AMD/BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf > create mode 100644 Platform/AMD/BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.c > > diff --git a/Platform/AMD/BoardPkg/BoardPkg.dsc b/Platform/AMD/BoardPkg/BoardPkg.dsc > index cb4065b86c60..aa0ee8287cd8 100644 > --- a/Platform/AMD/BoardPkg/BoardPkg.dsc > +++ b/Platform/AMD/BoardPkg/BoardPkg.dsc > @@ -18,3 +18,13 @@ [Defines] > > [Packages] > BoardPkg/BoardPkg.dec > + MinPlatformPkg/MinPlatformPkg.dec > + MdePkg/MdePkg.dec Sort? > + UefiCpuPkg/UefiCpuPkg.dec > + > +[LibraryClasses.common.PEIM] > + SetCacheMtrrLib|BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf > + > +[Components.IA32] > + BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf > + Please drop blank line at end of file. > diff --git a/Platform/AMD/BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf b/Platform/AMD/BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf > new file mode 100644 > index 000000000000..c66661d3f8dc > --- /dev/null > +++ b/Platform/AMD/BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf > @@ -0,0 +1,37 @@ > +## @file > +# Component information file for Platform SetCacheMtrr Library. > +# This library implementation is for AMD processor based platforms. > +# > +# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
> +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +## > + > +[Defines] > + INF_VERSION = 1.29 > + BASE_NAME = PeiSetCacheMtrrLib > + FILE_GUID = 1E8468E0-5EB4-4088-9B52-BFDC6E4DAE87 > + MODULE_TYPE = PEIM > + VERSION_STRING = 1.0 > + LIBRARY_CLASS = SetCacheMtrrLib > + > +[LibraryClasses] > + BaseLib > + DebugLib > + MtrrLib > + > +[Packages] > + MinPlatformPkg/MinPlatformPkg.dec > + MdePkg/MdePkg.dec Sort? > + UefiCpuPkg/UefiCpuPkg.dec > + > +[Sources] > + SetCacheMtrrLib.c > + > +[Guids] > + > +[Pcd] > + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress > + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize > + Please drop blank line at end of file. / Leif > diff --git a/Platform/AMD/BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.c b/Platform/AMD/BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.c > new file mode 100644 > index 000000000000..18404405d9fa > --- /dev/null > +++ b/Platform/AMD/BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.c > @@ -0,0 +1,132 @@ > +/** @file > + > +SetCacheMtrr library functions. > +This library implementation is for AMD processor based platforms. > + > +Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
> + > +SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#include > +#include > +#include > +#include > + > +/** > + This function sets the cache MTRR values for PEI phase. > +**/ > +VOID > +EFIAPI > +SetCacheMtrr ( > + VOID > + ) > +{ > + EFI_STATUS Status; > + > + Status = MtrrSetMemoryAttribute ( > + 0, > + 0xA0000, > + CacheWriteBack > + ); > + if (EFI_ERROR (Status)) { > + DEBUG (( > + DEBUG_ERROR, > + "Error(%r) in setting CacheWriteBack for 0-0x9FFFF\n", > + Status > + )); > + } > + > + Status = MtrrSetMemoryAttribute ( > + 0xA0000, > + 0x20000, > + CacheUncacheable > + ); > + if (EFI_ERROR (Status)) { > + DEBUG (( > + DEBUG_ERROR, > + "Error(%r) in setting CacheUncacheable for 0xA0000-0xBFFFF\n", > + Status > + )); > + } > + > + Status = MtrrSetMemoryAttribute ( > + 0xC0000, > + 0x40000, > + CacheWriteProtected > + ); > + if (EFI_ERROR (Status)) { > + DEBUG (( > + DEBUG_ERROR, > + "Error(%r) in setting CacheWriteProtected for 0xC0000-0xFFFFF\n", > + Status > + )); > + } > + > + Status = MtrrSetMemoryAttribute ( > + 0x100000, > + 0xAFF00000, > + CacheWriteBack > + ); > + if (EFI_ERROR (Status)) { > + DEBUG (( > + DEBUG_ERROR, > + "Error(%r) in setting CacheWriteBack for 0x100000-0xAFFFFFFF\n", > + Status > + )); > + } > + > + Status = MtrrSetMemoryAttribute ( > + PcdGet32 (PcdFlashAreaBaseAddress), > + PcdGet32 (PcdFlashAreaSize), > + CacheWriteProtected > + ); > + if (EFI_ERROR (Status)) { > + DEBUG (( > + DEBUG_ERROR, > + "Error(%r) in setting CacheWriteProtected for 0x%X-0x%X\n", > + Status, > + PcdGet32 (PcdFlashAreaBaseAddress), > + PcdGet32 (PcdFlashAreaBaseAddress) + PcdGet32 (PcdFlashAreaSize) > + )); > + } > + > + MtrrDebugPrintAllMtrrs (); > + return; > +} > + > +/** > + Update MTRR setting in EndOfPei phase. > + This function will set the MTRR value as CacheUncacheable > + for Flash address. > + > + @retval EFI_SUCCESS The function completes successfully. > + @retval Others Some error occurs. > +**/ > +EFI_STATUS > +EFIAPI > +SetCacheMtrrAfterEndOfPei ( > + VOID > + ) > +{ > + EFI_STATUS Status; > + > + Status = MtrrSetMemoryAttribute ( > + PcdGet32 (PcdFlashAreaBaseAddress), > + PcdGet32 (PcdFlashAreaSize), > + CacheUncacheable > + ); > + if (EFI_ERROR (Status)) { > + DEBUG (( > + DEBUG_ERROR, > + "Error(%r) in setting CacheUncacheable for 0x%X-0x%X\n", > + Status, > + PcdGet32 (PcdFlashAreaBaseAddress), > + PcdGet32 (PcdFlashAreaBaseAddress) + PcdGet32 (PcdFlashAreaSize) > + )); > + } > + > + MtrrDebugPrintAllMtrrs (); > + return EFI_SUCCESS; > +} > -- > 2.25.1 >