From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by mx.groups.io with SMTP id smtpd.web11.33892.1679921120611563718 for ; Mon, 27 Mar 2023 05:45:20 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=L06rG8gF; spf=permerror, err=parse error for token &{10 18 %{ir}.%{v}.%{d}.spf.has.pphosted.com}: invalid domain name (domain: quicinc.com, ip: 205.220.180.131, mailfrom: quic_llindhol@quicinc.com) Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 32RAOHVO029850; Mon, 27 Mar 2023 12:45:10 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=date : from : to : cc : subject : message-id : references : mime-version : content-type : in-reply-to; s=qcppdkim1; bh=Gec7HnkH9i+B2CgNCkWQm873D4964LSsIGXu1DVPgvY=; b=L06rG8gFX7W1hZW1ZHEoiGYBvy21QJXE/XYQzDDVUxPyqedw+reEVw4mm5yY1ICAfnYI T/Tk3RYyJpB1LiuiCtfRdaTyoMgULYmBBNVzHKaXF3OE9oUjiO4Wl1ccx9XhC05eyZuR FAqdK1xqzosuzWhKNg7vfFCVoVNQmdir3jkm8G/pAp0xpykWgV3ghwUZCwQuZZdP2UAA d88Z33qViNoasZY43BmZYaIHb0cFVNcKlz4tb52e5l9jxI9ktbzc0a3JXf7neJsMji0c XPI2rv+AiTzaErzt4Dp+uLUvqrcvAg0y/EQ+zANjgbsZzRAQItpshchMu+P9JWdqNA/A Wg== Received: from nasanppmta05.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3pk83t0fh0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 27 Mar 2023 12:45:10 +0000 Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 32RCj90B010745 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 27 Mar 2023 12:45:09 GMT Received: from qc-i7.hemma.eciton.net (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Mon, 27 Mar 2023 05:45:06 -0700 Date: Mon, 27 Mar 2023 13:45:02 +0100 From: "Leif Lindholm" To: Ard Biesheuvel CC: , Michael Kinney , Liming Gao , Jiewen Yao , Michael Kubacki , Sean Brogan , Rebecca Cran , Sami Mujawar , Taylor Beebe , Marvin =?iso-8859-1?Q?H=E4user?= , Bob Feng Subject: Re: [PATCH v2 01/17] MdePkg/ProcessorBind AARCH64: Add asm macro to emit GNU BTI note Message-ID: References: <20230327110112.262503-1-ardb@kernel.org> <20230327110112.262503-2-ardb@kernel.org> MIME-Version: 1.0 In-Reply-To: <20230327110112.262503-2-ardb@kernel.org> X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: mNzDuRf6_QATU69ibofg2bYix2LJMAVg X-Proofpoint-GUID: mNzDuRf6_QATU69ibofg2bYix2LJMAVg X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-24_11,2023-03-27_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 priorityscore=1501 malwarescore=0 suspectscore=0 bulkscore=0 mlxlogscore=900 spamscore=0 phishscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2303270099 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline On Mon, Mar 27, 2023 at 13:00:56 +0200, Ard Biesheuvel wrote: > Implement a CPP macro that can be called from .S files to emit the .note > section carrying the annotation that informs the linker that the object > file is compatible with BTI control flow integrity checks. > > Signed-off-by: Ard Biesheuvel > --- > MdePkg/Include/AArch64/ProcessorBind.h | 31 ++++++++++++++++++++ > 1 file changed, 31 insertions(+) > > diff --git a/MdePkg/Include/AArch64/ProcessorBind.h b/MdePkg/Include/AArch64/ProcessorBind.h > index abe2571245c665f3..11814f1ffaef698a 100644 > --- a/MdePkg/Include/AArch64/ProcessorBind.h > +++ b/MdePkg/Include/AArch64/ProcessorBind.h > @@ -186,6 +186,37 @@ typedef INT64 INTN; > #define GCC_ASM_IMPORT(func__) \ > .extern _CONCATENATE (__USER_LABEL_PREFIX__, func__) > > +#if defined(__ARM_FEATURE_BTI_DEFAULT) && __ARM_FEATURE_BTI_DEFAULT == 1 > +#define AARCH64_BTI(__type) \ > + .ifnc __type, ;\ > + bti __type ;\ > + .endif ;\ This didn't jump out at me until looking at the consumer side. This overlays two different sets of functionality depending on whether an option is given to the macro or not, which feels semantically suboptimal to me (i.e. it makes my head hurt). Could we split this into two macros - one that inserts the instruction and one that inserts the note, and expand the latter in the former? / Leif > + .ifndef .Lgnu_bti_notesize ;\ > + .pushsection .note.gnu.property, "a" ;\ > + .set NT_GNU_PROPERTY_TYPE_0, 0x5 ;\ > + .set GNU_PROPERTY_AARCH64_FEATURE_1_AND, 0xc0000000 ;\ > + .set GNU_PROPERTY_AARCH64_FEATURE_1_BTI, 0x1 ;\ > + .align 3 ;\ > + .long .Lnamesize ;\ > + .long .Lgnu_bti_notesize ;\ > + .long NT_GNU_PROPERTY_TYPE_0 ;\ > +0: .asciz "GNU" ;\ > + .set .Lnamesize, . - 0b ;\ > + .align 3 ;\ > +1: .long GNU_PROPERTY_AARCH64_FEATURE_1_AND ;\ > + .long .Lvalsize ;\ > +2: .long GNU_PROPERTY_AARCH64_FEATURE_1_BTI ;\ > + .set .Lvalsize, . - 2b ;\ > + .align 3 ;\ > + .set .Lgnu_bti_notesize, . - 1b ;\ > + .popsection ;\ > + .endif > +#endif > + > +#endif > + > +#ifndef AARCH64_BTI > +#define AARCH64_BTI(__type) > #endif > > /** > -- > 2.39.2 >