From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by mx.groups.io with SMTP id smtpd.web11.36352.1679927079161857045 for ; Mon, 27 Mar 2023 07:24:39 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="body hash did not verify" header.i=@quicinc.com header.s=qcppdkim1 header.b=mqxw//79; spf=permerror, err=parse error for token &{10 18 %{ir}.%{v}.%{d}.spf.has.pphosted.com}: invalid domain name (domain: quicinc.com, ip: 205.220.168.131, mailfrom: quic_llindhol@quicinc.com) Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 32RDeJRv031844; Mon, 27 Mar 2023 14:24:27 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=date : from : to : cc : subject : message-id : references : mime-version : content-type : content-transfer-encoding : in-reply-to; s=qcppdkim1; bh=o0ZF828225qfi5RbKDlUfp4WW1AOoUuIT0d+pPE8j0g=; b=mqxw//79T+YM5A62yu/PEKWuuspFCG6h9SgrUqsitmX80S28Pz8qXRDt6xOL48M2qM/b 8LexiXubhAaeNK79ICSiHyJDEEhTcs2TdRJ9OLWbSwjJvm+qz+rTkM9fITQxjNNxjlG0 ZHjz0+27vKz68Agul+kxj+aMMNdKlD0DfnP6xqaxw43XnrVRq/fZHgdfACjM6qQ+Wyjf HVeQjUipgjMWhmvQHDnmycqCtvmLwF2lvU/VVFrzj0aTBDyQt/poaiSGrJMec4X5LJf3 zVASij/j8NqExqWqZgaMKmLX+RJUtvM9KG8NdZCE5miYwPZlcqT4z15z3pNzwbXHST+J bg== Received: from nasanppmta04.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3pk8pvgm2v-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 27 Mar 2023 14:24:26 +0000 Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 32REOAXF018760 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 27 Mar 2023 14:24:10 GMT Received: from qc-i7.hemma.eciton.net (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Mon, 27 Mar 2023 07:24:06 -0700 Date: Mon, 27 Mar 2023 15:24:03 +0100 From: "Leif Lindholm" To: , CC: , Michael Kinney , Liming Gao , Jiewen Yao , Michael Kubacki , Sean Brogan , Rebecca Cran , Sami Mujawar , Taylor Beebe , Marvin =?iso-8859-1?Q?H=E4user?= , Bob Feng Subject: Re: [edk2-devel] [PATCH v2 01/17] MdePkg/ProcessorBind AARCH64: Add asm macro to emit GNU BTI note Message-ID: References: <20230327110112.262503-1-ardb@kernel.org> <20230327110112.262503-2-ardb@kernel.org> MIME-Version: 1.0 In-Reply-To: X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: vdiO2rKCpB7fNaBrL9pLxDEWIred3_d_ X-Proofpoint-ORIG-GUID: vdiO2rKCpB7fNaBrL9pLxDEWIred3_d_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-24_11,2023-03-27_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 malwarescore=0 clxscore=1011 lowpriorityscore=0 suspectscore=0 mlxlogscore=999 spamscore=0 phishscore=0 bulkscore=0 priorityscore=1501 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2303270114 X-MIME-Autoconverted: from 8bit to quoted-printable by mx0a-0031df01.pphosted.com id 32RDeJRv031844 Content-Type: text/plain; charset="utf-8" Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Mar 27, 2023 at 15:12:29 +0100, Pedro Falcato wrote: > On Mon, Mar 27, 2023 at 12:01=E2=80=AFPM Ard Biesheuvel = wrote: > > > > Implement a CPP macro that can be called from .S files to emit the .not= e > > section carrying the annotation that informs the linker that the object > > file is compatible with BTI control flow integrity checks. > > > > Signed-off-by: Ard Biesheuvel > > --- > > MdePkg/Include/AArch64/ProcessorBind.h | 31 ++++++++++++++++++++ > > 1 file changed, 31 insertions(+) > > > > diff --git a/MdePkg/Include/AArch64/ProcessorBind.h b/MdePkg/Include/AA= rch64/ProcessorBind.h > > index abe2571245c665f3..11814f1ffaef698a 100644 > > --- a/MdePkg/Include/AArch64/ProcessorBind.h > > +++ b/MdePkg/Include/AArch64/ProcessorBind.h > > @@ -186,6 +186,37 @@ typedef INT64 INTN; > > #define GCC_ASM_IMPORT(func__) \ > > .extern _CONCATENATE (__USER_LABEL_PREFIX__, func__) > > > > +#if defined(__ARM_FEATURE_BTI_DEFAULT) && __ARM_FEATURE_BTI_DEFAULT = =3D=3D 1 > > +#define AARCH64_BTI(__type) \ > > + .ifnc __type, ;\ > > + bti __type ;\ > > + .endif ;\ > > + .ifndef .Lgnu_bti_notesize ;\ > > + .pushsection .note.gnu.property, "a" ;\ > > + .set NT_GNU_PROPERTY_TYPE_0, 0x5 ;\ > > + .set GNU_PROPERTY_AARCH64_FEATURE_1_AND, 0xc0000000 ;\ > > + .set GNU_PROPERTY_AARCH64_FEATURE_1_BTI, 0x1 ;\ > > + .align 3 ;\ > > + .long .Lnamesize ;\ > > + .long .Lgnu_bti_notesize ;\ > > + .long NT_GNU_PROPERTY_TYPE_0 ;\ > > +0: .asciz "GNU" ;\ > > + .set .Lnamesize, . - 0b ;\ > > + .align 3 ;\ > > +1: .long GNU_PROPERTY_AARCH64_FEATURE_1_AND ;\ > > + .long .Lvalsize ;\ > > +2: .long GNU_PROPERTY_AARCH64_FEATURE_1_BTI ;\ > > + .set .Lvalsize, . - 2b ;\ > > + .align 3 ;\ > > + .set .Lgnu_bti_notesize, . - 1b ;\ > > + .popsection ;\ > > + .endif > > +#endif > > + > > +#endif > > + > > +#ifndef AARCH64_BTI > > +#define AARCH64_BTI(__type) > > #endif > > > > /** > > -- > > 2.39.2 >=20 > Patch-set wide comment: is there any chance we could take this > opportunity to introduce a global ASM_FUNC (or a more Linux-named > ENTRY(FuncName))? > It seems to be that the current way is a bit error prone and you end > up repeating yourself quite a bit with: >=20 > ASM_PFX(Foo): > AARCH64_BTI(c) > >=20 > having a: > ASM_FUNC(Foo) > >=20 > that does proper PFX and BTI expansion internally seems better to me. I was thinking while looking at this patch that ASM_FUNC could probably do with moving over to this file from AsmMacroIoLibV8.h. I didn't take the thought far enough to consider including the BTI bits in that, but I guess that could make sense. / Leif >=20 > --=20 > Pedro >=20 >=20 >=20 >=20 >=20