From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by mx.groups.io with SMTP id smtpd.web10.21882.1680173278170918352 for ; Thu, 30 Mar 2023 03:47:58 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=n++yWtYz; spf=permerror, err=parse error for token &{10 18 %{ir}.%{v}.%{d}.spf.has.pphosted.com}: invalid domain name (domain: quicinc.com, ip: 205.220.180.131, mailfrom: quic_llindhol@quicinc.com) Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 32U8mDk5001622; Thu, 30 Mar 2023 10:47:45 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=date : from : to : cc : subject : message-id : references : mime-version : content-type : in-reply-to; s=qcppdkim1; bh=sN9Lv0iUmRvB3SbNcuWta6vZ6kRToZKDA8nBrQX1S/s=; b=n++yWtYz6fvenRXw+4DS2pDYQu1RGUbD4vseXr1fug+tNWcjDnK0MqhCdk8pGOx56hbq Hmrg0N7ZO/9Yz7YMsrl5HCvWkA5qvZJkgWppRuxddF2+ZOCUqljt3GUNlw/4sL4iJu5C CpGQ7z/1OJXiTFL39nsfcmotO9OXGu++xB0BHIvuazR+K/r9Oq/15CfpDrepLYIXD6se Zy20KMsb8rqw9t4Lbl2LYfnzITb9V2uAv0VgQMpQazQ1DBZ46PUDmWUcCN+ycVVxaqWI ya/v+0Jgj1HIAYM3NuccENKXfQfcY5lU4FFd6uq1L4y9IR++RU1iyInMQ/2V7LWUAdlt +w== Received: from nasanppmta02.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3pmpbm321e-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 30 Mar 2023 10:47:45 +0000 Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 32UAliUT021868 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 30 Mar 2023 10:47:44 GMT Received: from qc-i7.hemma.eciton.net (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Thu, 30 Mar 2023 03:47:41 -0700 Date: Thu, 30 Mar 2023 11:47:38 +0100 From: "Leif Lindholm" To: , CC: , Michael Kinney , Liming Gao , Jiewen Yao , Michael Kubacki , Sean Brogan , Rebecca Cran , Sami Mujawar , Taylor Beebe , Marvin =?iso-8859-1?Q?H=E4user?= , Bob Feng Subject: Re: [edk2-devel] [PATCH v2 01/17] MdePkg/ProcessorBind AARCH64: Add asm macro to emit GNU BTI note Message-ID: References: <20230327110112.262503-1-ardb@kernel.org> <20230327110112.262503-2-ardb@kernel.org> MIME-Version: 1.0 In-Reply-To: X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Ws8y03NfrBsBGcT8DazQ9CoSNiYotM4w X-Proofpoint-ORIG-GUID: Ws8y03NfrBsBGcT8DazQ9CoSNiYotM4w X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-30_06,2023-03-30_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 spamscore=0 clxscore=1015 suspectscore=0 bulkscore=0 malwarescore=0 lowpriorityscore=0 mlxlogscore=952 adultscore=0 phishscore=0 priorityscore=1501 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2303300086 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline On Thu, Mar 30, 2023 at 09:28:45 +0200, Ard Biesheuvel wrote: > > > Patch-set wide comment: is there any chance we could take this > > > opportunity to introduce a global ASM_FUNC (or a more Linux-named > > > ENTRY(FuncName))? > > > It seems to be that the current way is a bit error prone and you end > > > up repeating yourself quite a bit with: > > > > > > ASM_PFX(Foo): > > > AARCH64_BTI(c) > > > > > > > > > having a: > > > ASM_FUNC(Foo) > > > > > > > > > that does proper PFX and BTI expansion internally seems better to me. > > > > I was thinking while looking at this patch that ASM_FUNC could > > probably do with moving over to this file from AsmMacroIoLibV8.h. > > I didn't take the thought far enough to consider including the BTI > > bits in that, but I guess that could make sense. > > Yeah, but I'd prefer it if we could do that globally, and not just for > AArch64 as part of this series. Yeah, no issue with that. This set adds primitives that will be useful for that in future. / Leif