From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by mx.groups.io with SMTP id smtpd.web11.6929.1681761132044385899 for ; Mon, 17 Apr 2023 12:52:12 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="body hash did not verify" header.i=@quicinc.com header.s=qcppdkim1 header.b=b/F7pnKB; spf=permerror, err=parse error for token &{10 18 %{ir}.%{v}.%{d}.spf.has.pphosted.com}: invalid domain name (domain: quicinc.com, ip: 205.220.180.131, mailfrom: quic_llindhol@quicinc.com) Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 33HITQMR019126; Mon, 17 Apr 2023 19:52:08 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=date : from : to : cc : subject : message-id : references : mime-version : content-type : content-transfer-encoding : in-reply-to; s=qcppdkim1; bh=1BlUxlAfKG7XxRVtbBe8G5FopcKRNZXrXAAXngpvxXc=; b=b/F7pnKB7iHo1O63UHfgj3bC9E71dM1kl0OKTqaG+kTqUIKVXLFR6JdXy/GCSpHL3jHR rXpfxtyojBtQlfcn1uIPdzth7ueRUNxJUipkHcL07gJsqlqJx/YgON7Qh5C90eZTgUsI 7pu43Q6uDDk5YKmo5EjWAn5wrQOtUF1V6WTFTdFi46puEKqm7iLWu8c7h6jyyjNcM8ww oDINO0QAd7/J8Mx11ABV/0VM0zYBBYgCq28IOoxlXzcwWcfu0xUsLDb9/Ig4zz/3Fix7 Q/c6XDLhjvfq8tim7PWoM4TQpdFUABAWqYi8zvc3qggyum8dmsMUXUq8bQ84+PGlROaq Nw== Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3q14gk9ap4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 17 Apr 2023 19:52:08 +0000 Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 33HJq7vU011502 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 17 Apr 2023 19:52:07 GMT Received: from qc-i7.hemma.eciton.net (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Mon, 17 Apr 2023 12:52:05 -0700 Date: Mon, 17 Apr 2023 20:52:02 +0100 From: "Leif Lindholm" To: Marvin =?utf-8?Q?Ha=CC=88user?= CC: , Ard Biesheuvel , Sami Mujawar , Vitaly Cheptsov Subject: Re: [PATCH 1/2] ArmPkg/AsmMacroIoLibV8: Introduce ASM_FUNC_ALIGN() Message-ID: References: <20230417180916.95237-1-mhaeuser@posteo.de> MIME-Version: 1.0 In-Reply-To: <20230417180916.95237-1-mhaeuser@posteo.de> X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 60BzM18TKY9BhFI3tHcH3IrAq4hnpqVG X-Proofpoint-GUID: 60BzM18TKY9BhFI3tHcH3IrAq4hnpqVG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-04-17_12,2023-04-17_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 mlxlogscore=464 mlxscore=0 priorityscore=1501 phishscore=0 suspectscore=0 bulkscore=0 impostorscore=0 clxscore=1011 lowpriorityscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2304170175 X-MIME-Autoconverted: from 8bit to quoted-printable by mx0a-0031df01.pphosted.com id 33HITQMR019126 Content-Type: text/plain; charset="utf-8" Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hi Marvin, First of all - many thanks for tracking down the bug that creates the need for this. On Mon, Apr 17, 2023 at 18:09:15 +0000, Marvin Ha=CC=88user wrote: > With the current ASM_FUNC() macro, there is no good way to declare an > alignment constraint for a function. As ASM_FUNC() switches sections, > declaring the constraint before the macro invocation applies it to the > current location in the previous section. Declaring the constraint afte= r > the macro invocation lets the function label point to the location prio= r > to alignment. Depending on toolchain behaviour, this may cause the labe= l > to point to alignment padding preceding the actual function definition. >=20 > To address these issues, introduce the ASM_FUNC_ALIGN() macro, which > declares the alignment constraint right before the function label. >=20 > Signed-off-by: Marvin H=C3=A4user > Cc: Leif Lindholm > Cc: Ard Biesheuvel > Cc: Sami Mujawar > Cc: Vitaly Cheptsov > --- > ArmPkg/Include/AsmMacroIoLibV8.h | 22 ++++++++++++++++++---- > 1 file changed, 18 insertions(+), 4 deletions(-) >=20 > diff --git a/ArmPkg/Include/AsmMacroIoLibV8.h b/ArmPkg/Include/AsmMacro= IoLibV8.h > index 135aaeca5d0b..919edc70384d 100644 > --- a/ArmPkg/Include/AsmMacroIoLibV8.h > +++ b/ArmPkg/Include/AsmMacroIoLibV8.h > @@ -34,15 +34,29 @@ > cbnz SAFE_XREG, 1f ;\ > b . ;// We should never get here > =20 > -#define _ASM_FUNC(Name, Section) \ > - .global Name ; \ > - .section #Section, "ax" ; \ > - .type Name, %function ; \ > +#define _ASM_FUNC_HDR(Name, Section) \ > + .global Name ; \ > + .section #Section, "ax" ; \ > + .type Name, %function > + > +#define _ASM_FUNC_FTR(Name) \ > Name: ; \ > AARCH64_BTI(c) > =20 > +#define _ASM_FUNC(Name, Section) \ > + _ASM_FUNC_HDR(Name, Section) ; \ > + _ASM_FUNC_FTR(Name) > + > +#define _ASM_FUNC_ALIGN(Name, Section, Align) \ I like this solution, but I'd like to hear Ard's opinion. I probably want to bikeshed some of the implementation details: Although I generally dislike duplicate definitions, I think I would prefer having _ASM_FUNC and _ASM_FUNC_ALIGN defined self-contained, without _HDR and _FTR. If we do keep the reused primitives, we need better language; the footer of the header is not a footer of the function. / Leif > + _ASM_FUNC_HDR(Name, Section) ; \ > + .balign Align ; \ > + _ASM_FUNC_FTR(Name) > + > #define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name) > =20 > +#define ASM_FUNC_ALIGN(Name, Align) \ > + _ASM_FUNC_ALIGN(ASM_PFX(Name), .text. ## Name, Align) > + > #define MOV32(Reg, Val) \ > movz Reg, (Val) >> 16, lsl #16 ; \ > movk Reg, (Val) & 0xffff > --=20 > 2.40.0 >=20