From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by mx.groups.io with SMTP id smtpd.web11.6963.1681761229243309830 for ; Mon, 17 Apr 2023 12:53:49 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="body hash did not verify" header.i=@quicinc.com header.s=qcppdkim1 header.b=HnBRCfgB; spf=permerror, err=parse error for token &{10 18 %{ir}.%{v}.%{d}.spf.has.pphosted.com}: invalid domain name (domain: quicinc.com, ip: 205.220.180.131, mailfrom: quic_llindhol@quicinc.com) Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 33HJ0NLo010303; Mon, 17 Apr 2023 19:53:46 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=date : from : to : cc : subject : message-id : references : mime-version : content-type : content-transfer-encoding : in-reply-to; s=qcppdkim1; bh=fiHVifekR4jACa87UDzQM7+lqanBMzEZYG4WTwJawGQ=; b=HnBRCfgBXmHNQRC4Oz9OWJmXD3N9Q53yzs7e74r5VW8KYV8zW9gNfIaeMoWMhrjjJH8R JsThpFJNVPMSzEAQaXPD6frLXfDRwYu7IKiabFkezKI8cORGTv8jvjuBF2Ez1LU78JFt FRd7ZC7UMl/KfljJu7cVVjhFBGLEx0ZiwZTuu2FjWzinQwmSW8HAXF1XvsAFKijLH+aP VDpAG5eOCkm8jV29T6VNY0Rz3bVlA6/6eb5BU1FQiuk4QOH2qXTM5+SV5QDcFYBYgzH0 3tALfD7is6azF/P9PyiOXZnELucr+8VTN3FvrKqrzrbBwrCaReeZRHVUeA9gdw/8kh0/ Eg== Received: from nasanppmta02.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3q1bvkr345-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 17 Apr 2023 19:53:46 +0000 Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 33HJri1K004899 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 17 Apr 2023 19:53:45 GMT Received: from qc-i7.hemma.eciton.net (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Mon, 17 Apr 2023 12:53:43 -0700 Date: Mon, 17 Apr 2023 20:53:40 +0100 From: "Leif Lindholm" To: Marvin =?utf-8?Q?Ha=CC=88user?= CC: , Ard Biesheuvel , Sami Mujawar , Vitaly Cheptsov Subject: Re: [PATCH 2/2] ArmPkg/ArmMmuLib: Fix ArmReplaceLiveTranslationEntry() alignment Message-ID: References: <20230417180916.95237-1-mhaeuser@posteo.de> <20230417180916.95237-2-mhaeuser@posteo.de> MIME-Version: 1.0 In-Reply-To: <20230417180916.95237-2-mhaeuser@posteo.de> X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: YN0fynnMxNeCC7NxXlbD1SkfDoEA_FnG X-Proofpoint-ORIG-GUID: YN0fynnMxNeCC7NxXlbD1SkfDoEA_FnG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-04-17_13,2023-04-17_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 mlxlogscore=445 impostorscore=0 malwarescore=0 adultscore=0 lowpriorityscore=0 bulkscore=0 suspectscore=0 clxscore=1015 mlxscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2304170175 X-MIME-Autoconverted: from 8bit to quoted-printable by mx0a-0031df01.pphosted.com id 33HJ0NLo010303 Content-Type: text/plain; charset="utf-8" Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Apr 17, 2023 at 18:09:16 +0000, Marvin Ha=CC=88user wrote: > As the ASM_FUNC() macro performs a section switch, the preceding > .balign directive applies the alignment constraint to the current > location in the previous section. As the linker may not merge the > sections in-order, ArmReplaceLiveTranslationEntry() may be left > unaligned. >=20 > Replace the explicit invocation of .balign with the ASM_FUNC_ALIGN() > macro, which guarantees the alignment constraint is applied correctly. >=20 > Signed-off-by: Marvin H=C3=A4user > Cc: Leif Lindholm > Cc: Ard Biesheuvel > Cc: Sami Mujawar > Cc: Vitaly Cheptsov Assuming we reach consensus on the preceding patch, this one is a no brainer: Reviewed-by: Leif Lindholm > --- > ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibReplaceEntry.S | 9 ++++----- > 1 file changed, 4 insertions(+), 5 deletions(-) >=20 > diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibReplaceEntry.S b= /ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibReplaceEntry.S > index e936a5be4e11..7627aeb95464 100644 > --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibReplaceEntry.S > +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibReplaceEntry.S > @@ -69,17 +69,16 @@ > .L2_\@: > .endm > =20 > - // Align this routine to a log2 upper bound of its size, so that it = is > - // guaranteed not to cross a page or block boundary. > - .balign 0x200 > - > //VOID > //ArmReplaceLiveTranslationEntry ( > // IN UINT64 *Entry, > // IN UINT64 Value, > // IN UINT64 Address > // ) > -ASM_FUNC(ArmReplaceLiveTranslationEntry) > +// > +// Align this routine to a log2 upper bound of its size, so that it is > +// guaranteed not to cross a page or block boundary. > +ASM_FUNC_ALIGN(ArmReplaceLiveTranslationEntry, 0x200) > =20 > // disable interrupts > mrs x4, daif > --=20 > 2.40.0 >=20