From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by mx.groups.io with SMTP id smtpd.web10.19110.1684752980644070669 for ; Mon, 22 May 2023 03:56:20 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=NuMarrNA; spf=permerror, err=parse error for token &{10 18 %{ir}.%{v}.%{d}.spf.has.pphosted.com}: invalid domain name (domain: quicinc.com, ip: 205.220.180.131, mailfrom: quic_llindhol@quicinc.com) Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 34MAhdGw002977; Mon, 22 May 2023 10:56:12 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=date : from : to : cc : subject : message-id : references : mime-version : content-type : in-reply-to; s=qcppdkim1; bh=DTbIAirKf3FFk3+an/3ciOAsR4n6Jvk4ZS23HszeBks=; b=NuMarrNAfKeHZEU4Ywapbo1DkKQXyHJjxEKadkhuJmqUaW3ubiu9QOtmAp/IDAceArqQ /MkV4aQk7JFi046teqZqb1iv6g7Hr6JLlW1PSamngCDIVHntmCh2pNsVuA7wWPK8PaIw tisdDK0yYQ0GoUtnbkZXTKxppHkTA3cwbQJEYtPCqUhkPsN2+MmiAGW0XaHylLtXwB8H TfmX0CdnFTD+kVpTEbmK13C42h5j499axjSKrtBmSYYvSL50kX9RBr5F5Hkf6JgvAOvE tR5wCK5O5lZI1YkNpD8aqBTBo9t680IdBay6oK/YxXQ9FNM78/XDjWIyLpcjcN7SiRQh Yw== Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3qppkdkgf6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 22 May 2023 10:56:12 +0000 Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 34MAuAjJ032683 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 22 May 2023 10:56:10 GMT Received: from qc-i7.hemma.eciton.net (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Mon, 22 May 2023 03:56:08 -0700 Date: Mon, 22 May 2023 11:56:05 +0100 From: "Leif Lindholm" To: Ard Biesheuvel CC: , Liming Gao , Michael D Kinney , Oliver Steffen Subject: Re: [PATCH edk2-stable202305] ArmPkg/ArmMmuLib: Add missing ISB after page table update Message-ID: References: <20230520091958.310712-1-ardb@kernel.org> MIME-Version: 1.0 In-Reply-To: <20230520091958.310712-1-ardb@kernel.org> X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: WbxzvNdYRM4J_7QXmEirI0gWtyZtvxR- X-Proofpoint-GUID: WbxzvNdYRM4J_7QXmEirI0gWtyZtvxR- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-22_06,2023-05-22_03,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 spamscore=0 bulkscore=0 malwarescore=0 mlxlogscore=999 suspectscore=0 adultscore=0 phishscore=0 mlxscore=0 impostorscore=0 priorityscore=1501 clxscore=1011 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305220093 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline On Sat, May 20, 2023 at 11:19:58 +0200, Ard Biesheuvel wrote: > The helper that updates live page table entries writes a zero entry, > invalidates the covered address range from the TLBs, and finally writes > the actual entry. This ensures that no TLB conflicts can occur. > > Writing the final entry needs to complete before any translations can be > performed, as otherwise, the zero entry, which describes an invalid > translation, may be observed by the page table walker, resulting in a > translation fault. For this reason, the final write is followed by a DSB > barrier instruction. > > However, this barrier will not stall the pipeline, and instruction > fetches may still hit this invalid translation, as has been observed and > reported by Oliver. To ensure that the new translation is fully active > before returning from this helper, we have to insert an ISB barrier as > well. > > Cc: Liming Gao > Cc: Leif Lindholm > Cc: Michael D Kinney > Reported-by: Oliver Steffen > Tested-by: Oliver Steffen > Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm We need this in the stable tag. Note: the isb instruction forces the synchronization of certain architectural events. It has no other effects. I.e., any issues exposed by this addition would already have been present before it. As such, I would suggest this addition need *not* affect the stable tag schedule. / Leif > --- > ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibReplaceEntry.S | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibReplaceEntry.S b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibReplaceEntry.S > index 887439bc042f0f16..1f0d8057926933d7 100644 > --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibReplaceEntry.S > +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibReplaceEntry.S > @@ -65,6 +65,7 @@ > // write updated entry > str x1, [x0] > dsb nshst > + isb > > .L2_\@: > .endm > -- > 2.39.2 >