From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-oi1-f175.google.com (mail-oi1-f175.google.com [209.85.167.175]) by mx.groups.io with SMTP id smtpd.web10.5338.1686047487471181936 for ; Tue, 06 Jun 2023 03:31:27 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@ventanamicro.com header.s=google header.b=QuGMkVBL; spf=pass (domain: ventanamicro.com, ip: 209.85.167.175, mailfrom: sunilvl@ventanamicro.com) Received: by mail-oi1-f175.google.com with SMTP id 5614622812f47-39a97058691so2980533b6e.2 for ; Tue, 06 Jun 2023 03:31:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1686047487; x=1688639487; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=/hzbZGqT3PD2SWMu5Lhoyc2LQQpMfvChDgKzgFpfbs0=; b=QuGMkVBLC0HOCfVbR2n7yg0E7NVX8CaL8ENiu0ln3AV48f4NLaxmzGxhrPhvowOGya eRdzvL3Peem1WVOvQqJTnRIjfmO6gUDYlMuql8t+jyvud7SzjVUME0oh32KHTzqTWFXj EF3dI3iP2hXt/2On/HdvFyE1UPUbF9hziiNWNz1WvyypEm63old7fT+cdfI9jT/A9/qJ +2KJO5ni+hE4f809eJL2UcadEUj5T4JEn++YoyQbwjVsNHN8IoYN0p0bk+19CgJnSqRj cBm4BwEiLVn1HeQBpUgKNmzTnOVqtiTds9TYdME4w58WK2niiOc1KPc3m6mwVrHoeJzP T1tw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686047487; x=1688639487; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=/hzbZGqT3PD2SWMu5Lhoyc2LQQpMfvChDgKzgFpfbs0=; b=lb2XEiLtvG3p/8/yv9TRNbWayYR+5IEsxFboQ0/dUfquF9x4tqT+m0U+nj+m33BQHm 3IrYXphfXfayZ9W9imcnqmhT1QHNS6gN55xR3+jCDukwcZ7BaAjTpUlIq1b7414rcW3d lTRqJtU5EWCm2/QmLTZNF9kr5vVR8rccaYb7G/a6iThy6bF79HXlbN65twXCNXaH5wgf PIOLDG326gRHBk9t6dz8PET3CpUWZBjGz5bOyvCsXdGL/lOnh5tMnr/AAD+M+Z0/8feR Fx6MXanQbMOKlV0uZaIStlPhqyfXtnHjIph19vo2GQ+hCy5UOHl1wckhWNJ9tGKupvLk ekzA== X-Gm-Message-State: AC+VfDzrZJW4nDTLb1OvbeBN1xAr0H58QNCyuiXJxVnAiDUY6EAmpEKy q5atGeZBHOiII/iByouwgU1iOg== X-Google-Smtp-Source: ACHHUZ6RWoO8sDU3Q6cbSE547n8lEm1dGS8hpH+N0P95pc33nARzQZq5plAVJA/R29UqK/GG9GMUrA== X-Received: by 2002:aca:f13:0:b0:398:12ee:3b73 with SMTP id 19-20020aca0f13000000b0039812ee3b73mr1859887oip.36.1686047486818; Tue, 06 Jun 2023 03:31:26 -0700 (PDT) Return-Path: Received: from sunil-laptop ([106.51.186.3]) by smtp.gmail.com with ESMTPSA id c13-20020a17090a674d00b0024dee5cbe29sm7343729pjm.27.2023.06.06.03.31.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Jun 2023 03:31:26 -0700 (PDT) Date: Tue, 6 Jun 2023 16:01:20 +0530 From: "Sunil V L" To: Tuan Phan Cc: devel@edk2.groups.io, michael.d.kinney@intel.com, gaoliming@byosoft.com.cn, zhiguang.liu@intel.com, git@danielschaefer.me, andrei.warkentin@intel.com Subject: Re: [PATCH v3 2/7] MdePkg/Register: RISC-V: Add satp mode bits shift definition Message-ID: References: <20230526231733.6755-1-tphan@ventanamicro.com> <20230526231733.6755-3-tphan@ventanamicro.com> MIME-Version: 1.0 In-Reply-To: <20230526231733.6755-3-tphan@ventanamicro.com> Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Fri, May 26, 2023 at 04:17:28PM -0700, Tuan Phan wrote: > The satp mode bits shift is used cross modules. It should be defined > in one place. > > Signed-off-by: Tuan Phan > Reviewed-by: Andrei Warkentin > --- LGTM. Reviewed-by: Sunil V L