From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pf1-f172.google.com (mail-pf1-f172.google.com [209.85.210.172]) by mx.groups.io with SMTP id smtpd.web10.5407.1686047728255389898 for ; Tue, 06 Jun 2023 03:35:28 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="signature has expired" header.i=@ventanamicro.com header.s=google header.b=bY2ikFAI; spf=pass (domain: ventanamicro.com, ip: 209.85.210.172, mailfrom: sunilvl@ventanamicro.com) Received: by mail-pf1-f172.google.com with SMTP id d2e1a72fcca58-654f8b56807so3264118b3a.1 for ; Tue, 06 Jun 2023 03:35:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1686047727; x=1688639727; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=bAXJJ5gBPvVGJ7FmMOQ9ji5rz7UFsnFS1cP8FjxMkkY=; b=bY2ikFAINrIQIq2nIQXg649l1fD0TVIMQCSNoircos3sW7IN5GN+NKwxUVNIN1QWGH piTulAD8GWpBRXKGQ5hV1eT84fGDHjOPl/ArSACS4LqoX9UiLh0ztw+/FbeGb0juWJSa dMwGtg8fRNpQx8JFulu/ogV4qDSQ5uRlsUC1paBL8nYzdsMWl4ETYCyLcP1MP6JFPOnF EkUEraxD/pO0JjwrcE15ZK4Lpj96EvK5tmi0LlXgqgKFjPmKaF8xY8ZJ/PqOBpjEc0e/ LFN9Dr9tV1zHfbKf2n7Xl7HzDWYn5NaCXvkrF4C/t+i24V6ZkUD6ZA76XHcSduEBeHhW U+Vw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686047728; x=1688639728; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=bAXJJ5gBPvVGJ7FmMOQ9ji5rz7UFsnFS1cP8FjxMkkY=; b=Mb/fvR2ck/O/xlqcCISvymD1Zgu57o+9RmVIt/HDlZT9Nzxrd56qsTZhYqxwYsiCzB OCwPoJOm0ZWQM8gzbJ99K0wurTFrUvhDwLzLKVLGILBX2A2uS9Fm+pIqSGKmlCzzoJhb k28Qq0CAR1P1Oe7AF4RICgAsyIXJN1PbSJgJGa1KbCWq6yhoV5u1HcLgjl85FF5iLAx6 TEp6u2AGi4XusNnivqXLk8hKeRUIIodZbytmVcHVb3Q7h7bO/+LYnAu6zkKvu29Z55ho Vuwk6bGzNxBcd06Jt8OZLUuCM9pm7ukKEBo8EdvJNhJTZiHSo0/ca5QueoN8nC07tLHE MD2Q== X-Gm-Message-State: AC+VfDxyajro2NbDpYI+IIznaf4jAV9K4VJfusG4yrLxFehyAEr2irxC 48449tNrFtI8voilkuLC5tn9Yg== X-Google-Smtp-Source: ACHHUZ6QXRL28IPxpUNJiXKeaxXni2uafQOitRZS/qE1g9Nsyv+86aAVKs16hsfnveTkACypj2VMBg== X-Received: by 2002:a05:6a20:144e:b0:10a:e9ff:808d with SMTP id a14-20020a056a20144e00b0010ae9ff808dmr2535761pzi.0.1686047727712; Tue, 06 Jun 2023 03:35:27 -0700 (PDT) Return-Path: Received: from sunil-laptop ([106.51.186.3]) by smtp.gmail.com with ESMTPSA id t9-20020a63f349000000b00502e7115cbdsm7085384pgj.51.2023.06.06.03.35.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Jun 2023 03:35:27 -0700 (PDT) Date: Tue, 6 Jun 2023 16:05:21 +0530 From: "Sunil V L" To: Tuan Phan Cc: devel@edk2.groups.io, michael.d.kinney@intel.com, gaoliming@byosoft.com.cn, zhiguang.liu@intel.com, git@danielschaefer.me, andrei.warkentin@intel.com Subject: Re: [PATCH v3 4/7] OvmfPkg/RiscVVirt: Remove satp bare mode setting Message-ID: References: <20230526231733.6755-1-tphan@ventanamicro.com> <20230526231733.6755-5-tphan@ventanamicro.com> MIME-Version: 1.0 In-Reply-To: <20230526231733.6755-5-tphan@ventanamicro.com> Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Fri, May 26, 2023 at 04:17:30PM -0700, Tuan Phan wrote: > MMU now is initialized in CpuDxe. There is no point to set satp to bare > mode as that should be the default mode when booting edk2. > > Signed-off-by: Tuan Phan > Reviewed-by: Andrei Warkentin > --- > OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 1 + > OvmfPkg/RiscVVirt/Sec/Memory.c | 18 ++---------------- > 2 files changed, 3 insertions(+), 16 deletions(-) > > diff --git a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc > index 731f54f73f81..bc204ba5fe52 100644 > --- a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc > +++ b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc > @@ -83,6 +83,7 @@ > # RISC-V Architectural Libraries > CpuExceptionHandlerLib|UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/BaseRiscV64CpuExceptionHandlerLib.inf > RiscVSbiLib|MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf > + RiscVMmuLib|UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf > PlatformBootManagerLib|OvmfPkg/RiscVVirt/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf > ResetSystemLib|OvmfPkg/RiscVVirt/Library/ResetSystemLib/BaseResetSystemLib.inf > > diff --git a/OvmfPkg/RiscVVirt/Sec/Memory.c b/OvmfPkg/RiscVVirt/Sec/Memory.c > index 0e2690c73687..aad71ee5dcbb 100644 > --- a/OvmfPkg/RiscVVirt/Sec/Memory.c > +++ b/OvmfPkg/RiscVVirt/Sec/Memory.c > @@ -85,21 +85,6 @@ AddMemoryRangeHob ( > AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase)); > } > > -/** > - Configure MMU > -**/ > -STATIC > -VOID > -InitMmu ( > - ) > -{ > - // > - // Set supervisor translation mode to Bare mode > - // > - RiscVSetSupervisorAddressTranslationRegister ((UINT64)SATP_MODE_OFF << 60); > - DEBUG ((DEBUG_INFO, "%a: Set Supervisor address mode to bare-metal mode.\n", __func__)); > -} > - > /** > Publish system RAM and reserve memory regions. > > @@ -327,7 +312,8 @@ MemoryPeimInitialization ( > > AddReservedMemoryMap (FdtPointer); > > - InitMmu (); > + /* Make sure SEC is booting with bare mode */ > + ASSERT ((RiscVGetSupervisorAddressTranslationRegister () & SATP64_MODE) == (SATP_MODE_OFF << SATP64_MODE_SHIFT)); > Makes sense. LGTM. Reviewed-by: Sunil V L