From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-oi1-f177.google.com (mail-oi1-f177.google.com [209.85.167.177]) by mx.groups.io with SMTP id smtpd.web11.25599.1685604426413601649 for ; Thu, 01 Jun 2023 00:27:06 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="signature has expired" header.i=@ventanamicro.com header.s=google header.b=aGqGgtFZ; spf=pass (domain: ventanamicro.com, ip: 209.85.167.177, mailfrom: sunilvl@ventanamicro.com) Received: by mail-oi1-f177.google.com with SMTP id 5614622812f47-39a55e5cfc0so411615b6e.3 for ; Thu, 01 Jun 2023 00:27:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1685604425; x=1688196425; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=RJ1CQiBrzOEopkl/16Cb7IXeCYt32ZbajQWYLax/K1Y=; b=aGqGgtFZ4ZadjjaD252BLW8Urf6E4NadRDUC0O7vZZWBj3w2IkE/+CvJ8XmVQ2/KK5 Wx5bxmKhSxkHc20f1PR/LOV3P2D6n8atFkEC/jxdQKctICcbn211L73A7fDFWgsU1yUf 9GcrWteuUPV5t3yRx7PBXvq+FgctP//lbLswI/ShIuhtL7k7hNuRNJtCIGnKUd1YTj4D 6WVMiSU8PQ8U6QT46dolORcwuzFDJ26PdL+4P4g6ofG9Fxk5sex2S1dOq+aQlJeeeGeT aWtONJilGNU5DHcDmRM35G0pBV7OSxBl5MV9c3jjJoLoKLjUlewSkVwujv5mcU0WeRbu Lxpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685604425; x=1688196425; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=RJ1CQiBrzOEopkl/16Cb7IXeCYt32ZbajQWYLax/K1Y=; b=Vzns6p2IJsKN2hSOFWViDL2+fEc3XUIvIrYaK+aXqQCLlLj0vnFfIKAtgBBvdmioJE tr8Cf5bfML+8+hkUu1TQkvNFfof7yy6msmwVblzLDKYyUdFOgraO1i6LhCE5lS+NaxjW Rqt8LztbdFWX70ZJyDsVWU6CWwsK/1jEAXgK4iZlocQLcmOWqNcUAZ16bfRHEUKYU17M GAfaUUOmVUrQTpA1BEVzvEdyG6OymWJFkFPnFOV8cb6bNWult7pqL1OcOLPrkPNCVltL 3kf4sfcGU+iEg3L+SrRvA8lnpPSh+5OrvK4FBu4NlaMY4VIkh6xM+4yUiewxHaDvBQPC YkSQ== X-Gm-Message-State: AC+VfDxZQINHBMhhWG69RvSi6YlN+lTF0XMvNI2iHR8NOPVMKf0foKnw 1wk2uBVe3ArNfhTjF7BHQiwFMA== X-Google-Smtp-Source: ACHHUZ5CpJQ8hZaQmDJTTUr7U2x7lFmEZ9YMAejf8sqlhqdQdicFHrnIVwjhBjEs3WB3+cytocV+vA== X-Received: by 2002:a05:6808:309c:b0:398:43a7:e9fe with SMTP id bl28-20020a056808309c00b0039843a7e9femr7489389oib.20.1685604425635; Thu, 01 Jun 2023 00:27:05 -0700 (PDT) Return-Path: Received: from sunil-laptop ([106.51.83.242]) by smtp.gmail.com with ESMTPSA id n4-20020acaef04000000b00399dff24197sm1462960oih.5.2023.06.01.00.27.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Jun 2023 00:27:05 -0700 (PDT) Date: Thu, 1 Jun 2023 12:56:59 +0530 From: "Sunil V L" To: "Li, Yong" Cc: devel@edk2.groups.io, Andrei Warkentin , Evan Chai , Tuan Phan Subject: Re: [edk2-devel] [PATCH 1/1] MdePkg/BaseLib: Add SpeculationBarrier implementation for RiscV64 Message-ID: References: <176385E31A3644FB.14832@groups.io> MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Mon, May 29, 2023 at 01:51:46PM +0800, Li, Yong wrote: > > Hi Sunil, > > Could you help review this my first patch to edk2 community for RiscV, this is the change to MdePkg/Library/BaseLib/RiscV64. > Since it is for RiscV specific, I guess you are the only maintainer per the Maintainers.txt ? > Please let me know if need additional reviewer. > > Thanks in advance for your time and kind helping for this first patch. > Hi Yong, Thank you for the patch! Just one typo in the commit text and one question below. Otherwise, LGTM. > > On 2023/5/29 13:24, Li, Yong wrote: > > Impelement the SpeculationBarrier with implementations consisting of typo - "Implement" > > fence instruction which provides finer-grain memory orderings. > > Perform Data Barrier in RiscV: fence rw,rw > > Perform Instruction Barrier in RiscV: fence.i; fence r,r > > More detail is in Chapter 17, RVWMO Memory Consistency Model > > https://github.com/riscv/riscv-isa-manual > > > > This API is first introduced in the below commits for IA32 and x64 > > https://github.com/tianocore/edk2/commit/d9f1cac51bd354507e880e614d11a1dc160d38a3 > > https://github.com/tianocore/edk2/commit/e83d841fdc2878959185c4c6cc38a7a1e88377a4 > > and below the commit for ARM and AArch64 implementation > > https://github.com/tianocore/edk2/commit/c0959b4426b2da45cdb8146a5116bb4fd9b86534 > > > > This commit is to add the RiscV64 implementation which will be used by > > variable service under Variable/RuntimeDxe > > > > Cc: Andrei Warkentin > > Cc: Evan Chai > > Cc: Sunil V L > > Cc: Tuan Phan > > Signed-off-by: Yong Li > > --- > > MdePkg/Library/BaseLib/BaseLib.inf | 1 + > > .../BaseLib/RiscV64/SpeculationBarrier.S | 34 +++++++++++++++++++ > > 2 files changed, 35 insertions(+) > > create mode 100644 MdePkg/Library/BaseLib/RiscV64/SpeculationBarrier.S > > > > diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf > > index 3a48492b1a01..03c7b02e828b 100644 > > --- a/MdePkg/Library/BaseLib/BaseLib.inf > > +++ b/MdePkg/Library/BaseLib/BaseLib.inf > > @@ -404,6 +404,7 @@ [Sources.RISCV64] > > RiscV64/CpuScratch.S | GCC > > RiscV64/ReadTimer.S | GCC > > RiscV64/RiscVMmu.S | GCC > > + RiscV64/SpeculationBarrier.S | GCC > > > > [Sources.LOONGARCH64] > > Math64.c > > diff --git a/MdePkg/Library/BaseLib/RiscV64/SpeculationBarrier.S b/MdePkg/Library/BaseLib/RiscV64/SpeculationBarrier.S > > new file mode 100644 > > index 000000000000..581a7653996f > > --- /dev/null > > +++ b/MdePkg/Library/BaseLib/RiscV64/SpeculationBarrier.S > > @@ -0,0 +1,34 @@ > > +##------------------------------------------------------------------------------ > > +# > > +# SpeculationBarrier() for RISCV64 > > +# > > +# Copyright (c) 2023, Intel Corporation. All rights reserved. > > +# > > +# SPDX-License-Identifier: BSD-2-Clause-Patent > > +# > > +##------------------------------------------------------------------------------ > > + > > +.text > > +.p2align 2 > > + > > +ASM_GLOBAL ASM_PFX(SpeculationBarrier) > > + > > + > > +#/** > > +# Uses as a barrier to stop speculative execution. > > +# > > +# Ensures that no later instruction will execute speculatively, until all prior > > +# instructions have completed. > > +# > > +#**/ > > +#VOID > > +#EFIAPI > > +#SpeculationBarrier ( > > +# VOID > > +# ); > > +# > > +ASM_PFX(SpeculationBarrier): > > + fence rw,rw Don't we need fence iorw, iorw? Thanks, Sunil > > + fence.i > > + fence r,r > > + ret