From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pl1-f182.google.com (mail-pl1-f182.google.com [209.85.214.182]) by mx.groups.io with SMTP id smtpd.web10.6683.1689398476884910913 for ; Fri, 14 Jul 2023 22:21:16 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@ventanamicro.com header.s=google header.b=d6g3b35j; spf=pass (domain: ventanamicro.com, ip: 209.85.214.182, mailfrom: sunilvl@ventanamicro.com) Received: by mail-pl1-f182.google.com with SMTP id d9443c01a7336-1b89b75dc1cso25220535ad.1 for ; Fri, 14 Jul 2023 22:21:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1689398476; x=1691990476; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=sHfhWim4RIcTZEemMa2XG2Rfs6KcwVM3SVDrFp1Jj6I=; b=d6g3b35jRtYPrqltMYjdpB2sMzCNzHWlP8q00mHz7uqlf0wWN3vYIRUKXZdKLOuZHn qBByu1A/HmvKcgAgA9HclfTJO5MYSd2mjI1APHGl1bt7orQQoweHSdwlCjlq0sFEh940 KughAMy2V51iZ91XTpaJ0/CaLCZM8iqH9PiqWnXB0fUlMtVNHGHOA+7urloTD11ETVHy c+kvKGTxaNj4qM/FiT5XzVCISJiJ40in4mgtdg1TeX+MgUt6fPMzjYY7/S/zO2f20DHV 9nRUkcBO6nKgg5ixHRPoB1O2EnMqyPHM789XA722NGOdWnA9LFh3dtpT7BNZXqMj5rpy xhOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689398476; x=1691990476; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=sHfhWim4RIcTZEemMa2XG2Rfs6KcwVM3SVDrFp1Jj6I=; b=AT35ORxx4YMk/z4NggLqFIpV1/xVIZ2EUlWL53kHOc4OD0X3ceGWLzWMhlBVTjotbG KG1dDHuoN6mRjHRnJjwYqCfgySwfvYdGkY1NXHZlB7W1CRdwkYXCKr0B7eyl4sPzXOjS MSpoCZPq6KdTLsRkHduEMp6cGHNctlVex6WEo1ZcFHamsM8Xl2D9pMDtl+9A4Cw8nEae xD5MKUKFmeMYmNct1/EZGtczCFN4wRBGepyjX61Y6AYxMPCV6ON4iejSDqNsqj8suEF1 zIx0HFrIHEVwv8V94i0fWy9R7pR/Co33KRsaCPXVA43U4xeaVOB02vsBLZAm9820hVjQ 3K/g== X-Gm-Message-State: ABy/qLY/THJ2Lsvkjc+H6p8lALSOBjM1o/o8WZzctjoJOnZth8glrosX 3jfVQX5CtG1uBgHz98VrB0P4kg== X-Google-Smtp-Source: APBJJlGfCiqW2HL45QcfMQatdtcxY8uZ1B3ShXHrlp5qeanlSemAs/LMX4TkoGq6GKX3A3+47hkycQ== X-Received: by 2002:a17:902:ce90:b0:1b8:417d:d042 with SMTP id f16-20020a170902ce9000b001b8417dd042mr6344047plg.20.1689398475657; Fri, 14 Jul 2023 22:21:15 -0700 (PDT) Return-Path: Received: from sunil-laptop ([106.51.190.25]) by smtp.gmail.com with ESMTPSA id x21-20020a170902b41500b001b3bf8001a9sm8632729plr.48.2023.07.14.22.21.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Jul 2023 22:21:15 -0700 (PDT) Date: Sat, 15 Jul 2023 10:51:08 +0530 From: "Sunil V L" To: Tuan Phan Cc: devel@edk2.groups.io, michael.d.kinney@intel.com, gaoliming@byosoft.com.cn, zhiguang.liu@intel.com, git@danielschaefer.me, andrei.warkentin@intel.com, ardb+tianocore@kernel.org Subject: Re: [PATCH v4 0/7] RISC-V: Add MMU support Message-ID: References: <20230623183934.23905-1-tphan@ventanamicro.com> MIME-Version: 1.0 In-Reply-To: <20230623183934.23905-1-tphan@ventanamicro.com> Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Reviewed-by: Sunil V L On Fri, Jun 23, 2023 at 11:39:27AM -0700, Tuan Phan wrote: > This series adds MMU support for RISC-V. Only SV39/48/57 modes > are supported and tested. The MMU is required to support setting > page attribute which is the first basic step to support security > booting on RISC-V. > > There are two parts: > 1. Add MMU base library. MMU will be enabled during > CpuDxe initialization. > 2. Fix all resources should be populated in HOB > or added to GCD by driver before accessing when MMU enabled. > > All changes can be found in the branch tphan/riscv_mmu at: > https://github.com/pttuan/edk2.git > > Changes in v4: > - Rebased master. > - Added VirtNorFlashDxe to APRIORI DXE list. > > Changes in v3: > - Move MMU library to UefiCpuPkg. > - Add Andrei reviewed-by. > > Changes in v2: > - Move MMU core to a library. > - Setup SATP mode as highest possible that HW supports. > > Tuan Phan (7): > MdePkg/BaseLib: RISC-V: Support getting satp register value > MdePkg/Register: RISC-V: Add satp mode bits shift definition > OvmfPkg/RiscVVirt: VirtNorFlashPlatformLib: Fix wrong flash size > OvmfPkg/RiscVVirt: SEC: Add IO memory resource hob for platform > devices > OvmfPkg/RiscVVirt: Add VirtNorFlashDxe to APRIORI list > OvmfPkg: RiscVVirt: Remove satp bare mode setting > UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode > > MdePkg/Include/Library/BaseLib.h | 5 + > .../Include/Register/RiscV64/RiscVEncoding.h | 7 +- > MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S | 8 + > .../VirtNorFlashStaticLib.c | 3 +- > OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 1 + > OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf | 10 + > OvmfPkg/RiscVVirt/Sec/Memory.c | 18 +- > OvmfPkg/RiscVVirt/Sec/Platform.c | 62 ++ > UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c | 9 +- > UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h | 2 + > UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf | 2 + > UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h | 39 ++ > .../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 569 ++++++++++++++++++ > .../BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 26 + > .../Library/BaseRiscVMmuLib/RiscVMmuCore.S | 31 + > 15 files changed, 770 insertions(+), 22 deletions(-) > create mode 100644 UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h > create mode 100644 UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c > create mode 100644 UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf > create mode 100644 UefiCpuPkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S > > -- > 2.25.1 >