From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 6B3EFAC0ECD for ; Fri, 15 Sep 2023 10:57:24 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=R10X7M2B/ShpQBKATnnoist7B4C9bC/9awh3Q/vt69o=; c=relaxed/simple; d=groups.io; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version:In-Reply-To:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Type:Content-Disposition; s=20140610; t=1694775442; v=1; b=Ivvw5uab8Tg90HoSHhcqpThZdoAJA7C/7NFZk7JSzprv4WdYQstoEIoHC10GSYNeNxJtwaTe lYR6JamKz5VaUNP71oAPKyfGYSznVKLw4O88m3c4poxs+444PPWoYuUEedXJHa/wCdEXRWu83Lm AzTB1aMGbqi5tdBRwHdKnoX4= X-Received: by 127.0.0.2 with SMTP id 7lPJYY7687511x4edqHN2qGt; Fri, 15 Sep 2023 03:57:22 -0700 X-Received: from mail-pf1-f174.google.com (mail-pf1-f174.google.com [209.85.210.174]) by mx.groups.io with SMTP id smtpd.web11.17698.1694775442328205557 for ; Fri, 15 Sep 2023 03:57:22 -0700 X-Received: by mail-pf1-f174.google.com with SMTP id d2e1a72fcca58-68fba57030fso1882467b3a.3 for ; Fri, 15 Sep 2023 03:57:22 -0700 (PDT) X-Gm-Message-State: AuyWVONbMcfsZwwvhgy3lXpXx7686176AA= X-Google-Smtp-Source: AGHT+IEyTuaqoDMUTrOPH61zXUEuD8G62C6bsOVo1xP8+DVkjymFgMrht++7h9ykgEW53dmxtRPqhg== X-Received: by 2002:a05:6a20:244e:b0:137:e595:830f with SMTP id t14-20020a056a20244e00b00137e595830fmr1483365pzc.57.1694775441635; Fri, 15 Sep 2023 03:57:21 -0700 (PDT) X-Received: from sunil-laptop ([106.51.189.46]) by smtp.gmail.com with ESMTPSA id b12-20020a170902ed0c00b001c444f185b4sm63925pld.237.2023.09.15.03.57.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Sep 2023 03:57:21 -0700 (PDT) Date: Fri, 15 Sep 2023 16:27:15 +0530 From: "Sunil V L" To: caiyuqing_hz@163.com Cc: devel@edk2.groups.io, quic_llindhol@quicinc.com, libing1202@outlook.com, inochiama@outlook.com Subject: Re: [edk2-devel] [PATCH v3 5/8] Sophgo/SG2042Pkg: Add SEC module. Message-ID: References: <27f47b7e4d8a1837529b06b311ed14f16669a5b2.1694010673.git.202235273@mail.sdu.edu.cn> MIME-Version: 1.0 In-Reply-To: <27f47b7e4d8a1837529b06b311ed14f16669a5b2.1694010673.git.202235273@mail.sdu.edu.cn> Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: Content-Type: text/plain; charset=us-ascii Content-Disposition: inline X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=Ivvw5uab; dmarc=none; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io On Thu, Sep 07, 2023 at 06:25:48PM +0800, caiyuqing_hz@163.com wrote: > From: caiyuqing379 <202235273@mail.sdu.edu.cn> > > This module supports Sophgo SG2042 EVB platform. It uses the > PEI less design. Add this module in SG2042Pkg leveraging the > one from OvmfPkg/RiscVVirt. > > Signed-off-by: caiyuqing379 <202235273@mail.sdu.edu.cn> > Co-authored-by: USER0FISH > Cc: dahogn > Cc: meng-cz > Cc: yli147 > Cc: ChaiEvan > Cc: Sunil V L > Cc: Leif Lindholm > --- > Silicon/Sophgo/SG2042Pkg/Sec/SecMain.inf | 68 +++++ > Silicon/Sophgo/SG2042Pkg/Sec/SecMain.h | 104 +++++++ > Silicon/Sophgo/SG2042Pkg/Sec/Cpu.c | 29 ++ > Silicon/Sophgo/SG2042Pkg/Sec/Memory.c | 347 +++++++++++++++++++++++ > Silicon/Sophgo/SG2042Pkg/Sec/Platform.c | 130 +++++++++ > Silicon/Sophgo/SG2042Pkg/Sec/SecMain.c | 115 ++++++++ > Silicon/Sophgo/SG2042Pkg/Sec/SecEntry.S | 18 ++ > 7 files changed, 811 insertions(+) > create mode 100644 Silicon/Sophgo/SG2042Pkg/Sec/SecMain.inf > create mode 100644 Silicon/Sophgo/SG2042Pkg/Sec/SecMain.h > create mode 100644 Silicon/Sophgo/SG2042Pkg/Sec/Cpu.c > create mode 100644 Silicon/Sophgo/SG2042Pkg/Sec/Memory.c > create mode 100644 Silicon/Sophgo/SG2042Pkg/Sec/Platform.c > create mode 100644 Silicon/Sophgo/SG2042Pkg/Sec/SecMain.c > create mode 100644 Silicon/Sophgo/SG2042Pkg/Sec/SecEntry.S > > diff --git a/Silicon/Sophgo/SG2042Pkg/Sec/SecMain.inf b/Silicon/Sophgo/SG2042Pkg/Sec/SecMain.inf > new file mode 100644 > index 000000000000..3b4d6d6b86bc > --- /dev/null > +++ b/Silicon/Sophgo/SG2042Pkg/Sec/SecMain.inf > @@ -0,0 +1,68 @@ > +## @file > +# SEC Driver for RISC-V > +# > +# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
> +# Copyright (c) 2023, Academy of Intelligent Innovation, Shandong Universiy, China.P.R. All rights reserved.
> +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +## > + > +[Defines] > + INF_VERSION = 0x0001001B > + BASE_NAME = SecMainRiscV64 > + FILE_GUID = 125E1236-9D4F-457B-BF7E-6311C88A1621 > + MODULE_TYPE = SEC > + VERSION_STRING = 1.0 > + ENTRY_POINT = SecMain > + > +# > +# The following information is for reference only and not required by the build tools. > +# > +# VALID_ARCHITECTURES = RISCV64 > +# > + > +[Sources] > + SecEntry.S > + SecMain.c > + SecMain.h > + Cpu.c > + Memory.c > + Platform.c > + > +[Packages] > + EmbeddedPkg/EmbeddedPkg.dec > + MdeModulePkg/MdeModulePkg.dec > + MdePkg/MdePkg.dec > + UefiCpuPkg/UefiCpuPkg.dec > + Silicon/Sophgo/SG2042Pkg/SG2042Pkg.dec > + Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec > + > +[LibraryClasses] > + BaseLib > + DebugLib > + PcdLib > + IoLib > + PeCoffLib > + LzmaDecompressLib > + RiscVSbiLib > + PrePiLib > + FdtLib > + MemoryAllocationLib > + HobLib > + SerialPortLib > + > +[FixedPcd] > + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvBase ## CONSUMES > + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvSize ## CONSUMES > + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionBaseAddress ## CONSUMES > + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionSize ## CONSUMES > + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUMES > + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamSize ## CONSUMES > + > +[Guids] > + gFdtHobGuid ## PRODUCES > + > +[BuildOptions] > + GCC:*_*_*_PP_FLAGS = -D__ASSEMBLY__ > + > diff --git a/Silicon/Sophgo/SG2042Pkg/Sec/SecMain.h b/Silicon/Sophgo/SG2042Pkg/Sec/SecMain.h > new file mode 100644 > index 000000000000..9d615e9fa6a1 > --- /dev/null > +++ b/Silicon/Sophgo/SG2042Pkg/Sec/SecMain.h > @@ -0,0 +1,104 @@ > +/** @file > + Master header file for SecCore. > + > + Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
> + Copyright (c) 2023, Academy of Intelligent Innovation, Shandong Universiy, China.P.R. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#ifndef SEC_MAIN_H_ > +#define SEC_MAIN_H_ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +/** > + Entry point to the C language phase of SEC. After the SEC assembly > + code has initialized some temporary memory and set up the stack, > + the control is transferred to this function. > + > + @param SizeOfRam Size of the temporary memory available for use. > + @param TempRamBase Base address of temporary ram > + @param BootFirmwareVolume Base address of the Boot Firmware Volume. > +**/ > +VOID > +NORETURN > +EFIAPI > +SecStartup ( > + IN UINTN BootHartId, > + IN VOID *DeviceTreeAddress > + ); > + > +/** > + Auto-generated function that calls the library constructors for all of the module's > + dependent libraries. This function must be called by the SEC Core once a stack has > + been established. > + > +**/ > +VOID > +EFIAPI > +ProcessLibraryConstructorList ( > + VOID > + ); > + > +/** > + Perform Platform PEIM initialization. > + > + @return EFI_SUCCESS The platform initialized successfully. > + @retval Others - As the error code indicates > + > +**/ > +EFI_STATUS > +EFIAPI > +PlatformPeimInitialization ( > + IN VOID *DeviceTreeAddress > + ); > + > +/** > + Perform Memory PEIM initialization. > + > + @param DeviceTreeAddress Pointer to FDT. > + @return EFI_SUCCESS The platform initialized successfully. > + @retval Others - As the error code indicates > + > +**/ > +EFI_STATUS > +EFIAPI > +MemoryPeimInitialization ( > + IN VOID *DeviceTreeAddress > + ); > + > +/** > + Perform CPU PEIM initialization. > + > + @return EFI_SUCCESS The platform initialized successfully. > + @retval Others - As the error code indicates > + > +**/ > +EFI_STATUS > +EFIAPI > +CpuPeimInitialization ( > + VOID > + ); > + > +#endif > diff --git a/Silicon/Sophgo/SG2042Pkg/Sec/Cpu.c b/Silicon/Sophgo/SG2042Pkg/Sec/Cpu.c > new file mode 100644 > index 000000000000..c72bafdcc478 > --- /dev/null > +++ b/Silicon/Sophgo/SG2042Pkg/Sec/Cpu.c > @@ -0,0 +1,29 @@ > +/** @file > +The library call to pass the device tree to DXE via HOB. > + > +Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.
> + > +SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#include > +#include > +#include > + > +/** > + Cpu Peim initialization. > + > +**/ > +EFI_STATUS > +CpuPeimInitialization ( > + VOID > + ) > +{ > + // > + // for MMU type >= sv39 > + // > + BuildCpuHob (40, 39); > + > + return EFI_SUCCESS; > +} > diff --git a/Silicon/Sophgo/SG2042Pkg/Sec/Memory.c b/Silicon/Sophgo/SG2042Pkg/Sec/Memory.c > new file mode 100644 > index 000000000000..3fa4df148ad2 > --- /dev/null > +++ b/Silicon/Sophgo/SG2042Pkg/Sec/Memory.c > @@ -0,0 +1,347 @@ > +/** @file > + Memory Detection for SG2042 EVB. > + > + Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.
> + Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
> + Copyright (c) 2023, Academy of Intelligent Innovation, Shandong Universiy, China.P.R. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > + > +Module Name: > + > + MemDetect.c > + > +**/ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +VOID > +BuildMemoryTypeInformationHob ( > + VOID > + ); > + > +/** > + Create memory range resource HOB using the memory base > + address and size. > + > + @param MemoryBase Memory range base address. > + @param MemorySize Memory range size. > + > +**/ > +STATIC > +VOID > +AddMemoryBaseSizeHob ( > + IN EFI_PHYSICAL_ADDRESS MemoryBase, > + IN UINT64 MemorySize > + ) > +{ > + BuildResourceDescriptorHob ( > + EFI_RESOURCE_SYSTEM_MEMORY, > + EFI_RESOURCE_ATTRIBUTE_PRESENT | > + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | > + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | > + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | > + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | > + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | > + EFI_RESOURCE_ATTRIBUTE_TESTED, > + MemoryBase, > + MemorySize > + ); > +} > + > +/** > + Create memory range resource HOB using memory base > + address and top address of the memory range. > + > + @param MemoryBase Memory range base address. > + @param MemoryLimit Memory range size. > + > +**/ > +STATIC > +VOID > +AddMemoryRangeHob ( > + IN EFI_PHYSICAL_ADDRESS MemoryBase, > + IN EFI_PHYSICAL_ADDRESS MemoryLimit > + ) > +{ > + AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase)); > +} > + > +/** > + Publish system RAM and reserve memory regions. > + > +**/ > +STATIC > +VOID > +InitializeRamRegions ( > + IN EFI_PHYSICAL_ADDRESS SystemMemoryBase, > + IN UINT64 SystemMemorySize > + ) > +{ > + AddMemoryRangeHob ( > + SystemMemoryBase, > + SystemMemoryBase + SystemMemorySize > + ); > +} > + > +/** Get the number of cells for a given property > + > + @param[in] Fdt Pointer to Device Tree (DTB) > + @param[in] Node Node > + @param[in] Name Name of the property > + > + @return Number of cells. > +**/ > +STATIC > +INT32 > +GetNumCells ( > + IN VOID *Fdt, > + IN INT32 Node, > + IN CONST CHAR8 *Name > + ) > +{ > + CONST INT32 *Prop; > + INT32 Len; > + UINT32 Val; > + > + Prop = fdt_getprop (Fdt, Node, Name, &Len); > + if (Prop == NULL) { > + return Len; > + } > + > + if (Len != sizeof (*Prop)) { > + return -FDT_ERR_BADNCELLS; > + } > + > + Val = fdt32_to_cpu (*Prop); > + if (Val > FDT_MAX_NCELLS) { > + return -FDT_ERR_BADNCELLS; > + } > + > + return (INT32)Val; > +} > + > +/** Mark reserved memory ranges in the EFI memory map > + > + * As per DT spec v0.4 Section 3.5.4, > + * "Reserved regions with the no-map property must be listed in the > + * memory map with type EfiReservedMemoryType. All other reserved > + * regions must be listed with type EfiBootServicesData." > + > + @param FdtPointer Pointer to FDT > + > +**/ > +STATIC > +VOID > +AddReservedMemoryMap ( > + IN VOID *FdtPointer > + ) > +{ > + CONST INT32 *RegProp; > + INT32 Node; > + INT32 SubNode; > + INT32 Len; > + EFI_PHYSICAL_ADDRESS Addr; > + UINT64 Size; > + INTN NumRsv, i; > + INT32 NumAddrCells, NumSizeCells; > + > + NumRsv = fdt_num_mem_rsv (FdtPointer); > + > + /* Look for an existing entry and add it to the efi mem map. */ > + for (i = 0; i < NumRsv; i++) { > + if (fdt_get_mem_rsv (FdtPointer, i, &Addr, &Size) != 0) { > + continue; > + } > + > + BuildMemoryAllocationHob ( > + Addr, > + Size, > + EfiReservedMemoryType > + ); > + } > + > + /* process reserved-memory */ > + Node = fdt_subnode_offset (FdtPointer, 0, "reserved-memory"); > + if (Node >= 0) { > + NumAddrCells = GetNumCells (FdtPointer, Node, "#address-cells"); > + if (NumAddrCells <= 0) { > + return; > + } > + > + NumSizeCells = GetNumCells (FdtPointer, Node, "#size-cells"); > + if (NumSizeCells <= 0) { > + return; > + } > + > + fdt_for_each_subnode (SubNode, FdtPointer, Node) { > + RegProp = fdt_getprop (FdtPointer, SubNode, "reg", &Len); > + > + if ((RegProp != 0) && (Len == ((NumAddrCells + NumSizeCells) * sizeof (INT32)))) { > + Addr = fdt32_to_cpu (RegProp[0]); > + > + if (NumAddrCells > 1) { > + Addr = (Addr << 32) | fdt32_to_cpu (RegProp[1]); > + } > + > + RegProp += NumAddrCells; > + Size = fdt32_to_cpu (RegProp[0]); > + > + if (NumSizeCells > 1) { > + Size = (Size << 32) | fdt32_to_cpu (RegProp[1]); > + } > + > + DEBUG (( > + DEBUG_INFO, > + "%a: Adding Reserved Memory Addr = 0x%llx, Size = 0x%llx\n", > + __func__, > + Addr, > + Size > + )); > + > + if (fdt_getprop (FdtPointer, SubNode, "no-map", &Len)) { Ensure you document that OpenSBI 1.3/1.3.1 should be used which fixed its no-map issue. Otherwise, you can get into some issues in linux kernel. Acked-by: Sunil V L -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#108711): https://edk2.groups.io/g/devel/message/108711 Mute This Topic: https://groups.io/mt/101213494/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=-=-=-=-=-=-=-=-=-=-=-